EESchema-LIBRARY Version 2.3 29/04/2008-12:21:02 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 170 # # Dev Name: 4000D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4000D IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4025 F0 "IC" 100 125 50 H V L B F1 "4000D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 0 100 0 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 1 1 I X I1 4 -300 0 200 R 40 40 1 1 I X I2 5 -300 -100 200 R 40 40 1 1 I X O 6 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4025 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 0 100 0 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 200 -100 -200 X I0 13 -300 100 200 R 40 40 2 1 I X I1 12 -300 0 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X O 10 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4009 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 8 -400 0 200 R 40 40 3 1 I X O 9 400 0 200 L 40 40 3 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4000N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4000N IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4025 F0 "IC" 100 125 50 H V L B F1 "4000N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 0 100 0 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 1 1 I X I1 4 -300 0 200 R 40 40 1 1 I X I2 5 -300 -100 200 R 40 40 1 1 I X O 6 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4025 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 0 100 0 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 200 -100 -200 X I0 13 -300 100 200 R 40 40 2 1 I X I1 12 -300 0 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X O 10 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4009 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 8 -400 0 200 R 40 40 3 1 I X O 9 400 0 200 L 40 40 3 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4001D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4001D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4001 F0 "IC" 100 125 50 H V L B F1 "4001D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 -200 -100 200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4001 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 -200 -100 200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4001 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 -200 -100 200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4001 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 100 70 100 P 2 4 0 0 -100 -100 70 -100 P 2 4 0 0 -100 -200 -100 200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4001N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4001N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4001 F0 "IC" 100 125 50 H V L B F1 "4001N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 -200 -100 200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4001 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 -200 -100 200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4001 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 -200 -100 200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4001 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 100 70 100 P 2 4 0 0 -100 -100 70 -100 P 2 4 0 0 -100 -200 -100 200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4002D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4002D IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4002 F0 "IC" 150 200 50 H V L B F1 "4002D" 150 -275 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 200 70 200 P 2 1 0 0 -100 100 100 100 P 2 1 0 0 -100 -100 100 -100 P 2 1 0 0 -100 -200 70 -200 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4002 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 200 70 200 P 2 2 0 0 -100 100 100 100 P 2 2 0 0 -100 -100 100 -100 P 2 2 0 0 -100 -200 70 -200 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4002N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4002N IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4002 F0 "IC" 150 200 50 H V L B F1 "4002N" 150 -275 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 200 70 200 P 2 1 0 0 -100 100 100 100 P 2 1 0 0 -100 -100 100 -100 P 2 1 0 0 -100 -200 70 -200 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4002 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 200 70 200 P 2 2 0 0 -100 100 100 100 P 2 2 0 0 -100 -100 100 -100 P 2 2 0 0 -100 -200 70 -200 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4006D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4006D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4006 F0 "IC" -300 425 50 H V L B F1 "4006D" -300 -500 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X CLK 3 -500 -300 200 R 40 40 1 1 I C X D1 1 -500 300 200 R 40 40 1 1 I X D1+4 13 500 300 200 L 40 40 1 1 O X D2 4 -500 200 200 R 40 40 1 1 I X D2+4 11 500 200 200 L 40 40 1 1 O X D2+5 12 500 100 200 L 40 40 1 1 O X D3 5 -500 0 200 R 40 40 1 1 I X D3+4 10 500 0 200 L 40 40 1 1 O X D4 6 -500 -100 200 R 40 40 1 1 I X D4+4 8 500 -100 200 L 40 40 1 1 O X D4+5 9 500 -200 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4006N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4006N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4006 F0 "IC" -300 425 50 H V L B F1 "4006N" -300 -500 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X CLK 3 -500 -300 200 R 40 40 1 1 I C X D1 1 -500 300 200 R 40 40 1 1 I X D1+4 13 500 300 200 L 40 40 1 1 O X D2 4 -500 200 200 R 40 40 1 1 I X D2+4 11 500 200 200 L 40 40 1 1 O X D2+5 12 500 100 200 L 40 40 1 1 O X D3 5 -500 0 200 R 40 40 1 1 I X D3+4 10 500 0 200 L 40 40 1 1 O X D4 6 -500 -100 200 R 40 40 1 1 I X D4+4 8 500 -100 200 L 40 40 1 1 O X D4+5 9 500 -200 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4007D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF 4007D IC 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: 4007 F0 "IC" -300 725 50 H V L B F1 "4007D" -300 -900 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X 1A 3 -500 400 200 R 40 40 1 1 I X 1DN 5 500 400 200 L 40 40 1 1 C X 1DP 1 500 500 200 L 40 40 1 1 C X 1SN 4 500 300 200 L 40 40 1 1 C X 1SP 2 500 600 200 L 40 40 1 1 C X 2A 6 -500 100 200 R 40 40 1 1 I X 2DN 8 500 0 200 L 40 40 1 1 B X 2DP 13 500 100 200 L 40 40 1 1 B X 3A 10 -500 -300 200 R 40 40 1 1 I X 3SN 9 500 -400 200 L 40 40 1 1 B X 3SP 11 500 -200 200 L 40 40 1 1 B X 3Y 12 500 -300 200 L 40 40 1 1 B X VDD 14 500 -600 200 L 40 40 1 1 I X VSS 7 500 -700 200 L 40 40 1 1 I ENDDRAW ENDDEF # # Dev Name: 4007N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF 4007N IC 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: 4007 F0 "IC" -300 725 50 H V L B F1 "4007N" -300 -900 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X 1A 3 -500 400 200 R 40 40 1 1 I X 1DN 5 500 400 200 L 40 40 1 1 C X 1DP 1 500 500 200 L 40 40 1 1 C X 1SN 4 500 300 200 L 40 40 1 1 C X 1SP 2 500 600 200 L 40 40 1 1 C X 2A 6 -500 100 200 R 40 40 1 1 I X 2DN 8 500 0 200 L 40 40 1 1 B X 2DP 13 500 100 200 L 40 40 1 1 B X 3A 10 -500 -300 200 R 40 40 1 1 I X 3SN 9 500 -400 200 L 40 40 1 1 B X 3SP 11 500 -200 200 L 40 40 1 1 B X 3Y 12 500 -300 200 L 40 40 1 1 B X VDD 14 500 -600 200 L 40 40 1 1 I X VSS 7 500 -700 200 L 40 40 1 1 I ENDDRAW ENDDEF # # Dev Name: 4008D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4008D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4008 F0 "IC" -300 525 50 H V L B F1 "4008D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X A1 7 -500 400 200 R 40 40 1 1 I X A2 5 -500 300 200 R 40 40 1 1 I X A3 3 -500 200 200 R 40 40 1 1 I X A4 1 -500 100 200 R 40 40 1 1 I X B1 6 -500 0 200 R 40 40 1 1 I X B2 4 -500 -100 200 R 40 40 1 1 I X B3 2 -500 -200 200 R 40 40 1 1 I X B4 15 -500 -300 200 R 40 40 1 1 I X CI 9 -500 -500 200 R 40 40 1 1 I X CO 14 500 -500 200 L 40 40 1 1 O X S1 10 500 400 200 L 40 40 1 1 O X S2 11 500 300 200 L 40 40 1 1 O X S3 12 500 200 200 L 40 40 1 1 O X S4 13 500 100 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4008N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4008N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4008 F0 "IC" -300 525 50 H V L B F1 "4008N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X A1 7 -500 400 200 R 40 40 1 1 I X A2 5 -500 300 200 R 40 40 1 1 I X A3 3 -500 200 200 R 40 40 1 1 I X A4 1 -500 100 200 R 40 40 1 1 I X B1 6 -500 0 200 R 40 40 1 1 I X B2 4 -500 -100 200 R 40 40 1 1 I X B3 2 -500 -200 200 R 40 40 1 1 I X B4 15 -500 -300 200 R 40 40 1 1 I X CI 9 -500 -500 200 R 40 40 1 1 I X CO 14 500 -500 200 L 40 40 1 1 O X S1 10 500 400 200 L 40 40 1 1 O X S2 11 500 300 200 L 40 40 1 1 O X S3 12 500 200 200 L 40 40 1 1 O X S4 13 500 100 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4009D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4009D IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4009 F0 "IC" 100 125 50 H V L B F1 "4009D" 100 -200 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4009 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4009 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4009 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 4009 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 4009 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4009N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4009N IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4009 F0 "IC" 100 125 50 H V L B F1 "4009N" 100 -200 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4009 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4009 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4009 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 4009 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 4009 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4010D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4010D IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4010 F0 "IC" 100 125 50 H V L B F1 "4010D" 100 -200 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4010 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4010 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4010 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O # Gate Name: E # Symbol Name: 4010 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O # Gate Name: F # Symbol Name: 4010 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4010N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4010N IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4010 F0 "IC" 100 125 50 H V L B F1 "4010N" 100 -200 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4010 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4010 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4010 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O # Gate Name: E # Symbol Name: 4010 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O # Gate Name: F # Symbol Name: 4010 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4011D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4011D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4011 F0 "IC" 100 125 50 H V L B F1 "4011D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4011 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4011 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4011 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 200 -100 -200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4011N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4011N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4011 F0 "IC" 100 125 50 H V L B F1 "4011N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4011 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4011 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4011 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 200 -100 -200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4012D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4012D IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4012 F0 "IC" 100 225 50 H V L B F1 "4012D" 100 -300 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4012 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4012N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4012N IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4012 F0 "IC" 100 225 50 H V L B F1 "4012N" 100 -300 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4012 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4013D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4013D IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4013 F0 "IC" -300 425 50 H V L B F1 "4013D" -300 -400 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 300 -300 P 2 1 0 0 300 -300 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -300 X CLK 3 -500 0 200 R 40 40 1 1 I C X D 5 -500 100 200 R 40 40 1 1 I X Q 1 500 300 200 L 40 40 1 1 O X Q\ 2 500 -200 200 L 40 40 1 1 O X R 4 -500 -200 200 R 40 40 1 1 I X S 6 -500 300 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4013 P 2 2 0 0 -300 -300 300 -300 P 2 2 0 0 300 -300 300 400 P 2 2 0 0 300 400 -300 400 P 2 2 0 0 -300 400 -300 -300 X CLK 11 -500 0 200 R 40 40 2 1 I C X D 9 -500 100 200 R 40 40 2 1 I X Q 13 500 300 200 L 40 40 2 1 O X Q\ 12 500 -200 200 L 40 40 2 1 O X R 10 -500 -200 200 R 40 40 2 1 I X S 8 -500 300 200 R 40 40 2 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4013N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4013N IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4013 F0 "IC" -300 425 50 H V L B F1 "4013N" -300 -400 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 300 -300 P 2 1 0 0 300 -300 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -300 X CLK 3 -500 0 200 R 40 40 1 1 I C X D 5 -500 100 200 R 40 40 1 1 I X Q 1 500 300 200 L 40 40 1 1 O X Q\ 2 500 -200 200 L 40 40 1 1 O X R 4 -500 -200 200 R 40 40 1 1 I X S 6 -500 300 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4013 P 2 2 0 0 -300 -300 300 -300 P 2 2 0 0 300 -300 300 400 P 2 2 0 0 300 400 -300 400 P 2 2 0 0 -300 400 -300 -300 X CLK 11 -500 0 200 R 40 40 2 1 I C X D 9 -500 100 200 R 40 40 2 1 I X Q 13 500 300 200 L 40 40 2 1 O X Q\ 12 500 -200 200 L 40 40 2 1 O X R 10 -500 -200 200 R 40 40 2 1 I X S 8 -500 300 200 R 40 40 2 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4014D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4014D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4014 F0 "IC" -300 625 50 H V L B F1 "4014D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X CLK 10 -500 -500 200 R 40 40 1 1 I C X P/S\ 9 -500 -600 200 R 40 40 1 1 I X P1 7 -500 400 200 R 40 40 1 1 I X P2 6 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 4 -500 100 200 R 40 40 1 1 I X P5 13 -500 0 200 R 40 40 1 1 I X P6 14 -500 -100 200 R 40 40 1 1 I X P7 15 -500 -200 200 R 40 40 1 1 I X P8 1 -500 -300 200 R 40 40 1 1 I X Q6 2 500 -100 200 L 40 40 1 1 O X Q7 12 500 -200 200 L 40 40 1 1 O X Q8 3 500 -300 200 L 40 40 1 1 O X SI 11 -500 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4014N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4014N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4014 F0 "IC" -300 625 50 H V L B F1 "4014N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X CLK 10 -500 -500 200 R 40 40 1 1 I C X P/S\ 9 -500 -600 200 R 40 40 1 1 I X P1 7 -500 400 200 R 40 40 1 1 I X P2 6 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 4 -500 100 200 R 40 40 1 1 I X P5 13 -500 0 200 R 40 40 1 1 I X P6 14 -500 -100 200 R 40 40 1 1 I X P7 15 -500 -200 200 R 40 40 1 1 I X P8 1 -500 -300 200 R 40 40 1 1 I X Q6 2 500 -100 200 L 40 40 1 1 O X Q7 12 500 -200 200 L 40 40 1 1 O X Q8 3 500 -300 200 L 40 40 1 1 O X SI 11 -500 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4015D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4015D IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4015 F0 "IC" -300 225 50 H V L B F1 "4015D" -300 -400 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 300 -300 P 2 1 0 0 300 -300 300 200 P 2 1 0 0 300 200 -300 200 P 2 1 0 0 -300 200 -300 -300 X CLK 1 -500 -100 200 R 40 40 1 1 I C X D 15 -500 100 200 R 40 40 1 1 I X QA 13 500 100 200 L 40 40 1 1 O X QB 12 500 0 200 L 40 40 1 1 O X QC 11 500 -100 200 L 40 40 1 1 O X QD 2 500 -200 200 L 40 40 1 1 O X RES 14 -500 -200 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4015 P 2 2 0 0 -300 -300 300 -300 P 2 2 0 0 300 -300 300 200 P 2 2 0 0 300 200 -300 200 P 2 2 0 0 -300 200 -300 -300 X CLK 9 -500 -100 200 R 40 40 2 1 I C X D 7 -500 100 200 R 40 40 2 1 I X QA 5 500 100 200 L 40 40 2 1 O X QB 4 500 0 200 L 40 40 2 1 O X QC 3 500 -100 200 L 40 40 2 1 O X QD 10 500 -200 200 L 40 40 2 1 O X RES 6 -500 -200 200 R 40 40 2 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 16 0 300 200 D 40 40 3 1 W X VSS 8 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4015N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4015N IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4015 F0 "IC" -300 225 50 H V L B F1 "4015N" -300 -400 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 300 -300 P 2 1 0 0 300 -300 300 200 P 2 1 0 0 300 200 -300 200 P 2 1 0 0 -300 200 -300 -300 X CLK 1 -500 -100 200 R 40 40 1 1 I C X D 15 -500 100 200 R 40 40 1 1 I X QA 13 500 100 200 L 40 40 1 1 O X QB 12 500 0 200 L 40 40 1 1 O X QC 11 500 -100 200 L 40 40 1 1 O X QD 2 500 -200 200 L 40 40 1 1 O X RES 14 -500 -200 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4015 P 2 2 0 0 -300 -300 300 -300 P 2 2 0 0 300 -300 300 200 P 2 2 0 0 300 200 -300 200 P 2 2 0 0 -300 200 -300 -300 X CLK 9 -500 -100 200 R 40 40 2 1 I C X D 7 -500 100 200 R 40 40 2 1 I X QA 5 500 100 200 L 40 40 2 1 O X QB 4 500 0 200 L 40 40 2 1 O X QC 3 500 -100 200 L 40 40 2 1 O X QD 10 500 -200 200 L 40 40 2 1 O X RES 6 -500 -200 200 R 40 40 2 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 16 0 300 200 D 40 40 3 1 W X VSS 8 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4016D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4016D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4016 F0 "IC" -300 225 50 H V L B F1 "4016D" -300 -300 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -200 300 -200 P 2 1 0 0 300 -200 300 200 P 2 1 0 0 300 200 -300 200 P 2 1 0 0 -300 200 -300 -200 X A 1 -500 100 200 R 40 40 1 1 T X B 2 500 100 200 L 40 40 1 1 T X C 13 -500 -100 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4016 P 2 2 0 0 -300 -200 300 -200 P 2 2 0 0 300 -200 300 200 P 2 2 0 0 300 200 -300 200 P 2 2 0 0 -300 200 -300 -200 X A 11 -500 100 200 R 40 40 2 1 T X B 10 500 100 200 L 40 40 2 1 T X C 12 -500 -100 200 R 40 40 2 1 I # Gate Name: C # Symbol Name: 4016 P 2 3 0 0 -300 -200 300 -200 P 2 3 0 0 300 -200 300 200 P 2 3 0 0 300 200 -300 200 P 2 3 0 0 -300 200 -300 -200 X A 4 -500 100 200 R 40 40 3 1 T X B 3 500 100 200 L 40 40 3 1 T X C 5 -500 -100 200 R 40 40 3 1 I # Gate Name: D # Symbol Name: 4016 P 2 4 0 0 -300 -200 300 -200 P 2 4 0 0 300 -200 300 200 P 2 4 0 0 300 200 -300 200 P 2 4 0 0 -300 200 -300 -200 X A 8 -500 100 200 R 40 40 4 1 T X B 9 500 100 200 L 40 40 4 1 T X C 6 -500 -100 200 R 40 40 4 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4016N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4016N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4016 F0 "IC" -300 225 50 H V L B F1 "4016N" -300 -300 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -200 300 -200 P 2 1 0 0 300 -200 300 200 P 2 1 0 0 300 200 -300 200 P 2 1 0 0 -300 200 -300 -200 X A 1 -500 100 200 R 40 40 1 1 T X B 2 500 100 200 L 40 40 1 1 T X C 13 -500 -100 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4016 P 2 2 0 0 -300 -200 300 -200 P 2 2 0 0 300 -200 300 200 P 2 2 0 0 300 200 -300 200 P 2 2 0 0 -300 200 -300 -200 X A 11 -500 100 200 R 40 40 2 1 T X B 10 500 100 200 L 40 40 2 1 T X C 12 -500 -100 200 R 40 40 2 1 I # Gate Name: C # Symbol Name: 4016 P 2 3 0 0 -300 -200 300 -200 P 2 3 0 0 300 -200 300 200 P 2 3 0 0 300 200 -300 200 P 2 3 0 0 -300 200 -300 -200 X A 4 -500 100 200 R 40 40 3 1 T X B 3 500 100 200 L 40 40 3 1 T X C 5 -500 -100 200 R 40 40 3 1 I # Gate Name: D # Symbol Name: 4016 P 2 4 0 0 -300 -200 300 -200 P 2 4 0 0 300 -200 300 200 P 2 4 0 0 300 200 -300 200 P 2 4 0 0 -300 200 -300 -200 X A 8 -500 100 200 R 40 40 4 1 T X B 9 500 100 200 L 40 40 4 1 T X C 6 -500 -100 200 R 40 40 4 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4017D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4017D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4017 F0 "IC" -300 625 50 H V L B F1 "4017D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X CLK 14 -500 0 200 R 40 40 1 1 I C X CO 12 500 -600 200 L 40 40 1 1 O X ENA 13 -500 -400 200 R 40 40 1 1 I I X Q0 3 500 500 200 L 40 40 1 1 O X Q1 2 500 400 200 L 40 40 1 1 O X Q2 4 500 300 200 L 40 40 1 1 O X Q3 7 500 200 200 L 40 40 1 1 O X Q4 10 500 100 200 L 40 40 1 1 O X Q5 1 500 0 200 L 40 40 1 1 O X Q6 5 500 -100 200 L 40 40 1 1 O X Q7 6 500 -200 200 L 40 40 1 1 O X Q8 9 500 -300 200 L 40 40 1 1 O X Q9 11 500 -400 200 L 40 40 1 1 O X RES 15 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4017N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4017N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4017 F0 "IC" -300 625 50 H V L B F1 "4017N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X CLK 14 -500 0 200 R 40 40 1 1 I C X CO 12 500 -600 200 L 40 40 1 1 O X ENA 13 -500 -400 200 R 40 40 1 1 I I X Q0 3 500 500 200 L 40 40 1 1 O X Q1 2 500 400 200 L 40 40 1 1 O X Q2 4 500 300 200 L 40 40 1 1 O X Q3 7 500 200 200 L 40 40 1 1 O X Q4 10 500 100 200 L 40 40 1 1 O X Q5 1 500 0 200 L 40 40 1 1 O X Q6 5 500 -100 200 L 40 40 1 1 O X Q7 6 500 -200 200 L 40 40 1 1 O X Q8 9 500 -300 200 L 40 40 1 1 O X Q9 11 500 -400 200 L 40 40 1 1 O X RES 15 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4018D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4018D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4018 F0 "IC" -300 525 50 H V L B F1 "4018D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 14 -500 -300 200 R 40 40 1 1 I C X D 1 -500 -200 200 R 40 40 1 1 I X J1 2 -500 400 200 R 40 40 1 1 I X J2 3 -500 300 200 R 40 40 1 1 I X J3 7 -500 200 200 R 40 40 1 1 I X J4 9 -500 100 200 R 40 40 1 1 I X J5 12 -500 0 200 R 40 40 1 1 I X PRE 10 -500 -400 200 R 40 40 1 1 I X Q1 5 500 400 200 L 40 40 1 1 O I X Q2 4 500 300 200 L 40 40 1 1 O I X Q3 6 500 200 200 L 40 40 1 1 O I X Q4 11 500 100 200 L 40 40 1 1 O I X Q5 13 500 0 200 L 40 40 1 1 O I X RES 15 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4018N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4018N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4018 F0 "IC" -300 525 50 H V L B F1 "4018N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 14 -500 -300 200 R 40 40 1 1 I C X D 1 -500 -200 200 R 40 40 1 1 I X J1 2 -500 400 200 R 40 40 1 1 I X J2 3 -500 300 200 R 40 40 1 1 I X J3 7 -500 200 200 R 40 40 1 1 I X J4 9 -500 100 200 R 40 40 1 1 I X J5 12 -500 0 200 R 40 40 1 1 I X PRE 10 -500 -400 200 R 40 40 1 1 I X Q1 5 500 400 200 L 40 40 1 1 O I X Q2 4 500 300 200 L 40 40 1 1 O I X Q3 6 500 200 200 L 40 40 1 1 O I X Q4 11 500 100 200 L 40 40 1 1 O I X Q5 13 500 0 200 L 40 40 1 1 O I X RES 15 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4019D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4019D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4019 F0 "IC" -300 625 50 H V L B F1 "4019D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A1 6 -500 500 200 R 40 40 1 1 I X A2 4 -500 300 200 R 40 40 1 1 I X A3 2 -500 100 200 R 40 40 1 1 I X A4 15 -500 -100 200 R 40 40 1 1 I X B1 7 -500 400 200 R 40 40 1 1 I X B2 5 -500 200 200 R 40 40 1 1 I X B3 3 -500 0 200 R 40 40 1 1 I X B4 1 -500 -200 200 R 40 40 1 1 I X D1 10 500 500 200 L 40 40 1 1 O X D2 11 500 300 200 L 40 40 1 1 O X D3 12 500 100 200 L 40 40 1 1 O X D4 13 500 -100 200 L 40 40 1 1 O X G1 14 -500 -400 200 R 40 40 1 1 I I X G2 9 -500 -500 200 R 40 40 1 1 I I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4019N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4019N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4019 F0 "IC" -300 625 50 H V L B F1 "4019N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A1 6 -500 500 200 R 40 40 1 1 I X A2 4 -500 300 200 R 40 40 1 1 I X A3 2 -500 100 200 R 40 40 1 1 I X A4 15 -500 -100 200 R 40 40 1 1 I X B1 7 -500 400 200 R 40 40 1 1 I X B2 5 -500 200 200 R 40 40 1 1 I X B3 3 -500 0 200 R 40 40 1 1 I X B4 1 -500 -200 200 R 40 40 1 1 I X D1 10 500 500 200 L 40 40 1 1 O X D2 11 500 300 200 L 40 40 1 1 O X D3 12 500 100 200 L 40 40 1 1 O X D4 13 500 -100 200 L 40 40 1 1 O X G1 14 -500 -400 200 R 40 40 1 1 I I X G2 9 -500 -500 200 R 40 40 1 1 I I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4020D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4020D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4020 F0 "IC" -300 625 50 H V L B F1 "4020D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X P1 10 -500 500 200 R 40 40 1 1 I C X Q1 9 500 500 200 L 40 40 1 1 O X Q4 7 500 400 200 L 40 40 1 1 O X Q5 5 500 300 200 L 40 40 1 1 O X Q6 4 500 200 200 L 40 40 1 1 O X Q7 6 500 100 200 L 40 40 1 1 O X Q8 13 500 0 200 L 40 40 1 1 O X Q9 12 500 -100 200 L 40 40 1 1 O X Q10 14 500 -200 200 L 40 40 1 1 O X Q11 15 500 -300 200 L 40 40 1 1 O X Q12 1 500 -400 200 L 40 40 1 1 O X Q13 2 500 -500 200 L 40 40 1 1 O X Q14 3 500 -600 200 L 40 40 1 1 O X RES 11 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4020N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4020N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4020 F0 "IC" -300 625 50 H V L B F1 "4020N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X P1 10 -500 500 200 R 40 40 1 1 I C X Q1 9 500 500 200 L 40 40 1 1 O X Q4 7 500 400 200 L 40 40 1 1 O X Q5 5 500 300 200 L 40 40 1 1 O X Q6 4 500 200 200 L 40 40 1 1 O X Q7 6 500 100 200 L 40 40 1 1 O X Q8 13 500 0 200 L 40 40 1 1 O X Q9 12 500 -100 200 L 40 40 1 1 O X Q10 14 500 -200 200 L 40 40 1 1 O X Q11 15 500 -300 200 L 40 40 1 1 O X Q12 1 500 -400 200 L 40 40 1 1 O X Q13 2 500 -500 200 L 40 40 1 1 O X Q14 3 500 -600 200 L 40 40 1 1 O X RES 11 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4021D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4021D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4021 F0 "IC" -300 725 50 H V L B F1 "4021D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -600 X CLK 10 -500 -400 200 R 40 40 1 1 I C X P/S\ 9 -500 -500 200 R 40 40 1 1 I X P1 7 -500 600 200 R 40 40 1 1 I X P2 6 -500 500 200 R 40 40 1 1 I X P3 5 -500 400 200 R 40 40 1 1 I X P4 4 -500 300 200 R 40 40 1 1 I X P5 13 -500 200 200 R 40 40 1 1 I X P6 14 -500 100 200 R 40 40 1 1 I X P7 15 -500 0 200 R 40 40 1 1 I X P8 1 -500 -100 200 R 40 40 1 1 I X Q6 2 500 600 200 L 40 40 1 1 O X Q7 12 500 400 200 L 40 40 1 1 O X Q8 3 500 200 200 L 40 40 1 1 O X SI 11 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4021N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4021N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4021 F0 "IC" -300 725 50 H V L B F1 "4021N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -600 X CLK 10 -500 -400 200 R 40 40 1 1 I C X P/S\ 9 -500 -500 200 R 40 40 1 1 I X P1 7 -500 600 200 R 40 40 1 1 I X P2 6 -500 500 200 R 40 40 1 1 I X P3 5 -500 400 200 R 40 40 1 1 I X P4 4 -500 300 200 R 40 40 1 1 I X P5 13 -500 200 200 R 40 40 1 1 I X P6 14 -500 100 200 R 40 40 1 1 I X P7 15 -500 0 200 R 40 40 1 1 I X P8 1 -500 -100 200 R 40 40 1 1 I X Q6 2 500 600 200 L 40 40 1 1 O X Q7 12 500 400 200 L 40 40 1 1 O X Q8 3 500 200 200 L 40 40 1 1 O X SI 11 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4022D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4022D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4022 F0 "IC" -300 525 50 H V L B F1 "4022D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 14 -500 0 200 R 40 40 1 1 I C X CLR 13 -500 400 200 R 40 40 1 1 I X CO 12 500 -500 200 L 40 40 1 1 O X Q0 2 500 400 200 L 40 40 1 1 O X Q1 1 500 300 200 L 40 40 1 1 O X Q2 3 500 200 200 L 40 40 1 1 O X Q3 7 500 100 200 L 40 40 1 1 O X Q4 11 500 0 200 L 40 40 1 1 O X Q5 4 500 -100 200 L 40 40 1 1 O X Q6 5 500 -200 200 L 40 40 1 1 O X Q7 10 500 -300 200 L 40 40 1 1 O X RES 15 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4022N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4022N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4022 F0 "IC" -300 525 50 H V L B F1 "4022N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 14 -500 0 200 R 40 40 1 1 I C X CLR 13 -500 400 200 R 40 40 1 1 I X CO 12 500 -500 200 L 40 40 1 1 O X Q0 2 500 400 200 L 40 40 1 1 O X Q1 1 500 300 200 L 40 40 1 1 O X Q2 3 500 200 200 L 40 40 1 1 O X Q3 7 500 100 200 L 40 40 1 1 O X Q4 11 500 0 200 L 40 40 1 1 O X Q5 4 500 -100 200 L 40 40 1 1 O X Q6 5 500 -200 200 L 40 40 1 1 O X Q7 10 500 -300 200 L 40 40 1 1 O X RES 15 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4023D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4023D IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4023 F0 "IC" 100 125 50 H V L B F1 "4023D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4023 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4023 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4023N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4023N IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4023 F0 "IC" 100 125 50 H V L B F1 "4023N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4023 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4023 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4024D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4024D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4024 F0 "IC" -300 425 50 H V L B F1 "4024D" -300 -500 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X CLK 1 -500 0 200 R 40 40 1 1 I C X Q1 12 500 300 200 L 40 40 1 1 O X Q2 11 500 200 200 L 40 40 1 1 O X Q3 9 500 100 200 L 40 40 1 1 O X Q4 6 500 0 200 L 40 40 1 1 O X Q5 5 500 -100 200 L 40 40 1 1 O X Q6 4 500 -200 200 L 40 40 1 1 O X Q7 3 500 -300 200 L 40 40 1 1 O X RES 2 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4024N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4024N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4024 F0 "IC" -300 425 50 H V L B F1 "4024N" -300 -500 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X CLK 1 -500 0 200 R 40 40 1 1 I C X Q1 12 500 300 200 L 40 40 1 1 O X Q2 11 500 200 200 L 40 40 1 1 O X Q3 9 500 100 200 L 40 40 1 1 O X Q4 6 500 0 200 L 40 40 1 1 O X Q5 5 500 -100 200 L 40 40 1 1 O X Q6 4 500 -200 200 L 40 40 1 1 O X Q7 3 500 -300 200 L 40 40 1 1 O X RES 2 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4025D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4025D IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4025 F0 "IC" 100 125 50 H V L B F1 "4025D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 0 100 0 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4025 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 0 100 0 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4025 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 0 100 0 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4025N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4025N IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4025 F0 "IC" 100 125 50 H V L B F1 "4025N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 0 100 0 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4025 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 0 100 0 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4025 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 0 100 0 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4026D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4026D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4026 F0 "IC" -300 625 50 H V L B F1 "4026D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A 10 500 500 200 L 40 40 1 1 O X B 12 500 400 200 L 40 40 1 1 O X C 13 500 300 200 L 40 40 1 1 O X CI 2 -500 -300 200 R 40 40 1 1 I X CLK 1 -500 0 200 R 40 40 1 1 I C X CO 5 500 -300 200 L 40 40 1 1 O X D 9 500 200 200 L 40 40 1 1 O X DEI 3 -500 -400 200 R 40 40 1 1 I X DEO 4 500 -400 200 L 40 40 1 1 O X E 11 500 100 200 L 40 40 1 1 O X F 6 500 0 200 L 40 40 1 1 O X G 7 500 -100 200 L 40 40 1 1 O X RES 15 -500 -500 200 R 40 40 1 1 I X UCS 14 500 -500 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4026N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4026N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4026 F0 "IC" -300 625 50 H V L B F1 "4026N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A 10 500 500 200 L 40 40 1 1 O X B 12 500 400 200 L 40 40 1 1 O X C 13 500 300 200 L 40 40 1 1 O X CI 2 -500 -300 200 R 40 40 1 1 I X CLK 1 -500 0 200 R 40 40 1 1 I C X CO 5 500 -300 200 L 40 40 1 1 O X D 9 500 200 200 L 40 40 1 1 O X DEI 3 -500 -400 200 R 40 40 1 1 I X DEO 4 500 -400 200 L 40 40 1 1 O X E 11 500 100 200 L 40 40 1 1 O X F 6 500 0 200 L 40 40 1 1 O X G 7 500 -100 200 L 40 40 1 1 O X RES 15 -500 -500 200 R 40 40 1 1 I X UCS 14 500 -500 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4027D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4027D IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4027 F0 "IC" -300 325 50 H V L B F1 "4027D" -300 -400 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 300 -300 P 2 1 0 0 300 -300 300 300 P 2 1 0 0 300 300 -300 300 P 2 1 0 0 -300 300 -300 -300 X CLK 3 -500 0 200 R 40 40 1 1 I C X J 6 -500 100 200 R 40 40 1 1 I X K 5 -500 -100 200 R 40 40 1 1 I X Q 1 500 200 200 L 40 40 1 1 O X Q\ 2 500 -200 200 L 40 40 1 1 O X R 4 -500 -200 200 R 40 40 1 1 I X S 7 -500 200 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4027 P 2 2 0 0 -300 -300 300 -300 P 2 2 0 0 300 -300 300 300 P 2 2 0 0 300 300 -300 300 P 2 2 0 0 -300 300 -300 -300 X CLK 13 -500 0 200 R 40 40 2 1 I C X J 10 -500 100 200 R 40 40 2 1 I X K 11 -500 -100 200 R 40 40 2 1 I X Q 15 500 200 200 L 40 40 2 1 O X Q\ 14 500 -200 200 L 40 40 2 1 O X R 12 -500 -200 200 R 40 40 2 1 I X S 9 -500 200 200 R 40 40 2 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 16 0 300 200 D 40 40 3 1 W X VSS 8 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4027N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4027N IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4027 F0 "IC" -300 325 50 H V L B F1 "4027N" -300 -400 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 300 -300 P 2 1 0 0 300 -300 300 300 P 2 1 0 0 300 300 -300 300 P 2 1 0 0 -300 300 -300 -300 X CLK 3 -500 0 200 R 40 40 1 1 I C X J 6 -500 100 200 R 40 40 1 1 I X K 5 -500 -100 200 R 40 40 1 1 I X Q 1 500 200 200 L 40 40 1 1 O X Q\ 2 500 -200 200 L 40 40 1 1 O X R 4 -500 -200 200 R 40 40 1 1 I X S 7 -500 200 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4027 P 2 2 0 0 -300 -300 300 -300 P 2 2 0 0 300 -300 300 300 P 2 2 0 0 300 300 -300 300 P 2 2 0 0 -300 300 -300 -300 X CLK 13 -500 0 200 R 40 40 2 1 I C X J 10 -500 100 200 R 40 40 2 1 I X K 11 -500 -100 200 R 40 40 2 1 I X Q 15 500 200 200 L 40 40 2 1 O X Q\ 14 500 -200 200 L 40 40 2 1 O X R 12 -500 -200 200 R 40 40 2 1 I X S 9 -500 200 200 R 40 40 2 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 16 0 300 200 D 40 40 3 1 W X VSS 8 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4028D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4028D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4028 F0 "IC" -300 525 50 H V L B F1 "4028D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X A 10 -500 100 200 R 40 40 1 1 I X B 13 -500 0 200 R 40 40 1 1 I X C 12 -500 -100 200 R 40 40 1 1 I X D 11 -500 -200 200 R 40 40 1 1 I X Q0 3 500 400 200 L 40 40 1 1 O X Q1 14 500 300 200 L 40 40 1 1 O X Q2 2 500 200 200 L 40 40 1 1 O X Q3 15 500 100 200 L 40 40 1 1 O X Q4 1 500 0 200 L 40 40 1 1 O X Q5 6 500 -100 200 L 40 40 1 1 O X Q6 7 500 -200 200 L 40 40 1 1 O X Q7 4 500 -300 200 L 40 40 1 1 O X Q8 9 500 -400 200 L 40 40 1 1 O X Q9 5 500 -500 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4028N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4028N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4028 F0 "IC" -300 525 50 H V L B F1 "4028N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X A 10 -500 100 200 R 40 40 1 1 I X B 13 -500 0 200 R 40 40 1 1 I X C 12 -500 -100 200 R 40 40 1 1 I X D 11 -500 -200 200 R 40 40 1 1 I X Q0 3 500 400 200 L 40 40 1 1 O X Q1 14 500 300 200 L 40 40 1 1 O X Q2 2 500 200 200 L 40 40 1 1 O X Q3 15 500 100 200 L 40 40 1 1 O X Q4 1 500 0 200 L 40 40 1 1 O X Q5 6 500 -100 200 L 40 40 1 1 O X Q6 7 500 -200 200 L 40 40 1 1 O X Q7 4 500 -300 200 L 40 40 1 1 O X Q8 9 500 -400 200 L 40 40 1 1 O X Q9 5 500 -500 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4029D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4029D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4029 F0 "IC" -300 525 50 H V L B F1 "4029D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X B/D\ 9 -500 -400 200 R 40 40 1 1 I X CI 5 -500 -200 200 R 40 40 1 1 I I X CLK 15 -500 -100 200 R 40 40 1 1 I C X CO 7 500 -100 200 L 40 40 1 1 O I X J1 4 -500 400 200 R 40 40 1 1 I X J2 12 -500 300 200 R 40 40 1 1 I X J3 13 -500 200 200 R 40 40 1 1 I X J4 3 -500 100 200 R 40 40 1 1 I X PE 1 -500 -300 200 R 40 40 1 1 I X Q1 6 500 400 200 L 40 40 1 1 O X Q2 11 500 300 200 L 40 40 1 1 O X Q3 14 500 200 200 L 40 40 1 1 O X Q4 2 500 100 200 L 40 40 1 1 O X U/D\ 10 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4029N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4029N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4029 F0 "IC" -300 525 50 H V L B F1 "4029N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X B/D\ 9 -500 -400 200 R 40 40 1 1 I X CI 5 -500 -200 200 R 40 40 1 1 I I X CLK 15 -500 -100 200 R 40 40 1 1 I C X CO 7 500 -100 200 L 40 40 1 1 O I X J1 4 -500 400 200 R 40 40 1 1 I X J2 12 -500 300 200 R 40 40 1 1 I X J3 13 -500 200 200 R 40 40 1 1 I X J4 3 -500 100 200 R 40 40 1 1 I X PE 1 -500 -300 200 R 40 40 1 1 I X Q1 6 500 400 200 L 40 40 1 1 O X Q2 11 500 300 200 L 40 40 1 1 O X Q3 14 500 200 200 L 40 40 1 1 O X Q4 2 500 100 200 L 40 40 1 1 O X U/D\ 10 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4030D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4030D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4030 F0 "IC" 100 125 50 H V L B F1 "4030D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 -200 -100 200 T 0 20 20 100 0 1 0 e X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4030 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 -200 -100 200 T 0 20 20 100 0 2 0 e X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4030 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 -200 -100 200 T 0 20 20 100 0 3 0 e X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4030 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 100 70 100 P 2 4 0 0 -100 -100 70 -100 P 2 4 0 0 -100 -200 -100 200 T 0 20 20 100 0 4 0 e X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4030N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4030N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4030 F0 "IC" 100 125 50 H V L B F1 "4030N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 -200 -100 200 T 0 20 20 100 0 1 0 e X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4030 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 -200 -100 200 T 0 20 20 100 0 2 0 e X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4030 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 -200 -100 200 T 0 20 20 100 0 3 0 e X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4030 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 100 70 100 P 2 4 0 0 -100 -100 70 -100 P 2 4 0 0 -100 -200 -100 200 T 0 20 20 100 0 4 0 e X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4031D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4031D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4031 F0 "IC" -300 425 50 H V L B F1 "4031D" -300 -500 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X CLK 2 -500 100 200 R 40 40 1 1 I C X DCO 9 500 -300 200 L 40 40 1 1 O X DIN 15 -500 -100 200 R 40 40 1 1 I X MC 10 -500 300 200 R 40 40 1 1 I X Q 6 500 300 200 L 40 40 1 1 O X Q\ 7 500 0 200 L 40 40 1 1 O X R 1 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4031N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4031N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4031 F0 "IC" -300 425 50 H V L B F1 "4031N" -300 -500 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X CLK 2 -500 100 200 R 40 40 1 1 I C X DCO 9 500 -300 200 L 40 40 1 1 O X DIN 15 -500 -100 200 R 40 40 1 1 I X MC 10 -500 300 200 R 40 40 1 1 I X Q 6 500 300 200 L 40 40 1 1 O X Q\ 7 500 0 200 L 40 40 1 1 O X R 1 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4032D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4032D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4032 F0 "IC" -300 725 50 H V L B F1 "4032D" -300 -900 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X A1 10 -500 600 200 R 40 40 1 1 I X A2 13 -500 200 200 R 40 40 1 1 I X A3 15 -500 -200 200 R 40 40 1 1 I X B1 11 -500 500 200 R 40 40 1 1 I X B2 12 -500 100 200 R 40 40 1 1 I X B3 14 -500 -300 200 R 40 40 1 1 I X CLK 3 -500 -600 200 R 40 40 1 1 I C X CR 6 -500 -700 200 R 40 40 1 1 I X I1 7 -500 400 200 R 40 40 1 1 I X I2 5 -500 0 200 R 40 40 1 1 I X I3 2 -500 -400 200 R 40 40 1 1 I X S1 9 500 500 200 L 40 40 1 1 O X S2 4 500 100 200 L 40 40 1 1 O X S3 1 500 -300 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4032N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4032N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4032 F0 "IC" -300 725 50 H V L B F1 "4032N" -300 -900 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X A1 10 -500 600 200 R 40 40 1 1 I X A2 13 -500 200 200 R 40 40 1 1 I X A3 15 -500 -200 200 R 40 40 1 1 I X B1 11 -500 500 200 R 40 40 1 1 I X B2 12 -500 100 200 R 40 40 1 1 I X B3 14 -500 -300 200 R 40 40 1 1 I X CLK 3 -500 -600 200 R 40 40 1 1 I C X CR 6 -500 -700 200 R 40 40 1 1 I X I1 7 -500 400 200 R 40 40 1 1 I X I2 5 -500 0 200 R 40 40 1 1 I X I3 2 -500 -400 200 R 40 40 1 1 I X S1 9 500 500 200 L 40 40 1 1 O X S2 4 500 100 200 L 40 40 1 1 O X S3 1 500 -300 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4033D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4033D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4033 F0 "IC" -300 425 50 H V L B F1 "4033D" -300 -600 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A 10 500 300 200 L 40 40 1 1 O X B 12 500 200 200 L 40 40 1 1 O X BI/RBO 4 -500 -100 200 R 40 40 1 1 I X C 13 500 100 200 L 40 40 1 1 O X CLK 1 -500 300 200 R 40 40 1 1 I C X CO 5 500 -400 200 L 40 40 1 1 O X D 9 500 0 200 L 40 40 1 1 O X E 11 500 -100 200 L 40 40 1 1 O X F 6 500 -200 200 L 40 40 1 1 O X G 7 500 -300 200 L 40 40 1 1 O X INH 2 -500 100 200 R 40 40 1 1 I X LT 14 -500 0 200 R 40 40 1 1 I X R 15 -500 -400 200 R 40 40 1 1 I X RBI 3 -500 -200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4033N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4033N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4033 F0 "IC" -300 425 50 H V L B F1 "4033N" -300 -600 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A 10 500 300 200 L 40 40 1 1 O X B 12 500 200 200 L 40 40 1 1 O X BI/RBO 4 -500 -100 200 R 40 40 1 1 I X C 13 500 100 200 L 40 40 1 1 O X CLK 1 -500 300 200 R 40 40 1 1 I C X CO 5 500 -400 200 L 40 40 1 1 O X D 9 500 0 200 L 40 40 1 1 O X E 11 500 -100 200 L 40 40 1 1 O X F 6 500 -200 200 L 40 40 1 1 O X G 7 500 -300 200 L 40 40 1 1 O X INH 2 -500 100 200 R 40 40 1 1 I X LT 14 -500 0 200 R 40 40 1 1 I X R 15 -500 -400 200 R 40 40 1 1 I X RBI 3 -500 -200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4034D # Package Name: SO24W # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4034D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4034 F0 "IC" -300 825 50 H V L B F1 "4034D" -300 -900 50 H V L B F2 "40xx-SO24W" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 800 P 2 1 0 0 300 800 -300 800 P 2 1 0 0 -300 800 -300 -800 X A/B\ 11 -500 -600 200 R 40 40 1 1 I X A/S\ 14 -500 -700 200 R 40 40 1 1 I X A1 16 -500 700 200 R 40 40 1 1 B X A2 17 -500 600 200 R 40 40 1 1 B X A3 18 -500 500 200 R 40 40 1 1 B X A4 19 -500 400 200 R 40 40 1 1 B X A5 20 -500 300 200 R 40 40 1 1 B X A6 21 -500 200 200 R 40 40 1 1 B X A7 22 -500 100 200 R 40 40 1 1 B X A8 23 -500 0 200 R 40 40 1 1 B X AE 9 -500 -300 200 R 40 40 1 1 I X B1 8 500 700 200 L 40 40 1 1 B X B2 7 500 600 200 L 40 40 1 1 B X B3 6 500 500 200 L 40 40 1 1 B X B4 5 500 400 200 L 40 40 1 1 B X B5 4 500 300 200 L 40 40 1 1 B X B6 3 500 200 200 L 40 40 1 1 B X B7 2 500 100 200 L 40 40 1 1 B X B8 1 500 0 200 L 40 40 1 1 B X CLK 15 -500 -200 200 R 40 40 1 1 I C X DS 10 -500 -400 200 R 40 40 1 1 I X P/S\ 13 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 24 0 300 200 D 40 40 2 1 W X VSS 12 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4034N # Package Name: DIL24-6 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4034N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4034 F0 "IC" -300 825 50 H V L B F1 "4034N" -300 -900 50 H V L B F2 "40xx-DIL24-6" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 800 P 2 1 0 0 300 800 -300 800 P 2 1 0 0 -300 800 -300 -800 X A/B\ 11 -500 -600 200 R 40 40 1 1 I X A/S\ 14 -500 -700 200 R 40 40 1 1 I X A1 16 -500 700 200 R 40 40 1 1 B X A2 17 -500 600 200 R 40 40 1 1 B X A3 18 -500 500 200 R 40 40 1 1 B X A4 19 -500 400 200 R 40 40 1 1 B X A5 20 -500 300 200 R 40 40 1 1 B X A6 21 -500 200 200 R 40 40 1 1 B X A7 22 -500 100 200 R 40 40 1 1 B X A8 23 -500 0 200 R 40 40 1 1 B X AE 9 -500 -300 200 R 40 40 1 1 I X B1 8 500 700 200 L 40 40 1 1 B X B2 7 500 600 200 L 40 40 1 1 B X B3 6 500 500 200 L 40 40 1 1 B X B4 5 500 400 200 L 40 40 1 1 B X B5 4 500 300 200 L 40 40 1 1 B X B6 3 500 200 200 L 40 40 1 1 B X B7 2 500 100 200 L 40 40 1 1 B X B8 1 500 0 200 L 40 40 1 1 B X CLK 15 -500 -200 200 R 40 40 1 1 I C X DS 10 -500 -400 200 R 40 40 1 1 I X P/S\ 13 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 24 0 300 200 D 40 40 2 1 W X VSS 12 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4035D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4035D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4035 F0 "IC" -300 625 50 H V L B F1 "4035D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 6 -500 0 200 R 40 40 1 1 I C X J 4 -500 -200 200 R 40 40 1 1 I X K 3 -500 -300 200 R 40 40 1 1 I I X P/S\ 7 -500 -100 200 R 40 40 1 1 I X P0 9 -500 500 200 R 40 40 1 1 I X P1 10 -500 400 200 R 40 40 1 1 I X P2 11 -500 300 200 R 40 40 1 1 I X P3 12 -500 200 200 R 40 40 1 1 I X Q0 1 500 500 200 L 40 40 1 1 O X Q1 15 500 400 200 L 40 40 1 1 O X Q2 14 500 300 200 L 40 40 1 1 O X Q3 13 500 200 200 L 40 40 1 1 O X RES 5 -500 -500 200 R 40 40 1 1 I X T/C\ 2 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4035N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4035N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4035 F0 "IC" -300 625 50 H V L B F1 "4035N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 6 -500 0 200 R 40 40 1 1 I C X J 4 -500 -200 200 R 40 40 1 1 I X K 3 -500 -300 200 R 40 40 1 1 I I X P/S\ 7 -500 -100 200 R 40 40 1 1 I X P0 9 -500 500 200 R 40 40 1 1 I X P1 10 -500 400 200 R 40 40 1 1 I X P2 11 -500 300 200 R 40 40 1 1 I X P3 12 -500 200 200 R 40 40 1 1 I X Q0 1 500 500 200 L 40 40 1 1 O X Q1 15 500 400 200 L 40 40 1 1 O X Q2 14 500 300 200 L 40 40 1 1 O X Q3 13 500 200 200 L 40 40 1 1 O X RES 5 -500 -500 200 R 40 40 1 1 I X T/C\ 2 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4038D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4038D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4038 F0 "IC" -300 725 50 H V L B F1 "4038D" -300 -900 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X A1 10 -500 600 200 R 40 40 1 1 I X A2 13 -500 200 200 R 40 40 1 1 I X A3 15 -500 -200 200 R 40 40 1 1 I X B1 11 -500 500 200 R 40 40 1 1 I X B2 12 -500 100 200 R 40 40 1 1 I X B3 14 -500 -300 200 R 40 40 1 1 I X CLK 3 -500 -600 200 R 40 40 1 1 I C X CR 6 -500 -700 200 R 40 40 1 1 I X I1 7 -500 400 200 R 40 40 1 1 I X I2 5 -500 0 200 R 40 40 1 1 I X I3 2 -500 -400 200 R 40 40 1 1 I X S1 9 500 500 200 L 40 40 1 1 O X S2 4 500 100 200 L 40 40 1 1 O X S3 1 500 -300 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4038N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4038N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4038 F0 "IC" -300 725 50 H V L B F1 "4038N" -300 -900 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X A1 10 -500 600 200 R 40 40 1 1 I X A2 13 -500 200 200 R 40 40 1 1 I X A3 15 -500 -200 200 R 40 40 1 1 I X B1 11 -500 500 200 R 40 40 1 1 I X B2 12 -500 100 200 R 40 40 1 1 I X B3 14 -500 -300 200 R 40 40 1 1 I X CLK 3 -500 -600 200 R 40 40 1 1 I C X CR 6 -500 -700 200 R 40 40 1 1 I X I1 7 -500 400 200 R 40 40 1 1 I X I2 5 -500 0 200 R 40 40 1 1 I X I3 2 -500 -400 200 R 40 40 1 1 I X S1 9 500 500 200 L 40 40 1 1 O X S2 4 500 100 200 L 40 40 1 1 O X S3 1 500 -300 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4040D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4040D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4040 F0 "IC" -300 625 50 H V L B F1 "4040D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X P1 10 -500 500 200 R 40 40 1 1 I IC X Q1 9 500 500 200 L 40 40 1 1 O X Q2 7 500 400 200 L 40 40 1 1 O X Q3 6 500 300 200 L 40 40 1 1 O X Q4 5 500 200 200 L 40 40 1 1 O X Q5 3 500 100 200 L 40 40 1 1 O X Q6 2 500 0 200 L 40 40 1 1 O X Q7 4 500 -100 200 L 40 40 1 1 O X Q8 13 500 -200 200 L 40 40 1 1 O X Q9 12 500 -300 200 L 40 40 1 1 O X Q10 14 500 -400 200 L 40 40 1 1 O X Q11 15 500 -500 200 L 40 40 1 1 O X Q12 1 500 -600 200 L 40 40 1 1 O X RES 11 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4040N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4040N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4040 F0 "IC" -300 625 50 H V L B F1 "4040N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X P1 10 -500 500 200 R 40 40 1 1 I IC X Q1 9 500 500 200 L 40 40 1 1 O X Q2 7 500 400 200 L 40 40 1 1 O X Q3 6 500 300 200 L 40 40 1 1 O X Q4 5 500 200 200 L 40 40 1 1 O X Q5 3 500 100 200 L 40 40 1 1 O X Q6 2 500 0 200 L 40 40 1 1 O X Q7 4 500 -100 200 L 40 40 1 1 O X Q8 13 500 -200 200 L 40 40 1 1 O X Q9 12 500 -300 200 L 40 40 1 1 O X Q10 14 500 -400 200 L 40 40 1 1 O X Q11 15 500 -500 200 L 40 40 1 1 O X Q12 1 500 -600 200 L 40 40 1 1 O X RES 11 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4041D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4041D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4041 F0 "IC" -300 625 50 H V L B F1 "4041D" -300 -700 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A 3 -500 500 200 R 40 40 1 1 I X B 6 -500 200 200 R 40 40 1 1 I X C 10 -500 -100 200 R 40 40 1 1 I X D 13 -500 -400 200 R 40 40 1 1 I X QA 1 500 500 200 L 40 40 1 1 O X QA\ 2 500 400 200 L 40 40 1 1 O X QB 4 500 200 200 L 40 40 1 1 O X QB\ 5 500 100 200 L 40 40 1 1 O X QC 8 500 -100 200 L 40 40 1 1 O X QC\ 9 500 -200 200 L 40 40 1 1 O X QD 11 500 -400 200 L 40 40 1 1 O X QD\ 12 500 -500 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4041N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4041N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4041 F0 "IC" -300 625 50 H V L B F1 "4041N" -300 -700 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A 3 -500 500 200 R 40 40 1 1 I X B 6 -500 200 200 R 40 40 1 1 I X C 10 -500 -100 200 R 40 40 1 1 I X D 13 -500 -400 200 R 40 40 1 1 I X QA 1 500 500 200 L 40 40 1 1 O X QA\ 2 500 400 200 L 40 40 1 1 O X QB 4 500 200 200 L 40 40 1 1 O X QB\ 5 500 100 200 L 40 40 1 1 O X QC 8 500 -100 200 L 40 40 1 1 O X QC\ 9 500 -200 200 L 40 40 1 1 O X QD 11 500 -400 200 L 40 40 1 1 O X QD\ 12 500 -500 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4042D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4042D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4042 F0 "IC" -300 425 50 H V L B F1 "4042D" -300 -600 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X CLK 5 -500 -200 200 R 40 40 1 1 I C X D0 4 -500 300 200 R 40 40 1 1 I X D1 7 -500 200 200 R 40 40 1 1 I X D2 13 -500 100 200 R 40 40 1 1 I X D3 14 -500 0 200 R 40 40 1 1 I X POL 6 -500 -400 200 R 40 40 1 1 I X Q0 2 500 300 200 L 40 40 1 1 O X Q0\ 3 500 200 200 L 40 40 1 1 O X Q1 10 500 100 200 L 40 40 1 1 O X Q1\ 9 500 0 200 L 40 40 1 1 O X Q2 11 500 -100 200 L 40 40 1 1 O X Q2\ 12 500 -200 200 L 40 40 1 1 O X Q3 1 500 -300 200 L 40 40 1 1 O X Q3\ 15 500 -400 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4042N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4042N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4042 F0 "IC" -300 425 50 H V L B F1 "4042N" -300 -600 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X CLK 5 -500 -200 200 R 40 40 1 1 I C X D0 4 -500 300 200 R 40 40 1 1 I X D1 7 -500 200 200 R 40 40 1 1 I X D2 13 -500 100 200 R 40 40 1 1 I X D3 14 -500 0 200 R 40 40 1 1 I X POL 6 -500 -400 200 R 40 40 1 1 I X Q0 2 500 300 200 L 40 40 1 1 O X Q0\ 3 500 200 200 L 40 40 1 1 O X Q1 10 500 100 200 L 40 40 1 1 O X Q1\ 9 500 0 200 L 40 40 1 1 O X Q2 11 500 -100 200 L 40 40 1 1 O X Q2\ 12 500 -200 200 L 40 40 1 1 O X Q3 1 500 -300 200 L 40 40 1 1 O X Q3\ 15 500 -400 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4043D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4043D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4043 F0 "IC" -300 725 50 H V L B F1 "4043D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X EN 5 -500 -600 200 R 40 40 1 1 I X Q0 2 500 600 200 L 40 40 1 1 O X Q1 9 500 300 200 L 40 40 1 1 O X Q2 10 500 0 200 L 40 40 1 1 O X Q3 1 500 -300 200 L 40 40 1 1 O X R0 3 -500 500 200 R 40 40 1 1 I X R1 7 -500 200 200 R 40 40 1 1 I X R2 11 -500 -100 200 R 40 40 1 1 I X R3 15 -500 -400 200 R 40 40 1 1 I X S0 4 -500 600 200 R 40 40 1 1 I X S1 6 -500 300 200 R 40 40 1 1 I X S2 12 -500 0 200 R 40 40 1 1 I X S3 14 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4043N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4043N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4043 F0 "IC" -300 725 50 H V L B F1 "4043N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X EN 5 -500 -600 200 R 40 40 1 1 I X Q0 2 500 600 200 L 40 40 1 1 O X Q1 9 500 300 200 L 40 40 1 1 O X Q2 10 500 0 200 L 40 40 1 1 O X Q3 1 500 -300 200 L 40 40 1 1 O X R0 3 -500 500 200 R 40 40 1 1 I X R1 7 -500 200 200 R 40 40 1 1 I X R2 11 -500 -100 200 R 40 40 1 1 I X R3 15 -500 -400 200 R 40 40 1 1 I X S0 4 -500 600 200 R 40 40 1 1 I X S1 6 -500 300 200 R 40 40 1 1 I X S2 12 -500 0 200 R 40 40 1 1 I X S3 14 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4044D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4044D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4044 F0 "IC" -300 725 50 H V L B F1 "4044D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X EN 5 -500 -600 200 R 40 40 1 1 I X Q0 13 500 600 200 L 40 40 1 1 O X Q1 9 500 300 200 L 40 40 1 1 O X Q2 10 500 0 200 L 40 40 1 1 O X Q3 1 500 -300 200 L 40 40 1 1 O X R0 4 -500 600 200 R 40 40 1 1 I X R1 6 -500 300 200 R 40 40 1 1 I X R2 12 -500 0 200 R 40 40 1 1 I X R3 14 -500 -300 200 R 40 40 1 1 I X S0 3 -500 500 200 R 40 40 1 1 I X S1 7 -500 200 200 R 40 40 1 1 I X S2 11 -500 -100 200 R 40 40 1 1 I X S3 15 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4044N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4044N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4044 F0 "IC" -300 725 50 H V L B F1 "4044N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X EN 5 -500 -600 200 R 40 40 1 1 I X Q0 13 500 600 200 L 40 40 1 1 O X Q1 9 500 300 200 L 40 40 1 1 O X Q2 10 500 0 200 L 40 40 1 1 O X Q3 1 500 -300 200 L 40 40 1 1 O X R0 4 -500 600 200 R 40 40 1 1 I X R1 6 -500 300 200 R 40 40 1 1 I X R2 12 -500 0 200 R 40 40 1 1 I X R3 14 -500 -300 200 R 40 40 1 1 I X S0 3 -500 500 200 R 40 40 1 1 I X S1 7 -500 200 200 R 40 40 1 1 I X S2 11 -500 -100 200 R 40 40 1 1 I X S3 15 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4045D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4045D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4045 F0 "IC" -400 425 50 H V L B F1 "4045D" -200 -400 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW A -900 0 200 -899 899 1 1 0 N -900 -200 -900 200 P 2 1 0 0 -900 200 -900 -200 P 2 1 0 0 -640 0 -580 0 P 2 1 0 0 -580 0 -500 0 A -500 0 200 -899 899 1 1 0 N -500 -200 -500 200 P 2 1 0 0 -500 200 -500 -200 P 2 1 0 0 -240 0 -170 0 P 2 1 0 0 -170 0 -100 0 A -90 0 200 -899 899 1 1 0 N -90 -200 -90 200 P 2 1 0 0 -90 200 -90 -200 P 2 1 0 0 170 0 310 0 P 2 1 0 0 -900 300 -830 300 P 2 1 0 0 -830 300 -830 190 P 2 1 0 0 -900 -300 -830 -300 P 2 1 0 0 -830 -300 -830 -190 P 2 1 0 0 -1000 500 -580 500 P 2 1 0 0 -580 500 -580 0 P 2 1 0 0 900 340 690 340 P 2 1 0 0 690 340 690 -200 P 2 1 0 0 690 -200 690 -350 P 2 1 0 0 690 -350 900 -350 P 2 1 0 0 900 -350 900 340 P 2 1 0 0 530 340 320 340 P 2 1 0 0 320 340 320 -350 P 2 1 0 0 320 -350 530 -350 P 2 1 0 0 530 -350 530 -200 P 2 1 0 0 530 -200 530 340 P 2 1 0 0 -170 0 -170 250 P 2 1 0 0 -170 250 310 250 P 2 1 0 0 540 200 680 200 P 2 1 0 0 530 -200 690 -200 C -670 0 31 1 1 0 N C -270 0 31 1 1 0 N C 140 0 31 1 1 0 N C -580 0 20 1 1 0 N C -170 0 20 1 1 0 N T 0 -840 350 60 0 1 0 SP T 0 -840 550 60 0 1 0 T0 T 0 -840 -360 60 0 1 0 SN T 0 -800 0 60 0 1 0 T1 X Q 7 1000 200 100 L 40 40 1 1 I X Q\ 8 1000 -200 100 L 40 40 1 1 I X SN 2 -1100 -300 200 R 40 40 1 1 I X SP 1 -1100 300 200 R 40 40 1 1 I X T0 15 -1100 500 100 R 40 40 1 1 I X T1 16 -1100 0 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 3 0 300 200 D 40 40 2 1 W X VSS 14 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4045N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4045N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4045 F0 "IC" -400 425 50 H V L B F1 "4045N" -200 -400 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW A -900 0 200 -899 899 1 1 0 N -900 -200 -900 200 P 2 1 0 0 -900 200 -900 -200 P 2 1 0 0 -640 0 -580 0 P 2 1 0 0 -580 0 -500 0 A -500 0 200 -899 899 1 1 0 N -500 -200 -500 200 P 2 1 0 0 -500 200 -500 -200 P 2 1 0 0 -240 0 -170 0 P 2 1 0 0 -170 0 -100 0 A -90 0 200 -899 899 1 1 0 N -90 -200 -90 200 P 2 1 0 0 -90 200 -90 -200 P 2 1 0 0 170 0 310 0 P 2 1 0 0 -900 300 -830 300 P 2 1 0 0 -830 300 -830 190 P 2 1 0 0 -900 -300 -830 -300 P 2 1 0 0 -830 -300 -830 -190 P 2 1 0 0 -1000 500 -580 500 P 2 1 0 0 -580 500 -580 0 P 2 1 0 0 900 340 690 340 P 2 1 0 0 690 340 690 -200 P 2 1 0 0 690 -200 690 -350 P 2 1 0 0 690 -350 900 -350 P 2 1 0 0 900 -350 900 340 P 2 1 0 0 530 340 320 340 P 2 1 0 0 320 340 320 -350 P 2 1 0 0 320 -350 530 -350 P 2 1 0 0 530 -350 530 -200 P 2 1 0 0 530 -200 530 340 P 2 1 0 0 -170 0 -170 250 P 2 1 0 0 -170 250 310 250 P 2 1 0 0 540 200 680 200 P 2 1 0 0 530 -200 690 -200 C -670 0 31 1 1 0 N C -270 0 31 1 1 0 N C 140 0 31 1 1 0 N C -580 0 20 1 1 0 N C -170 0 20 1 1 0 N T 0 -840 350 60 0 1 0 SP T 0 -840 550 60 0 1 0 T0 T 0 -840 -360 60 0 1 0 SN T 0 -800 0 60 0 1 0 T1 X Q 7 1000 200 100 L 40 40 1 1 I X Q\ 8 1000 -200 100 L 40 40 1 1 I X SN 2 -1100 -300 200 R 40 40 1 1 I X SP 1 -1100 300 200 R 40 40 1 1 I X T0 15 -1100 500 100 R 40 40 1 1 I X T1 16 -1100 0 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 3 0 300 200 D 40 40 2 1 W X VSS 14 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4046D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4046D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4046 F0 "IC" -400 625 50 H V L B F1 "4046D" -400 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -700 400 -700 P 2 1 0 0 400 -700 400 600 P 2 1 0 0 400 600 -400 600 P 2 1 0 0 -400 600 -400 -700 X CIN 3 -600 500 200 R 40 40 1 1 I X CX@1 6 -600 0 200 R 40 40 1 1 I X CX@2 7 -600 -300 200 R 40 40 1 1 I X DEMO 10 600 -500 200 L 40 40 1 1 O X INH 5 -600 -400 200 R 40 40 1 1 I X PC1 2 600 400 200 L 40 40 1 1 O X PC2 13 600 200 200 L 40 40 1 1 O X PP 1 600 500 200 L 40 40 1 1 O X R1 11 -600 -500 200 R 40 40 1 1 I X R2 12 -600 -600 200 R 40 40 1 1 I X SIGIN 14 -600 200 200 R 40 40 1 1 I X VCOIN 9 600 -300 200 L 40 40 1 1 I X VCOOUT 4 -600 400 200 R 40 40 1 1 O X ZEN 15 600 -600 200 L 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4046N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4046N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4046 F0 "IC" -400 625 50 H V L B F1 "4046N" -400 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -700 400 -700 P 2 1 0 0 400 -700 400 600 P 2 1 0 0 400 600 -400 600 P 2 1 0 0 -400 600 -400 -700 X CIN 3 -600 500 200 R 40 40 1 1 I X CX@1 6 -600 0 200 R 40 40 1 1 I X CX@2 7 -600 -300 200 R 40 40 1 1 I X DEMO 10 600 -500 200 L 40 40 1 1 O X INH 5 -600 -400 200 R 40 40 1 1 I X PC1 2 600 400 200 L 40 40 1 1 O X PC2 13 600 200 200 L 40 40 1 1 O X PP 1 600 500 200 L 40 40 1 1 O X R1 11 -600 -500 200 R 40 40 1 1 I X R2 12 -600 -600 200 R 40 40 1 1 I X SIGIN 14 -600 200 200 R 40 40 1 1 I X VCOIN 9 600 -300 200 L 40 40 1 1 I X VCOOUT 4 -600 400 200 R 40 40 1 1 O X ZEN 15 600 -600 200 L 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4047D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4047D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4047 F0 "IC" -300 725 50 H V L B F1 "4047D" -300 -600 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -500 X +T 8 -500 300 200 R 40 40 1 1 I X -T 6 -500 400 200 R 40 40 1 1 I X AST 5 -500 600 200 R 40 40 1 1 I X AST\ 4 -500 500 200 R 40 40 1 1 I X C 1 -500 -100 200 R 40 40 1 1 I X OSC 13 500 -100 200 L 40 40 1 1 O X Q 10 500 600 200 L 40 40 1 1 O X Q\ 11 500 300 200 L 40 40 1 1 O X R 2 -500 -200 200 R 40 40 1 1 I X R/C 3 -500 0 200 R 40 40 1 1 I X RES 9 -500 -400 200 R 40 40 1 1 I X RET 12 -500 200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4047N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4047N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4047 F0 "IC" -300 725 50 H V L B F1 "4047N" -300 -600 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -500 X +T 8 -500 300 200 R 40 40 1 1 I X -T 6 -500 400 200 R 40 40 1 1 I X AST 5 -500 600 200 R 40 40 1 1 I X AST\ 4 -500 500 200 R 40 40 1 1 I X C 1 -500 -100 200 R 40 40 1 1 I X OSC 13 500 -100 200 L 40 40 1 1 O X Q 10 500 600 200 L 40 40 1 1 O X Q\ 11 500 300 200 L 40 40 1 1 O X R 2 -500 -200 200 R 40 40 1 1 I X R/C 3 -500 0 200 R 40 40 1 1 I X RES 9 -500 -400 200 R 40 40 1 1 I X RET 12 -500 200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4048D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4048D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4048 F0 "IC" -300 725 50 H V L B F1 "4048D" -300 -900 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X A 14 -500 600 200 R 40 40 1 1 I X B 13 -500 500 200 R 40 40 1 1 I X C 12 -500 400 200 R 40 40 1 1 I X D 11 -500 300 200 R 40 40 1 1 I X E 6 -500 200 200 R 40 40 1 1 I X EXIN 15 -500 -700 200 R 40 40 1 1 I X F 5 -500 100 200 R 40 40 1 1 I X G 4 -500 0 200 R 40 40 1 1 I X H 3 -500 -100 200 R 40 40 1 1 I X J 1 500 600 200 L 40 40 1 1 O X KA 10 -500 -300 200 R 40 40 1 1 I X KB 7 -500 -400 200 R 40 40 1 1 I X KC 9 -500 -500 200 R 40 40 1 1 I X KD 2 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4048N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4048N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4048 F0 "IC" -300 725 50 H V L B F1 "4048N" -300 -900 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -800 300 -800 P 2 1 0 0 300 -800 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -800 X A 14 -500 600 200 R 40 40 1 1 I X B 13 -500 500 200 R 40 40 1 1 I X C 12 -500 400 200 R 40 40 1 1 I X D 11 -500 300 200 R 40 40 1 1 I X E 6 -500 200 200 R 40 40 1 1 I X EXIN 15 -500 -700 200 R 40 40 1 1 I X F 5 -500 100 200 R 40 40 1 1 I X G 4 -500 0 200 R 40 40 1 1 I X H 3 -500 -100 200 R 40 40 1 1 I X J 1 500 600 200 L 40 40 1 1 O X KA 10 -500 -300 200 R 40 40 1 1 I X KB 7 -500 -400 200 R 40 40 1 1 I X KC 9 -500 -500 200 R 40 40 1 1 I X KD 2 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4049D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4049D IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4049 F0 "IC" 100 125 50 H V L B F1 "4049D" 100 -200 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4049 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4049 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4049 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 4049 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 4049 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4049N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4049N IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4049 F0 "IC" 100 125 50 H V L B F1 "4049N" 100 -200 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4049 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4049 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4049 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 4049 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 4049 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4050D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4050D IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4050 F0 "IC" 100 125 50 H V L B F1 "4050D" 100 -200 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4050 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4050 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4050 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O # Gate Name: E # Symbol Name: 4050 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O # Gate Name: F # Symbol Name: 4050 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4050N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4050N IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4050 F0 "IC" 100 125 50 H V L B F1 "4050N" 100 -200 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4050 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4050 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 7 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4050 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 10 400 0 200 L 40 40 4 1 O # Gate Name: E # Symbol Name: 4050 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 12 400 0 200 L 40 40 5 1 O # Gate Name: F # Symbol Name: 4050 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 14 -400 0 200 R 40 40 6 1 I X O 15 400 0 200 L 40 40 6 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 1 0 300 200 D 40 40 7 1 W X VSS 8 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4051D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4051D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4051 F0 "IC" -300 725 50 H V L B F1 "4051D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X A 11 -500 -400 200 R 40 40 1 1 I X B 10 -500 -500 200 R 40 40 1 1 I X C 9 -500 -600 200 R 40 40 1 1 I X INH 6 -500 -300 200 R 40 40 1 1 I X X 3 500 600 200 L 40 40 1 1 B X X0 13 -500 600 200 R 40 40 1 1 B X X1 14 -500 500 200 R 40 40 1 1 B X X2 15 -500 400 200 R 40 40 1 1 B X X3 12 -500 300 200 R 40 40 1 1 B X X4 1 -500 200 200 R 40 40 1 1 B X X5 5 -500 100 200 R 40 40 1 1 B X X6 2 -500 0 200 R 40 40 1 1 B X X7 4 -500 -100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4051N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4051N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4051 F0 "IC" -300 725 50 H V L B F1 "4051N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X A 11 -500 -400 200 R 40 40 1 1 I X B 10 -500 -500 200 R 40 40 1 1 I X C 9 -500 -600 200 R 40 40 1 1 I X INH 6 -500 -300 200 R 40 40 1 1 I X X 3 500 600 200 L 40 40 1 1 B X X0 13 -500 600 200 R 40 40 1 1 B X X1 14 -500 500 200 R 40 40 1 1 B X X2 15 -500 400 200 R 40 40 1 1 B X X3 12 -500 300 200 R 40 40 1 1 B X X4 1 -500 200 200 R 40 40 1 1 B X X5 5 -500 100 200 R 40 40 1 1 B X X6 2 -500 0 200 R 40 40 1 1 B X X7 4 -500 -100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4052D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4052D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4052 F0 "IC" -300 625 50 H V L B F1 "4052D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X A 10 -500 -500 200 R 40 40 1 1 I X B 9 -500 -600 200 R 40 40 1 1 I X INH 6 -500 -400 200 R 40 40 1 1 I X X 13 500 500 200 L 40 40 1 1 B X X0 12 -500 500 200 R 40 40 1 1 B X X1 14 -500 400 200 R 40 40 1 1 B X X2 15 -500 300 200 R 40 40 1 1 B X X3 11 -500 200 200 R 40 40 1 1 B X Y 3 500 0 200 L 40 40 1 1 B X Y0 1 -500 0 200 R 40 40 1 1 B X Y1 5 -500 -100 200 R 40 40 1 1 B X Y2 2 -500 -200 200 R 40 40 1 1 B X Y3 4 -500 -300 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4052N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4052N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4052 F0 "IC" -300 625 50 H V L B F1 "4052N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X A 10 -500 -500 200 R 40 40 1 1 I X B 9 -500 -600 200 R 40 40 1 1 I X INH 6 -500 -400 200 R 40 40 1 1 I X X 13 500 500 200 L 40 40 1 1 B X X0 12 -500 500 200 R 40 40 1 1 B X X1 14 -500 400 200 R 40 40 1 1 B X X2 15 -500 300 200 R 40 40 1 1 B X X3 11 -500 200 200 R 40 40 1 1 B X Y 3 500 0 200 L 40 40 1 1 B X Y0 1 -500 0 200 R 40 40 1 1 B X Y1 5 -500 -100 200 R 40 40 1 1 B X Y2 2 -500 -200 200 R 40 40 1 1 B X Y3 4 -500 -300 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4053D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4053D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4053 F0 "IC" -300 725 50 H V L B F1 "4053D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X A 11 -500 -400 200 R 40 40 1 1 I X B 10 -500 -500 200 R 40 40 1 1 I X C 9 -500 -600 200 R 40 40 1 1 I X INH 6 -500 -300 200 R 40 40 1 1 I X X 14 500 600 200 L 40 40 1 1 B X X0 12 -500 600 200 R 40 40 1 1 B X X1 13 -500 500 200 R 40 40 1 1 B X Y 15 500 300 200 L 40 40 1 1 B X Y0 2 -500 300 200 R 40 40 1 1 B X Y1 1 -500 200 200 R 40 40 1 1 B X Z 4 500 0 200 L 40 40 1 1 B X Z0 5 -500 0 200 R 40 40 1 1 B X Z1 3 -500 -100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4053N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4053N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4053 F0 "IC" -300 725 50 H V L B F1 "4053N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X A 11 -500 -400 200 R 40 40 1 1 I X B 10 -500 -500 200 R 40 40 1 1 I X C 9 -500 -600 200 R 40 40 1 1 I X INH 6 -500 -300 200 R 40 40 1 1 I X X 14 500 600 200 L 40 40 1 1 B X X0 12 -500 600 200 R 40 40 1 1 B X X1 13 -500 500 200 R 40 40 1 1 B X Y 15 500 300 200 L 40 40 1 1 B X Y0 2 -500 300 200 R 40 40 1 1 B X Y1 1 -500 200 200 R 40 40 1 1 B X Z 4 500 0 200 L 40 40 1 1 B X Z0 5 -500 0 200 R 40 40 1 1 B X Z1 3 -500 -100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4055D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4055D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4055 F0 "IC" -300 525 50 H V L B F1 "4055D" -300 -600 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X A 9 500 400 200 L 40 40 1 1 O X B 10 500 300 200 L 40 40 1 1 O X C 11 500 200 200 L 40 40 1 1 O X D 12 500 100 200 L 40 40 1 1 O X DFI 6 -500 -400 200 R 40 40 1 1 I X DFO 1 500 -400 200 L 40 40 1 1 O X E 13 500 0 200 L 40 40 1 1 O X F 15 500 -100 200 L 40 40 1 1 O X G 14 500 -200 200 L 40 40 1 1 O X I0 5 -500 400 200 R 40 40 1 1 I X I1 3 -500 300 200 R 40 40 1 1 I X I2 2 -500 200 200 R 40 40 1 1 I X I3 4 -500 100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4055N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4055N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4055 F0 "IC" -300 525 50 H V L B F1 "4055N" -300 -600 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X A 9 500 400 200 L 40 40 1 1 O X B 10 500 300 200 L 40 40 1 1 O X C 11 500 200 200 L 40 40 1 1 O X D 12 500 100 200 L 40 40 1 1 O X DFI 6 -500 -400 200 R 40 40 1 1 I X DFO 1 500 -400 200 L 40 40 1 1 O X E 13 500 0 200 L 40 40 1 1 O X F 15 500 -100 200 L 40 40 1 1 O X G 14 500 -200 200 L 40 40 1 1 O X I0 5 -500 400 200 R 40 40 1 1 I X I1 3 -500 300 200 R 40 40 1 1 I X I2 2 -500 200 200 R 40 40 1 1 I X I3 4 -500 100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4056D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4056D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4056 F0 "IC" -300 425 50 H V L B F1 "4056D" -300 -500 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X A 9 500 300 200 L 40 40 1 1 O X B 10 500 200 200 L 40 40 1 1 O X C 11 500 100 200 L 40 40 1 1 O X D 12 500 0 200 L 40 40 1 1 O X DFI 6 -500 -200 200 R 40 40 1 1 I X E 13 500 -100 200 L 40 40 1 1 O X F 15 500 -200 200 L 40 40 1 1 O X G 14 500 -300 200 L 40 40 1 1 O X I0 5 -500 300 200 R 40 40 1 1 I X I1 3 -500 200 200 R 40 40 1 1 I X I2 2 -500 100 200 R 40 40 1 1 I X I3 4 -500 0 200 R 40 40 1 1 I X ST 1 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4056N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4056N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4056 F0 "IC" -300 425 50 H V L B F1 "4056N" -300 -500 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -400 X A 9 500 300 200 L 40 40 1 1 O X B 10 500 200 200 L 40 40 1 1 O X C 11 500 100 200 L 40 40 1 1 O X D 12 500 0 200 L 40 40 1 1 O X DFI 6 -500 -200 200 R 40 40 1 1 I X E 13 500 -100 200 L 40 40 1 1 O X F 15 500 -200 200 L 40 40 1 1 O X G 14 500 -300 200 L 40 40 1 1 O X I0 5 -500 300 200 R 40 40 1 1 I X I1 3 -500 200 200 R 40 40 1 1 I X I2 2 -500 100 200 R 40 40 1 1 I X I3 4 -500 0 200 R 40 40 1 1 I X ST 1 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWR+VEE T 1 -150 -155 50 0 2 0 VEE T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W X VEE 7 -200 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4060D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4060D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4060 F0 "IC" -300 725 50 H V L B F1 "4060D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X P0 9 500 -500 200 L 40 40 1 1 O X P0\ 10 500 -600 200 L 40 40 1 1 O X P1 11 -500 600 200 R 40 40 1 1 I X Q4 7 500 600 200 L 40 40 1 1 O X Q5 5 500 500 200 L 40 40 1 1 O X Q6 4 500 400 200 L 40 40 1 1 O X Q7 6 500 300 200 L 40 40 1 1 O X Q8 14 500 200 200 L 40 40 1 1 O X Q9 13 500 100 200 L 40 40 1 1 O X Q10 15 500 0 200 L 40 40 1 1 O X Q12 1 500 -100 200 L 40 40 1 1 O X Q13 2 500 -200 200 L 40 40 1 1 O X Q14 3 500 -300 200 L 40 40 1 1 O X RES 12 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4060N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4060N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4060 F0 "IC" -300 725 50 H V L B F1 "4060N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X P0 9 500 -500 200 L 40 40 1 1 O X P0\ 10 500 -600 200 L 40 40 1 1 O X P1 11 -500 600 200 R 40 40 1 1 I X Q4 7 500 600 200 L 40 40 1 1 O X Q5 5 500 500 200 L 40 40 1 1 O X Q6 4 500 400 200 L 40 40 1 1 O X Q7 6 500 300 200 L 40 40 1 1 O X Q8 14 500 200 200 L 40 40 1 1 O X Q9 13 500 100 200 L 40 40 1 1 O X Q10 15 500 0 200 L 40 40 1 1 O X Q12 1 500 -100 200 L 40 40 1 1 O X Q13 2 500 -200 200 L 40 40 1 1 O X Q14 3 500 -300 200 L 40 40 1 1 O X RES 12 -500 -600 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4063D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4063D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4063 F0 "IC" -400 625 50 H V L B F1 "4063D" -400 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -600 400 -600 P 2 1 0 0 400 -600 400 600 P 2 1 0 0 400 600 -400 600 P 2 1 0 0 -400 600 -400 -600 X A0 10 -600 500 200 R 40 40 1 1 I X A1 12 -600 400 200 R 40 40 1 1 I X A2 13 -600 300 200 R 40 40 1 1 I X A3 15 -600 200 200 R 40 40 1 1 I X AB_I 4 -600 -300 200 R 40 40 1 1 I X A>B_O 5 600 -300 200 L 40 40 1 1 O X B0 9 -600 100 200 R 40 40 1 1 I X B1 11 -600 0 200 R 40 40 1 1 I X B2 14 -600 -100 200 R 40 40 1 1 I X B3 1 -600 -200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4063N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4063N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4063 F0 "IC" -400 625 50 H V L B F1 "4063N" -400 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -600 400 -600 P 2 1 0 0 400 -600 400 600 P 2 1 0 0 400 600 -400 600 P 2 1 0 0 -400 600 -400 -600 X A0 10 -600 500 200 R 40 40 1 1 I X A1 12 -600 400 200 R 40 40 1 1 I X A2 13 -600 300 200 R 40 40 1 1 I X A3 15 -600 200 200 R 40 40 1 1 I X AB_I 4 -600 -300 200 R 40 40 1 1 I X A>B_O 5 600 -300 200 L 40 40 1 1 O X B0 9 -600 100 200 R 40 40 1 1 I X B1 11 -600 0 200 R 40 40 1 1 I X B2 14 -600 -100 200 R 40 40 1 1 I X B3 1 -600 -200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4066D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4066D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4066 F0 "IC" -300 225 50 H V L B F1 "4066D" -300 -300 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -200 300 -200 P 2 1 0 0 300 -200 300 200 P 2 1 0 0 300 200 -300 200 P 2 1 0 0 -300 200 -300 -200 X A 1 -500 100 200 R 40 40 1 1 T X B 2 500 100 200 L 40 40 1 1 T X C 13 -500 -100 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4066 P 2 2 0 0 -300 -200 300 -200 P 2 2 0 0 300 -200 300 200 P 2 2 0 0 300 200 -300 200 P 2 2 0 0 -300 200 -300 -200 X A 4 -500 100 200 R 40 40 2 1 T X B 3 500 100 200 L 40 40 2 1 T X C 5 -500 -100 200 R 40 40 2 1 I # Gate Name: C # Symbol Name: 4066 P 2 3 0 0 -300 -200 300 -200 P 2 3 0 0 300 -200 300 200 P 2 3 0 0 300 200 -300 200 P 2 3 0 0 -300 200 -300 -200 X A 8 -500 100 200 R 40 40 3 1 T X B 9 500 100 200 L 40 40 3 1 T X C 6 -500 -100 200 R 40 40 3 1 I # Gate Name: D # Symbol Name: 4066 P 2 4 0 0 -300 -200 300 -200 P 2 4 0 0 300 -200 300 200 P 2 4 0 0 300 200 -300 200 P 2 4 0 0 -300 200 -300 -200 X A 11 -500 100 200 R 40 40 4 1 T X B 10 500 100 200 L 40 40 4 1 T X C 12 -500 -100 200 R 40 40 4 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4066N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4066N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4066 F0 "IC" -300 225 50 H V L B F1 "4066N" -300 -300 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -200 300 -200 P 2 1 0 0 300 -200 300 200 P 2 1 0 0 300 200 -300 200 P 2 1 0 0 -300 200 -300 -200 X A 1 -500 100 200 R 40 40 1 1 T X B 2 500 100 200 L 40 40 1 1 T X C 13 -500 -100 200 R 40 40 1 1 I # Gate Name: B # Symbol Name: 4066 P 2 2 0 0 -300 -200 300 -200 P 2 2 0 0 300 -200 300 200 P 2 2 0 0 300 200 -300 200 P 2 2 0 0 -300 200 -300 -200 X A 4 -500 100 200 R 40 40 2 1 T X B 3 500 100 200 L 40 40 2 1 T X C 5 -500 -100 200 R 40 40 2 1 I # Gate Name: C # Symbol Name: 4066 P 2 3 0 0 -300 -200 300 -200 P 2 3 0 0 300 -200 300 200 P 2 3 0 0 300 200 -300 200 P 2 3 0 0 -300 200 -300 -200 X A 8 -500 100 200 R 40 40 3 1 T X B 9 500 100 200 L 40 40 3 1 T X C 6 -500 -100 200 R 40 40 3 1 I # Gate Name: D # Symbol Name: 4066 P 2 4 0 0 -300 -200 300 -200 P 2 4 0 0 300 -200 300 200 P 2 4 0 0 300 200 -300 200 P 2 4 0 0 -300 200 -300 -200 X A 11 -500 100 200 R 40 40 4 1 T X B 10 500 100 200 L 40 40 4 1 T X C 12 -500 -100 200 R 40 40 4 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4067D # Package Name: SO24W # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4067D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4067 F0 "IC" -300 1125 50 H V L B F1 "4067D" -300 -1300 50 H V L B F2 "40xx-SO24W" 0 150 50 H I C C DRAW P 2 1 0 0 -300 1100 -300 -1200 P 2 1 0 0 -300 -1200 300 -1200 P 2 1 0 0 300 -1200 300 1100 P 2 1 0 0 300 1100 -300 1100 X A 10 -500 900 200 R 40 40 1 1 I X B 11 -500 800 200 R 40 40 1 1 I X C 14 -500 700 200 R 40 40 1 1 I X D 13 -500 600 200 R 40 40 1 1 I X INH 15 -500 1000 200 R 40 40 1 1 I X X 1 500 400 200 L 40 40 1 1 O X X0 9 -500 400 200 R 40 40 1 1 I X X1 8 -500 300 200 R 40 40 1 1 I X X2 7 -500 200 200 R 40 40 1 1 I X X3 6 -500 100 200 R 40 40 1 1 I X X4 5 -500 0 200 R 40 40 1 1 I X X5 4 -500 -100 200 R 40 40 1 1 I X X6 3 -500 -200 200 R 40 40 1 1 I X X7 2 -500 -300 200 R 40 40 1 1 I X X8 23 -500 -400 200 R 40 40 1 1 I X X9 22 -500 -500 200 R 40 40 1 1 I X X10 21 -500 -600 200 R 40 40 1 1 I X X11 20 -500 -700 200 R 40 40 1 1 I X X12 19 -500 -800 200 R 40 40 1 1 I X X13 18 -500 -900 200 R 40 40 1 1 I X X14 17 -500 -1000 200 R 40 40 1 1 I X X15 16 -500 -1100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 24 0 300 200 D 40 40 2 1 W X VSS 12 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4067N # Package Name: DIL24-6 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4067N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4067 F0 "IC" -300 1125 50 H V L B F1 "4067N" -300 -1300 50 H V L B F2 "40xx-DIL24-6" 0 150 50 H I C C DRAW P 2 1 0 0 -300 1100 -300 -1200 P 2 1 0 0 -300 -1200 300 -1200 P 2 1 0 0 300 -1200 300 1100 P 2 1 0 0 300 1100 -300 1100 X A 10 -500 900 200 R 40 40 1 1 I X B 11 -500 800 200 R 40 40 1 1 I X C 14 -500 700 200 R 40 40 1 1 I X D 13 -500 600 200 R 40 40 1 1 I X INH 15 -500 1000 200 R 40 40 1 1 I X X 1 500 400 200 L 40 40 1 1 O X X0 9 -500 400 200 R 40 40 1 1 I X X1 8 -500 300 200 R 40 40 1 1 I X X2 7 -500 200 200 R 40 40 1 1 I X X3 6 -500 100 200 R 40 40 1 1 I X X4 5 -500 0 200 R 40 40 1 1 I X X5 4 -500 -100 200 R 40 40 1 1 I X X6 3 -500 -200 200 R 40 40 1 1 I X X7 2 -500 -300 200 R 40 40 1 1 I X X8 23 -500 -400 200 R 40 40 1 1 I X X9 22 -500 -500 200 R 40 40 1 1 I X X10 21 -500 -600 200 R 40 40 1 1 I X X11 20 -500 -700 200 R 40 40 1 1 I X X12 19 -500 -800 200 R 40 40 1 1 I X X13 18 -500 -900 200 R 40 40 1 1 I X X14 17 -500 -1000 200 R 40 40 1 1 I X X15 16 -500 -1100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 24 0 300 200 D 40 40 2 1 W X VSS 12 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4068D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4068D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4068 F0 "IC" 200 200 50 H V L B F1 "4068D" 200 -275 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -100 -500 -100 500 A -100 300 200 -3599 -2701 1 1 0 N 100 300 -100 500 A -100 -300 200 -899 -1 1 1 0 N -100 -500 100 -300 P 2 1 0 0 100 300 100 -300 X I0 2 -300 400 200 R 40 40 1 1 I X I1 3 -300 300 200 R 40 40 1 1 I X I2 4 -300 200 200 R 40 40 1 1 I X I3 5 -300 100 200 R 40 40 1 1 I X I4 9 -300 -100 200 R 40 40 1 1 I X I5 10 -300 -200 200 R 40 40 1 1 I X I6 11 -300 -300 200 R 40 40 1 1 I X I7 12 -300 -400 200 R 40 40 1 1 I X J 13 300 0 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4068N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4068N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4068 F0 "IC" 200 200 50 H V L B F1 "4068N" 200 -275 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -100 -500 -100 500 A -100 300 200 -3599 -2701 1 1 0 N 100 300 -100 500 A -100 -300 200 -899 -1 1 1 0 N -100 -500 100 -300 P 2 1 0 0 100 300 100 -300 X I0 2 -300 400 200 R 40 40 1 1 I X I1 3 -300 300 200 R 40 40 1 1 I X I2 4 -300 200 200 R 40 40 1 1 I X I3 5 -300 100 200 R 40 40 1 1 I X I4 9 -300 -100 200 R 40 40 1 1 I X I5 10 -300 -200 200 R 40 40 1 1 I X I6 11 -300 -300 200 R 40 40 1 1 I X I7 12 -300 -400 200 R 40 40 1 1 I X J 13 300 0 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4069D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4069D IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4069 F0 "IC" 100 125 50 H V L B F1 "4069D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 1 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4069 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4069 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4069 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 8 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 4069 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 10 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 4069 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 13 -400 0 200 R 40 40 6 1 I X O 12 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 14 0 300 200 D 40 40 7 1 W X VSS 7 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4069N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 4069N IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 4069 F0 "IC" 100 125 50 H V L B F1 "4069N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -200 -200 200 0 P 2 1 0 0 200 0 -200 200 P 2 1 0 0 -200 200 -200 -200 X I 1 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4069 P 2 2 0 0 -200 -200 200 0 P 2 2 0 0 200 0 -200 200 P 2 2 0 0 -200 200 -200 -200 X I 3 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4069 P 2 3 0 0 -200 -200 200 0 P 2 3 0 0 200 0 -200 200 P 2 3 0 0 -200 200 -200 -200 X I 5 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4069 P 2 4 0 0 -200 -200 200 0 P 2 4 0 0 200 0 -200 200 P 2 4 0 0 -200 200 -200 -200 X I 9 -400 0 200 R 40 40 4 1 I X O 8 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 4069 P 2 5 0 0 -200 -200 200 0 P 2 5 0 0 200 0 -200 200 P 2 5 0 0 -200 200 -200 -200 X I 11 -400 0 200 R 40 40 5 1 I X O 10 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 4069 P 2 6 0 0 -200 -200 200 0 P 2 6 0 0 200 0 -200 200 P 2 6 0 0 -200 200 -200 -200 X I 13 -400 0 200 R 40 40 6 1 I X O 12 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 14 0 300 200 D 40 40 7 1 W X VSS 7 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 4070D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4070D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4070 F0 "IC" 100 125 50 H V L B F1 "4070D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 70 100 -100 100 A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 70 -100 -100 -100 P 2 1 0 0 -100 200 -100 -200 T 0 20 20 100 0 1 0 e X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4070 P 2 2 0 0 70 100 -100 100 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 70 -100 -100 -100 P 2 2 0 0 -100 200 -100 -200 T 0 20 20 100 0 2 0 e X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4070 P 2 3 0 0 70 100 -100 100 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 70 -100 -100 -100 P 2 3 0 0 -100 200 -100 -200 T 0 20 20 100 0 3 0 e X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4070 P 2 4 0 0 70 100 -100 100 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 70 -100 -100 -100 P 2 4 0 0 -100 200 -100 -200 T 0 20 20 100 0 4 0 e X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4070N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4070N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4070 F0 "IC" 100 125 50 H V L B F1 "4070N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 70 100 -100 100 A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 70 -100 -100 -100 P 2 1 0 0 -100 200 -100 -200 T 0 20 20 100 0 1 0 e X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4070 P 2 2 0 0 70 100 -100 100 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 70 -100 -100 -100 P 2 2 0 0 -100 200 -100 -200 T 0 20 20 100 0 2 0 e X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4070 P 2 3 0 0 70 100 -100 100 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 70 -100 -100 -100 P 2 3 0 0 -100 200 -100 -200 T 0 20 20 100 0 3 0 e X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4070 P 2 4 0 0 70 100 -100 100 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 70 -100 -100 -100 P 2 4 0 0 -100 200 -100 -200 T 0 20 20 100 0 4 0 e X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4071D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4071D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4071 F0 "IC" 100 125 50 H V L B F1 "4071D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 70 100 -100 100 P 2 1 0 0 70 -100 -100 -100 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4071 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 70 100 -100 100 P 2 2 0 0 70 -100 -100 -100 P 2 2 0 0 -100 200 -100 -200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4071 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 70 100 -100 100 P 2 3 0 0 70 -100 -100 -100 P 2 3 0 0 -100 200 -100 -200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4071 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 70 100 -100 100 P 2 4 0 0 70 -100 -100 -100 P 2 4 0 0 -100 200 -100 -200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4071N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4071N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4071 F0 "IC" 100 125 50 H V L B F1 "4071N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 70 100 -100 100 P 2 1 0 0 70 -100 -100 -100 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4071 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 70 100 -100 100 P 2 2 0 0 70 -100 -100 -100 P 2 2 0 0 -100 200 -100 -200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4071 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 70 100 -100 100 P 2 3 0 0 70 -100 -100 -100 P 2 3 0 0 -100 200 -100 -200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4071 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 70 100 -100 100 P 2 4 0 0 70 -100 -100 -100 P 2 4 0 0 -100 200 -100 -200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4072D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4072D IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4072 F0 "IC" 150 200 50 H V L B F1 "4072D" 150 -275 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 200 70 200 P 2 1 0 0 -100 -200 70 -200 P 2 1 0 0 -100 100 100 100 P 2 1 0 0 -100 -100 100 -100 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4072 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 200 70 200 P 2 2 0 0 -100 -200 70 -200 P 2 2 0 0 -100 100 100 100 P 2 2 0 0 -100 -100 100 -100 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4072N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4072N IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4072 F0 "IC" 150 200 50 H V L B F1 "4072N" 150 -275 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 200 70 200 P 2 1 0 0 -100 -200 70 -200 P 2 1 0 0 -100 100 100 100 P 2 1 0 0 -100 -100 100 -100 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4072 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 200 70 200 P 2 2 0 0 -100 -200 70 -200 P 2 2 0 0 -100 100 100 100 P 2 2 0 0 -100 -100 100 -100 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4073D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4073D IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4073 F0 "IC" 100 125 50 H V L B F1 "4073D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4073 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4073 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4073N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4073N IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4073 F0 "IC" 100 125 50 H V L B F1 "4073N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4073 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4073 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4075D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4075D IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4075 F0 "IC" 100 125 50 H V L B F1 "4075D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 0 100 0 A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4075 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 0 100 0 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4075 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 0 100 0 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4075N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF 4075N IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: 4075 F0 "IC" 100 125 50 H V L B F1 "4075N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -100 -100 70 -100 P 2 1 0 0 -100 100 70 100 P 2 1 0 0 -100 0 100 0 A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 0 200 R 40 40 1 1 I X I2 8 -300 -100 200 R 40 40 1 1 I X O 9 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4075 P 2 2 0 0 -100 -100 70 -100 P 2 2 0 0 -100 100 70 100 P 2 2 0 0 -100 0 100 0 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 X I0 3 -300 100 200 R 40 40 2 1 I X I1 4 -300 0 200 R 40 40 2 1 I X I2 5 -300 -100 200 R 40 40 2 1 I X O 6 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4075 P 2 3 0 0 -100 -100 70 -100 P 2 3 0 0 -100 100 70 100 P 2 3 0 0 -100 0 100 0 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 X I0 11 -300 100 200 R 40 40 3 1 I X I1 12 -300 0 200 R 40 40 3 1 I X I2 13 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 14 0 300 200 D 40 40 4 1 W X VSS 7 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: 4076D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4076D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4076 F0 "IC" -300 625 50 H V L B F1 "4076D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 7 -500 -200 200 R 40 40 1 1 I C X CLR 15 -500 -500 200 R 40 40 1 1 I X D0 14 -500 500 200 R 40 40 1 1 I X D1 13 -500 400 200 R 40 40 1 1 I X D2 12 -500 300 200 R 40 40 1 1 I X D3 11 -500 200 200 R 40 40 1 1 I X DID@1 9 -500 0 200 R 40 40 1 1 I X DID@2 10 -500 -100 200 R 40 40 1 1 I X DOD@1 1 -500 -300 200 R 40 40 1 1 I X DOD@2 2 -500 -400 200 R 40 40 1 1 I X Q0 3 500 500 200 L 40 40 1 1 O X Q1 4 500 400 200 L 40 40 1 1 O X Q2 5 500 300 200 L 40 40 1 1 O X Q3 6 500 200 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4076N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4076N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4076 F0 "IC" -300 625 50 H V L B F1 "4076N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 7 -500 -200 200 R 40 40 1 1 I C X CLR 15 -500 -500 200 R 40 40 1 1 I X D0 14 -500 500 200 R 40 40 1 1 I X D1 13 -500 400 200 R 40 40 1 1 I X D2 12 -500 300 200 R 40 40 1 1 I X D3 11 -500 200 200 R 40 40 1 1 I X DID@1 9 -500 0 200 R 40 40 1 1 I X DID@2 10 -500 -100 200 R 40 40 1 1 I X DOD@1 1 -500 -300 200 R 40 40 1 1 I X DOD@2 2 -500 -400 200 R 40 40 1 1 I X Q0 3 500 500 200 L 40 40 1 1 O X Q1 4 500 400 200 L 40 40 1 1 O X Q2 5 500 300 200 L 40 40 1 1 O X Q3 6 500 200 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4077D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4077D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4077 F0 "IC" 100 125 50 H V L B F1 "4077D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 70 100 -100 100 P 2 1 0 0 70 -100 -100 -100 P 2 1 0 0 -100 200 -100 -200 T 0 20 20 100 0 1 0 e X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4077 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 70 100 -100 100 P 2 2 0 0 70 -100 -100 -100 P 2 2 0 0 -100 200 -100 -200 T 0 20 20 100 0 2 0 e X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4077 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 70 100 -100 100 P 2 3 0 0 70 -100 -100 -100 P 2 3 0 0 -100 200 -100 -200 T 0 20 20 100 0 3 0 e X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4077 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 70 100 -100 100 P 2 4 0 0 70 -100 -100 -100 P 2 4 0 0 -100 200 -100 -200 T 0 20 20 100 0 4 0 e X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4077N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4077N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4077 F0 "IC" 100 125 50 H V L B F1 "4077N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 70 100 -100 100 P 2 1 0 0 70 -100 -100 -100 P 2 1 0 0 -100 200 -100 -200 T 0 20 20 100 0 1 0 e X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4077 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 70 100 -100 100 P 2 2 0 0 70 -100 -100 -100 P 2 2 0 0 -100 200 -100 -200 T 0 20 20 100 0 2 0 e X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4077 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 70 100 -100 100 P 2 3 0 0 70 -100 -100 -100 P 2 3 0 0 -100 200 -100 -200 T 0 20 20 100 0 3 0 e X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4077 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 70 100 -100 100 P 2 4 0 0 70 -100 -100 -100 P 2 4 0 0 -100 200 -100 -200 T 0 20 20 100 0 4 0 e X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4078D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4078D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4078 F0 "IC" 200 200 50 H V L B F1 "4078D" 200 -275 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 300 200 -3599 -2701 1 1 0 N 100 300 -100 500 A -100 -300 200 -899 -1 1 1 0 N -100 -500 100 -300 P 2 1 0 0 -100 300 100 300 P 2 1 0 0 -100 200 100 200 P 2 1 0 0 -100 100 100 100 P 2 1 0 0 -100 -100 100 -100 P 2 1 0 0 -100 -200 100 -200 P 2 1 0 0 100 300 100 -300 P 2 1 0 0 -100 -300 100 -300 P 2 1 0 0 70 400 -100 400 P 2 1 0 0 70 -400 -100 -400 P 2 1 0 0 -100 500 -100 -500 X I0 2 -300 400 200 R 40 40 1 1 I X I1 3 -300 300 200 R 40 40 1 1 I X I2 4 -300 200 200 R 40 40 1 1 I X I3 5 -300 100 200 R 40 40 1 1 I X I4 9 -300 -100 200 R 40 40 1 1 I X I5 10 -300 -200 200 R 40 40 1 1 I X I6 11 -300 -300 200 R 40 40 1 1 I X I7 12 -300 -400 200 R 40 40 1 1 I X J 13 300 0 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4078N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4078N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4078 F0 "IC" 200 200 50 H V L B F1 "4078N" 200 -275 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 300 200 -3599 -2701 1 1 0 N 100 300 -100 500 A -100 -300 200 -899 -1 1 1 0 N -100 -500 100 -300 P 2 1 0 0 -100 300 100 300 P 2 1 0 0 -100 200 100 200 P 2 1 0 0 -100 100 100 100 P 2 1 0 0 -100 -100 100 -100 P 2 1 0 0 -100 -200 100 -200 P 2 1 0 0 100 300 100 -300 P 2 1 0 0 -100 -300 100 -300 P 2 1 0 0 70 400 -100 400 P 2 1 0 0 70 -400 -100 -400 P 2 1 0 0 -100 500 -100 -500 X I0 2 -300 400 200 R 40 40 1 1 I X I1 3 -300 300 200 R 40 40 1 1 I X I2 4 -300 200 200 R 40 40 1 1 I X I3 5 -300 100 200 R 40 40 1 1 I X I4 9 -300 -100 200 R 40 40 1 1 I X I5 10 -300 -200 200 R 40 40 1 1 I X I6 11 -300 -300 200 R 40 40 1 1 I X I7 12 -300 -400 200 R 40 40 1 1 I X J 13 300 0 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4081D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4081D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4081 F0 "IC" 100 125 50 H V L B F1 "4081D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -100 200 -100 -200 A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4081 P 2 2 0 0 -100 200 -100 -200 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4081 P 2 3 0 0 -100 200 -100 -200 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4081 P 2 4 0 0 -100 200 -100 -200 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4081N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4081N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4081 F0 "IC" 100 125 50 H V L B F1 "4081N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -100 200 -100 -200 A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4081 P 2 2 0 0 -100 200 -100 -200 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O # Gate Name: C # Symbol Name: 4081 P 2 3 0 0 -100 200 -100 -200 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O # Gate Name: D # Symbol Name: 4081 P 2 4 0 0 -100 200 -100 -200 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4082D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4082D IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4082 F0 "IC" 150 175 50 H V L B F1 "4082D" 150 -250 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4082 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4082N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4082N IC 0 40 Y Y 3 L N # Gate Name: A # Symbol Name: 4082 F0 "IC" 150 175 50 H V L B F1 "4082N" 150 -250 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 100 200 -3599 -2701 1 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 1 1 0 N -100 -300 100 -100 P 2 1 0 0 100 100 100 -100 P 2 1 0 0 -100 300 -100 -300 X I0 2 -300 200 200 R 40 40 1 1 I X I1 3 -300 100 200 R 40 40 1 1 I X I2 4 -300 -100 200 R 40 40 1 1 I X I3 5 -300 -200 200 R 40 40 1 1 I X O 1 300 0 200 L 40 40 1 1 O # Gate Name: B # Symbol Name: 4082 A -100 100 200 -3599 -2701 2 1 0 N 100 100 -100 300 A -100 -100 200 -899 -1 2 1 0 N -100 -300 100 -100 P 2 2 0 0 100 100 100 -100 P 2 2 0 0 -100 300 -100 -300 X I0 9 -300 200 200 R 40 40 2 1 I X I1 10 -300 100 200 R 40 40 2 1 I X I2 11 -300 -100 200 R 40 40 2 1 I X I3 12 -300 -200 200 R 40 40 2 1 I X O 13 300 0 200 L 40 40 2 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 7 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4089D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4089D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4089 F0 "IC" -300 625 50 H V L B F1 "4089D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X 15 1 500 0 200 L 40 40 1 1 O X A 14 -500 500 200 R 40 40 1 1 I X B 15 -500 400 200 R 40 40 1 1 I X C 2 -500 300 200 R 40 40 1 1 I X CAS 12 -500 -200 200 R 40 40 1 1 I X CLK 9 -500 0 200 R 40 40 1 1 I C X CLR 13 -500 -500 200 R 40 40 1 1 I X D 3 -500 200 200 R 40 40 1 1 I X INHI 11 -500 -400 200 R 40 40 1 1 I X INO 7 500 100 200 L 40 40 1 1 O X OUT 6 500 500 200 L 40 40 1 1 O X OUT\ 5 500 300 200 L 40 40 1 1 O X S15 4 -500 -300 200 R 40 40 1 1 I X ST 10 -500 -100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4089N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4089N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4089 F0 "IC" -300 625 50 H V L B F1 "4089N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X 15 1 500 0 200 L 40 40 1 1 O X A 14 -500 500 200 R 40 40 1 1 I X B 15 -500 400 200 R 40 40 1 1 I X C 2 -500 300 200 R 40 40 1 1 I X CAS 12 -500 -200 200 R 40 40 1 1 I X CLK 9 -500 0 200 R 40 40 1 1 I C X CLR 13 -500 -500 200 R 40 40 1 1 I X D 3 -500 200 200 R 40 40 1 1 I X INHI 11 -500 -400 200 R 40 40 1 1 I X INO 7 500 100 200 L 40 40 1 1 O X OUT 6 500 500 200 L 40 40 1 1 O X OUT\ 5 500 300 200 L 40 40 1 1 O X S15 4 -500 -300 200 R 40 40 1 1 I X ST 10 -500 -100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4093D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4093D IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4093 F0 "IC" 100 125 50 H V L B F1 "4093D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 P 2 1 0 0 -50 40 10 -40 P 2 1 0 0 -10 40 50 -40 P 2 1 0 0 -10 40 -80 40 P 2 1 0 0 10 -40 70 -40 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4093 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 P 2 2 0 0 -50 40 10 -40 P 2 2 0 0 -10 40 50 -40 P 2 2 0 0 -10 40 -80 40 P 2 2 0 0 10 -40 70 -40 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4093 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 P 2 3 0 0 -50 40 10 -40 P 2 3 0 0 -10 40 50 -40 P 2 3 0 0 -10 40 -80 40 P 2 3 0 0 10 -40 70 -40 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4093 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 200 -100 -200 P 2 4 0 0 -50 40 10 -40 P 2 4 0 0 -10 40 50 -40 P 2 4 0 0 -10 40 -80 40 P 2 4 0 0 10 -40 70 -40 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4093N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 5 # DEF 4093N IC 0 40 Y Y 5 L N # Gate Name: A # Symbol Name: 4093 F0 "IC" 100 125 50 H V L B F1 "4093N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW A -100 0 200 -899 899 1 1 0 N -100 -200 -100 200 P 2 1 0 0 -100 200 -100 -200 P 2 1 0 0 -50 40 10 -40 P 2 1 0 0 -10 40 50 -40 P 2 1 0 0 -10 40 -80 40 P 2 1 0 0 10 -40 70 -40 X I0 1 -300 100 200 R 40 40 1 1 I X I1 2 -300 -100 200 R 40 40 1 1 I X O 3 300 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 4093 A -100 0 200 -899 899 2 1 0 N -100 -200 -100 200 P 2 2 0 0 -100 200 -100 -200 P 2 2 0 0 -50 40 10 -40 P 2 2 0 0 -10 40 50 -40 P 2 2 0 0 -10 40 -80 40 P 2 2 0 0 10 -40 70 -40 X I0 5 -300 100 200 R 40 40 2 1 I X I1 6 -300 -100 200 R 40 40 2 1 I X O 4 300 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 4093 A -100 0 200 -899 899 3 1 0 N -100 -200 -100 200 P 2 3 0 0 -100 200 -100 -200 P 2 3 0 0 -50 40 10 -40 P 2 3 0 0 -10 40 50 -40 P 2 3 0 0 -10 40 -80 40 P 2 3 0 0 10 -40 70 -40 X I0 8 -300 100 200 R 40 40 3 1 I X I1 9 -300 -100 200 R 40 40 3 1 I X O 10 300 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 4093 A -100 0 200 -899 899 4 1 0 N -100 -200 -100 200 P 2 4 0 0 -100 200 -100 -200 P 2 4 0 0 -50 40 10 -40 P 2 4 0 0 -10 40 50 -40 P 2 4 0 0 -10 40 -80 40 P 2 4 0 0 10 -40 70 -40 X I0 12 -300 100 200 R 40 40 4 1 I X I1 13 -300 -100 200 R 40 40 4 1 I X O 11 300 0 200 L 40 40 4 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 14 0 300 200 D 40 40 5 1 W X VSS 7 0 -300 200 U 40 40 5 1 W ENDDRAW ENDDEF # # Dev Name: 4094D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4094D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4094 F0 "IC" -400 625 50 H V L B F1 "4094D" -400 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -400 600 P 2 1 0 0 -400 600 -400 -600 X CLK 3 -600 300 200 R 40 40 1 1 I C X D 2 -600 400 200 R 40 40 1 1 I X OE 15 -600 200 200 R 40 40 1 1 I X Q1 4 500 500 200 L 40 40 1 1 O X Q2 5 500 400 200 L 40 40 1 1 O X Q3 6 500 300 200 L 40 40 1 1 O X Q4 7 500 200 200 L 40 40 1 1 O X Q5 14 500 100 200 L 40 40 1 1 O X Q6 13 500 0 200 L 40 40 1 1 O X Q7 12 500 -100 200 L 40 40 1 1 O X Q8 11 500 -200 200 L 40 40 1 1 O X QS 9 500 -400 200 L 40 40 1 1 O X QS* 10 500 -500 200 L 40 40 1 1 O X STR 1 -600 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4094N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4094N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4094 F0 "IC" -400 625 50 H V L B F1 "4094N" -400 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -400 600 P 2 1 0 0 -400 600 -400 -600 X CLK 3 -600 300 200 R 40 40 1 1 I C X D 2 -600 400 200 R 40 40 1 1 I X OE 15 -600 200 200 R 40 40 1 1 I X Q1 4 500 500 200 L 40 40 1 1 O X Q2 5 500 400 200 L 40 40 1 1 O X Q3 6 500 300 200 L 40 40 1 1 O X Q4 7 500 200 200 L 40 40 1 1 O X Q5 14 500 100 200 L 40 40 1 1 O X Q6 13 500 0 200 L 40 40 1 1 O X Q7 12 500 -100 200 L 40 40 1 1 O X Q8 11 500 -200 200 L 40 40 1 1 O X QS 9 500 -400 200 L 40 40 1 1 O X QS* 10 500 -500 200 L 40 40 1 1 O X STR 1 -600 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4095D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4095D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4095 F0 "IC" -300 625 50 H V L B F1 "4095D" -300 -700 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 12 -500 0 200 R 40 40 1 1 I C X J1 3 -500 400 200 R 40 40 1 1 I X J2 4 -500 300 200 R 40 40 1 1 I X J3 5 -500 200 200 R 40 40 1 1 I X K1 11 -500 -200 200 R 40 40 1 1 I X K2 10 -500 -300 200 R 40 40 1 1 I X K3 9 -500 -400 200 R 40 40 1 1 I X Q 8 500 300 200 L 40 40 1 1 O X Q\ 6 500 -300 200 L 40 40 1 1 O X R 2 -500 -500 200 R 40 40 1 1 I X S 13 -500 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4095N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4095N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4095 F0 "IC" -300 625 50 H V L B F1 "4095N" -300 -700 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 12 -500 0 200 R 40 40 1 1 I C X J1 3 -500 400 200 R 40 40 1 1 I X J2 4 -500 300 200 R 40 40 1 1 I X J3 5 -500 200 200 R 40 40 1 1 I X K1 11 -500 -200 200 R 40 40 1 1 I X K2 10 -500 -300 200 R 40 40 1 1 I X K3 9 -500 -400 200 R 40 40 1 1 I X Q 8 500 300 200 L 40 40 1 1 O X Q\ 6 500 -300 200 L 40 40 1 1 O X R 2 -500 -500 200 R 40 40 1 1 I X S 13 -500 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4096D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4096D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4096 F0 "IC" -300 625 50 H V L B F1 "4096D" -300 -700 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 12 -500 0 200 R 40 40 1 1 I C X J1 3 -500 400 200 R 40 40 1 1 I X J2 4 -500 300 200 R 40 40 1 1 I X J3 5 -500 200 200 R 40 40 1 1 I I X K1 11 -500 -200 200 R 40 40 1 1 I X K2 10 -500 -300 200 R 40 40 1 1 I X K3 9 -500 -400 200 R 40 40 1 1 I I X Q 8 500 300 200 L 40 40 1 1 O X Q\ 6 500 -300 200 L 40 40 1 1 O X R 2 -500 -500 200 R 40 40 1 1 I X S 13 -500 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4096N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4096N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4096 F0 "IC" -300 625 50 H V L B F1 "4096N" -300 -700 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X CLK 12 -500 0 200 R 40 40 1 1 I C X J1 3 -500 400 200 R 40 40 1 1 I X J2 4 -500 300 200 R 40 40 1 1 I X J3 5 -500 200 200 R 40 40 1 1 I I X K1 11 -500 -200 200 R 40 40 1 1 I X K2 10 -500 -300 200 R 40 40 1 1 I X K3 9 -500 -400 200 R 40 40 1 1 I I X Q 8 500 300 200 L 40 40 1 1 O X Q\ 6 500 -300 200 L 40 40 1 1 O X R 2 -500 -500 200 R 40 40 1 1 I X S 13 -500 500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4097D # Package Name: SO24W # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4097D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4097 F0 "IC" -300 1125 50 H V L B F1 "4097D" -300 -1300 50 H V L B F2 "40xx-SO24W" 0 150 50 H I C C DRAW P 2 1 0 0 -300 1100 -300 -1200 P 2 1 0 0 -300 -1200 300 -1200 P 2 1 0 0 300 -1200 300 1100 P 2 1 0 0 300 1100 -300 1100 X A 10 -500 900 200 R 40 40 1 1 I X B 11 -500 800 200 R 40 40 1 1 I X C 14 -500 700 200 R 40 40 1 1 I X INH 13 -500 1000 200 R 40 40 1 1 I X X 1 500 500 200 L 40 40 1 1 O X X0 9 -500 500 200 R 40 40 1 1 I X X1 8 -500 400 200 R 40 40 1 1 I X X2 7 -500 300 200 R 40 40 1 1 I X X3 6 -500 200 200 R 40 40 1 1 I X X4 5 -500 100 200 R 40 40 1 1 I X X5 4 -500 0 200 R 40 40 1 1 I X X6 3 -500 -100 200 R 40 40 1 1 I X X7 2 -500 -200 200 R 40 40 1 1 I X Y 17 500 -400 200 L 40 40 1 1 O X Y0 23 -500 -400 200 R 40 40 1 1 I X Y1 22 -500 -500 200 R 40 40 1 1 I X Y2 21 -500 -600 200 R 40 40 1 1 I X Y3 20 -500 -700 200 R 40 40 1 1 I X Y4 19 -500 -800 200 R 40 40 1 1 I X Y5 18 -500 -900 200 R 40 40 1 1 I X Y6 16 -500 -1000 200 R 40 40 1 1 I X Y7 15 -500 -1100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 24 0 300 200 D 40 40 2 1 W X VSS 12 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4097N # Package Name: DIL24-6 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4097N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4097 F0 "IC" -300 1125 50 H V L B F1 "4097N" -300 -1300 50 H V L B F2 "40xx-DIL24-6" 0 150 50 H I C C DRAW P 2 1 0 0 -300 1100 -300 -1200 P 2 1 0 0 -300 -1200 300 -1200 P 2 1 0 0 300 -1200 300 1100 P 2 1 0 0 300 1100 -300 1100 X A 10 -500 900 200 R 40 40 1 1 I X B 11 -500 800 200 R 40 40 1 1 I X C 14 -500 700 200 R 40 40 1 1 I X INH 13 -500 1000 200 R 40 40 1 1 I X X 1 500 500 200 L 40 40 1 1 O X X0 9 -500 500 200 R 40 40 1 1 I X X1 8 -500 400 200 R 40 40 1 1 I X X2 7 -500 300 200 R 40 40 1 1 I X X3 6 -500 200 200 R 40 40 1 1 I X X4 5 -500 100 200 R 40 40 1 1 I X X5 4 -500 0 200 R 40 40 1 1 I X X6 3 -500 -100 200 R 40 40 1 1 I X X7 2 -500 -200 200 R 40 40 1 1 I X Y 17 500 -400 200 L 40 40 1 1 O X Y0 23 -500 -400 200 R 40 40 1 1 I X Y1 22 -500 -500 200 R 40 40 1 1 I X Y2 21 -500 -600 200 R 40 40 1 1 I X Y3 20 -500 -700 200 R 40 40 1 1 I X Y4 19 -500 -800 200 R 40 40 1 1 I X Y5 18 -500 -900 200 R 40 40 1 1 I X Y6 16 -500 -1000 200 R 40 40 1 1 I X Y7 15 -500 -1100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 24 0 300 200 D 40 40 2 1 W X VSS 12 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4098D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4098D IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: 4098 F0 "IC" -500 -500 50 H V L B F1 "4098D" -500 -400 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -500 -300 500 -300 P 2 1 0 0 500 -300 500 300 P 2 1 0 0 500 300 -500 300 P 2 1 0 0 -500 300 -500 -300 X CX 1 -200 500 200 D 40 40 1 1 P X Q 6 700 200 200 L 40 40 1 1 O X Q\ 7 700 -200 200 L 40 40 1 1 O X RST 3 -700 -200 200 R 40 40 1 1 I I X RXCX 2 200 500 200 D 40 40 1 1 P X TR+ 4 -700 200 200 R 40 40 1 1 I X TR- 5 -700 0 200 R 40 40 1 1 I # Gate Name: G$2 # Symbol Name: 4098 P 2 2 0 0 -500 -300 500 -300 P 2 2 0 0 500 -300 500 300 P 2 2 0 0 500 300 -500 300 P 2 2 0 0 -500 300 -500 -300 X CX 15 -200 500 200 D 40 40 2 1 P X Q 10 700 200 200 L 40 40 2 1 O X Q\ 9 700 -200 200 L 40 40 2 1 O X RST 13 -700 -200 200 R 40 40 2 1 I I X RXCX 14 200 500 200 D 40 40 2 1 P X TR+ 12 -700 200 200 R 40 40 2 1 I X TR- 11 -700 0 200 R 40 40 2 1 I # Gate Name: G$3 # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 16 0 300 200 D 40 40 3 1 W X VSS 8 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4098N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF 4098N IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: 4098 F0 "IC" -500 -500 50 H V L B F1 "4098N" -500 -400 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -500 -300 500 -300 P 2 1 0 0 500 -300 500 300 P 2 1 0 0 500 300 -500 300 P 2 1 0 0 -500 300 -500 -300 X CX 1 -200 500 200 D 40 40 1 1 P X Q 6 700 200 200 L 40 40 1 1 O X Q\ 7 700 -200 200 L 40 40 1 1 O X RST 3 -700 -200 200 R 40 40 1 1 I I X RXCX 2 200 500 200 D 40 40 1 1 P X TR+ 4 -700 200 200 R 40 40 1 1 I X TR- 5 -700 0 200 R 40 40 1 1 I # Gate Name: G$2 # Symbol Name: 4098 P 2 2 0 0 -500 -300 500 -300 P 2 2 0 0 500 -300 500 300 P 2 2 0 0 500 300 -500 300 P 2 2 0 0 -500 300 -500 -300 X CX 15 -200 500 200 D 40 40 2 1 P X Q 10 700 200 200 L 40 40 2 1 O X Q\ 9 700 -200 200 L 40 40 2 1 O X RST 13 -700 -200 200 R 40 40 2 1 I I X RXCX 14 200 500 200 D 40 40 2 1 P X TR+ 12 -700 200 200 R 40 40 2 1 I X TR- 11 -700 0 200 R 40 40 2 1 I # Gate Name: G$3 # Symbol Name: PWRN T 1 50 175 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 16 0 300 200 D 40 40 3 1 W X VSS 8 0 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: 4099D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4099D IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4099 F0 "IC" -300 425 50 H V L B F1 "4099D" -300 -600 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A0 5 -500 300 200 R 40 40 1 1 I X A1 6 -500 200 200 R 40 40 1 1 I X A2 7 -500 100 200 R 40 40 1 1 I X CLR 2 -500 -400 200 R 40 40 1 1 I X D 3 -500 -300 200 R 40 40 1 1 I X E\ 4 -500 -200 200 R 40 40 1 1 I X Q0 9 500 300 200 L 40 40 1 1 O X Q1 10 500 200 200 L 40 40 1 1 O X Q2 11 500 100 200 L 40 40 1 1 O X Q3 12 500 0 200 L 40 40 1 1 O X Q4 13 500 -100 200 L 40 40 1 1 O X Q5 14 500 -200 200 L 40 40 1 1 O X Q6 15 500 -300 200 L 40 40 1 1 O X Q7 1 500 -400 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4099N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4099N IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: 4099 F0 "IC" -300 425 50 H V L B F1 "4099N" -300 -600 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A0 5 -500 300 200 R 40 40 1 1 I X A1 6 -500 200 200 R 40 40 1 1 I X A2 7 -500 100 200 R 40 40 1 1 I X CLR 2 -500 -400 200 R 40 40 1 1 I X D 3 -500 -300 200 R 40 40 1 1 I X E\ 4 -500 -200 200 R 40 40 1 1 I X Q0 9 500 300 200 L 40 40 1 1 O X Q1 10 500 200 200 L 40 40 1 1 O X Q2 11 500 100 200 L 40 40 1 1 O X Q3 12 500 0 200 L 40 40 1 1 O X Q4 13 500 -100 200 L 40 40 1 1 O X Q5 14 500 -200 200 L 40 40 1 1 O X Q6 15 500 -300 200 L 40 40 1 1 O X Q7 1 500 -400 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4160D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4160D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4160D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4160N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4160N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4160N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4161D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4161D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4161D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4161N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4161N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4161N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4162D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4162D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4162D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4162N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4162N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4162N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4163D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4163D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4163D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4163N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4163N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4160 F0 "IC" -300 525 50 H V L B F1 "4163N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLEAR\ 1 -500 -100 200 R 40 40 1 1 I X CLK 2 -500 -300 200 R 40 40 1 1 I C X CO 15 500 -300 200 L 40 40 1 1 O X LOAD\ 9 -500 -200 200 R 40 40 1 1 I X P1 3 -500 400 200 R 40 40 1 1 I X P2 4 -500 300 200 R 40 40 1 1 I X P3 5 -500 200 200 R 40 40 1 1 I X P4 6 -500 100 200 R 40 40 1 1 I X PE 7 -500 -500 200 R 40 40 1 1 I X Q1 14 500 400 200 L 40 40 1 1 O X Q2 13 500 300 200 L 40 40 1 1 O X Q3 12 500 200 200 L 40 40 1 1 O X Q4 11 500 100 200 L 40 40 1 1 O X TE 10 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4174D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4174D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4174 F0 "IC" -300 525 50 H V L B F1 "4174D" -300 -600 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X CLK 9 -500 -400 200 R 40 40 1 1 I C X D0 3 -500 400 200 R 40 40 1 1 I X D1 4 -500 300 200 R 40 40 1 1 I X D2 6 -500 200 200 R 40 40 1 1 I X D3 11 -500 100 200 R 40 40 1 1 I X D4 13 -500 0 200 R 40 40 1 1 I X D5 14 -500 -100 200 R 40 40 1 1 I X Q0 2 500 400 200 L 40 40 1 1 O X Q1 5 500 300 200 L 40 40 1 1 O X Q2 7 500 200 200 L 40 40 1 1 O X Q3 10 500 100 200 L 40 40 1 1 O X Q4 12 500 0 200 L 40 40 1 1 O X Q5 15 500 -100 200 L 40 40 1 1 O X RESET\ 1 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4174N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4174N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4174 F0 "IC" -300 525 50 H V L B F1 "4174N" -300 -600 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X CLK 9 -500 -400 200 R 40 40 1 1 I C X D0 3 -500 400 200 R 40 40 1 1 I X D1 4 -500 300 200 R 40 40 1 1 I X D2 6 -500 200 200 R 40 40 1 1 I X D3 11 -500 100 200 R 40 40 1 1 I X D4 13 -500 0 200 R 40 40 1 1 I X D5 14 -500 -100 200 R 40 40 1 1 I X Q0 2 500 400 200 L 40 40 1 1 O X Q1 5 500 300 200 L 40 40 1 1 O X Q2 7 500 200 200 L 40 40 1 1 O X Q3 10 500 100 200 L 40 40 1 1 O X Q4 12 500 0 200 L 40 40 1 1 O X Q5 15 500 -100 200 L 40 40 1 1 O X RESET\ 1 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4175D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4175D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4175 F0 "IC" -300 525 50 H V L B F1 "4175D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 9 -500 -500 200 R 40 40 1 1 I C X D0 4 -500 400 200 R 40 40 1 1 I X D1 5 -500 300 200 R 40 40 1 1 I X D2 12 -500 200 200 R 40 40 1 1 I X D3 13 -500 100 200 R 40 40 1 1 I X Q0 2 500 400 200 L 40 40 1 1 O X Q0\ 3 500 300 200 L 40 40 1 1 O X Q0\1 6 500 100 200 L 40 40 1 1 O X Q0\2 11 500 -100 200 L 40 40 1 1 O X Q0\3 14 500 -300 200 L 40 40 1 1 O X Q1 7 500 200 200 L 40 40 1 1 O X Q2 10 500 0 200 L 40 40 1 1 O X Q3 15 500 -200 200 L 40 40 1 1 O X RESET\ 1 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4175N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4175N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4175 F0 "IC" -300 525 50 H V L B F1 "4175N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 9 -500 -500 200 R 40 40 1 1 I C X D0 4 -500 400 200 R 40 40 1 1 I X D1 5 -500 300 200 R 40 40 1 1 I X D2 12 -500 200 200 R 40 40 1 1 I X D3 13 -500 100 200 R 40 40 1 1 I X Q0 2 500 400 200 L 40 40 1 1 O X Q0\ 3 500 300 200 L 40 40 1 1 O X Q0\1 6 500 100 200 L 40 40 1 1 O X Q0\2 11 500 -100 200 L 40 40 1 1 O X Q0\3 14 500 -300 200 L 40 40 1 1 O X Q1 7 500 200 200 L 40 40 1 1 O X Q2 10 500 0 200 L 40 40 1 1 O X Q3 15 500 -200 200 L 40 40 1 1 O X RESET\ 1 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4194D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4194D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4194 F0 "IC" -300 725 50 H V L B F1 "4194D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X CLK 11 -500 -600 200 R 40 40 1 1 I X DP0 3 -500 600 200 R 40 40 1 1 I X DP1 4 -500 500 200 R 40 40 1 1 I X DP2 5 -500 400 200 R 40 40 1 1 I X DP3 6 -500 300 200 R 40 40 1 1 I X DSL 7 -500 0 200 R 40 40 1 1 I X DSR 2 -500 100 200 R 40 40 1 1 I X Q0 15 500 600 200 L 40 40 1 1 O X Q1 14 500 500 200 L 40 40 1 1 O X Q2 13 500 400 200 L 40 40 1 1 O X Q3 12 500 300 200 L 40 40 1 1 O X RESET\ 1 -500 -500 200 R 40 40 1 1 I X S0 9 -500 -200 200 R 40 40 1 1 I X S1 10 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4194N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4194N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4194 F0 "IC" -300 725 50 H V L B F1 "4194N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X CLK 11 -500 -600 200 R 40 40 1 1 I X DP0 3 -500 600 200 R 40 40 1 1 I X DP1 4 -500 500 200 R 40 40 1 1 I X DP2 5 -500 400 200 R 40 40 1 1 I X DP3 6 -500 300 200 R 40 40 1 1 I X DSL 7 -500 0 200 R 40 40 1 1 I X DSR 2 -500 100 200 R 40 40 1 1 I X Q0 15 500 600 200 L 40 40 1 1 O X Q1 14 500 500 200 L 40 40 1 1 O X Q2 13 500 400 200 L 40 40 1 1 O X Q3 12 500 300 200 L 40 40 1 1 O X RESET\ 1 -500 -500 200 R 40 40 1 1 I X S0 9 -500 -200 200 R 40 40 1 1 I X S1 10 -500 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4415D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4415D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4415 F0 "IC" -300 725 50 H V L B F1 "4415D" -300 -800 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X CLK 1 -500 -400 200 R 40 40 1 1 I X DIS\ 10 -500 -100 200 R 40 40 1 1 I X INH\ 15 -500 -600 200 R 40 40 1 1 I X OA 14 500 600 200 L 40 40 1 1 O X OB 13 500 500 200 L 40 40 1 1 O X OC 12 500 400 200 L 40 40 1 1 O X OD 11 500 300 200 L 40 40 1 1 O X SETA 3 -500 600 200 R 40 40 1 1 I X SETB 4 -500 500 200 R 40 40 1 1 I X SETC 5 -500 400 200 R 40 40 1 1 I X SETD 6 -500 300 200 R 40 40 1 1 I X SET\ 2 -500 -200 200 R 40 40 1 1 I X ST1\ 7 -500 0 200 R 40 40 1 1 I X ST2 9 -500 100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4415N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4415N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4415 F0 "IC" -300 725 50 H V L B F1 "4415N" -300 -800 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X CLK 1 -500 -400 200 R 40 40 1 1 I X DIS\ 10 -500 -100 200 R 40 40 1 1 I X INH\ 15 -500 -600 200 R 40 40 1 1 I X OA 14 500 600 200 L 40 40 1 1 O X OB 13 500 500 200 L 40 40 1 1 O X OC 12 500 400 200 L 40 40 1 1 O X OD 11 500 300 200 L 40 40 1 1 O X SETA 3 -500 600 200 R 40 40 1 1 I X SETB 4 -500 500 200 R 40 40 1 1 I X SETC 5 -500 400 200 R 40 40 1 1 I X SETD 6 -500 300 200 R 40 40 1 1 I X SET\ 2 -500 -200 200 R 40 40 1 1 I X ST1\ 7 -500 0 200 R 40 40 1 1 I X ST2 9 -500 100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4490D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4490D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4490 F0 "IC" -300 525 50 H V L B F1 "4490D" -300 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X AIN 1 -500 400 200 R 40 40 1 1 I X AO 15 500 400 200 L 40 40 1 1 O X BIN 14 -500 300 200 R 40 40 1 1 I X BO 2 500 300 200 L 40 40 1 1 O X CIN 3 -500 200 200 R 40 40 1 1 I X CO 13 500 200 200 L 40 40 1 1 O X DIN 12 -500 100 200 R 40 40 1 1 I X DO 4 500 100 200 L 40 40 1 1 O X EIN 5 -500 0 200 R 40 40 1 1 I X EO 11 500 0 200 L 40 40 1 1 O X FIN 10 -500 -100 200 R 40 40 1 1 I X FO 6 500 -100 200 L 40 40 1 1 O X OSCIN 7 -500 -300 200 R 40 40 1 1 I X OSCOUT 9 -500 -500 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 4490N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 4490N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 4490 F0 "IC" -300 525 50 H V L B F1 "4490N" -300 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X AIN 1 -500 400 200 R 40 40 1 1 I X AO 15 500 400 200 L 40 40 1 1 O X BIN 14 -500 300 200 R 40 40 1 1 I X BO 2 500 300 200 L 40 40 1 1 O X CIN 3 -500 200 200 R 40 40 1 1 I X CO 13 500 200 200 L 40 40 1 1 O X DIN 12 -500 100 200 R 40 40 1 1 I X DO 4 500 100 200 L 40 40 1 1 O X EIN 5 -500 0 200 R 40 40 1 1 I X EO 11 500 0 200 L 40 40 1 1 O X FIN 10 -500 -100 200 R 40 40 1 1 I X FO 6 500 -100 200 L 40 40 1 1 O X OSCIN 7 -500 -300 200 R 40 40 1 1 I X OSCOUT 9 -500 -500 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 40106D # Package Name: SO14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 40106D IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 40106 F0 "IC" 100 125 50 H V L B F1 "40106D" 100 -200 50 H V L B F2 "40xx-SO14" 0 150 50 H I C C DRAW P 2 1 0 0 -200 200 200 0 P 2 1 0 0 200 0 -200 -200 P 2 1 0 0 -200 -200 -200 200 P 2 1 0 0 -30 -50 -70 50 P 2 1 0 0 -80 -50 -120 50 P 2 1 0 0 -80 -50 -30 -50 P 2 1 0 0 -30 -50 5 -50 P 2 1 0 0 -155 50 -120 50 P 2 1 0 0 -120 50 -70 50 X I 1 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 40106 P 2 2 0 0 -200 200 200 0 P 2 2 0 0 200 0 -200 -200 P 2 2 0 0 -200 -200 -200 200 P 2 2 0 0 -30 -50 -70 50 P 2 2 0 0 -80 -50 -120 50 P 2 2 0 0 -80 -50 -30 -50 P 2 2 0 0 -30 -50 5 -50 P 2 2 0 0 -155 50 -120 50 P 2 2 0 0 -120 50 -70 50 X I 3 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 40106 P 2 3 0 0 -200 200 200 0 P 2 3 0 0 200 0 -200 -200 P 2 3 0 0 -200 -200 -200 200 P 2 3 0 0 -30 -50 -70 50 P 2 3 0 0 -80 -50 -120 50 P 2 3 0 0 -80 -50 -30 -50 P 2 3 0 0 -30 -50 5 -50 P 2 3 0 0 -155 50 -120 50 P 2 3 0 0 -120 50 -70 50 X I 5 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 40106 P 2 4 0 0 -200 200 200 0 P 2 4 0 0 200 0 -200 -200 P 2 4 0 0 -200 -200 -200 200 P 2 4 0 0 -30 -50 -70 50 P 2 4 0 0 -80 -50 -120 50 P 2 4 0 0 -80 -50 -30 -50 P 2 4 0 0 -30 -50 5 -50 P 2 4 0 0 -155 50 -120 50 P 2 4 0 0 -120 50 -70 50 X I 9 -400 0 200 R 40 40 4 1 I X O 8 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 40106 P 2 5 0 0 -200 200 200 0 P 2 5 0 0 200 0 -200 -200 P 2 5 0 0 -200 -200 -200 200 P 2 5 0 0 -30 -50 -70 50 P 2 5 0 0 -80 -50 -120 50 P 2 5 0 0 -80 -50 -30 -50 P 2 5 0 0 -30 -50 5 -50 P 2 5 0 0 -155 50 -120 50 P 2 5 0 0 -120 50 -70 50 X I 11 -400 0 200 R 40 40 5 1 I X O 10 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 40106 P 2 6 0 0 -200 200 200 0 P 2 6 0 0 200 0 -200 -200 P 2 6 0 0 -200 -200 -200 200 P 2 6 0 0 -30 -50 -70 50 P 2 6 0 0 -80 -50 -120 50 P 2 6 0 0 -80 -50 -30 -50 P 2 6 0 0 -30 -50 5 -50 P 2 6 0 0 -155 50 -120 50 P 2 6 0 0 -120 50 -70 50 X I 13 -400 0 200 R 40 40 6 1 I X O 12 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 14 0 300 200 D 40 40 7 1 W X VSS 7 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 40106N # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 7 # DEF 40106N IC 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: 40106 F0 "IC" 100 125 50 H V L B F1 "40106N" 100 -200 50 H V L B F2 "40xx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -200 200 200 0 P 2 1 0 0 200 0 -200 -200 P 2 1 0 0 -200 -200 -200 200 P 2 1 0 0 -30 -50 -70 50 P 2 1 0 0 -80 -50 -120 50 P 2 1 0 0 -80 -50 -30 -50 P 2 1 0 0 -30 -50 5 -50 P 2 1 0 0 -155 50 -120 50 P 2 1 0 0 -120 50 -70 50 X I 1 -400 0 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O I # Gate Name: B # Symbol Name: 40106 P 2 2 0 0 -200 200 200 0 P 2 2 0 0 200 0 -200 -200 P 2 2 0 0 -200 -200 -200 200 P 2 2 0 0 -30 -50 -70 50 P 2 2 0 0 -80 -50 -120 50 P 2 2 0 0 -80 -50 -30 -50 P 2 2 0 0 -30 -50 5 -50 P 2 2 0 0 -155 50 -120 50 P 2 2 0 0 -120 50 -70 50 X I 3 -400 0 200 R 40 40 2 1 I X O 4 400 0 200 L 40 40 2 1 O I # Gate Name: C # Symbol Name: 40106 P 2 3 0 0 -200 200 200 0 P 2 3 0 0 200 0 -200 -200 P 2 3 0 0 -200 -200 -200 200 P 2 3 0 0 -30 -50 -70 50 P 2 3 0 0 -80 -50 -120 50 P 2 3 0 0 -80 -50 -30 -50 P 2 3 0 0 -30 -50 5 -50 P 2 3 0 0 -155 50 -120 50 P 2 3 0 0 -120 50 -70 50 X I 5 -400 0 200 R 40 40 3 1 I X O 6 400 0 200 L 40 40 3 1 O I # Gate Name: D # Symbol Name: 40106 P 2 4 0 0 -200 200 200 0 P 2 4 0 0 200 0 -200 -200 P 2 4 0 0 -200 -200 -200 200 P 2 4 0 0 -30 -50 -70 50 P 2 4 0 0 -80 -50 -120 50 P 2 4 0 0 -80 -50 -30 -50 P 2 4 0 0 -30 -50 5 -50 P 2 4 0 0 -155 50 -120 50 P 2 4 0 0 -120 50 -70 50 X I 9 -400 0 200 R 40 40 4 1 I X O 8 400 0 200 L 40 40 4 1 O I # Gate Name: E # Symbol Name: 40106 P 2 5 0 0 -200 200 200 0 P 2 5 0 0 200 0 -200 -200 P 2 5 0 0 -200 -200 -200 200 P 2 5 0 0 -30 -50 -70 50 P 2 5 0 0 -80 -50 -120 50 P 2 5 0 0 -80 -50 -30 -50 P 2 5 0 0 -30 -50 5 -50 P 2 5 0 0 -155 50 -120 50 P 2 5 0 0 -120 50 -70 50 X I 11 -400 0 200 R 40 40 5 1 I X O 10 400 0 200 L 40 40 5 1 O I # Gate Name: F # Symbol Name: 40106 P 2 6 0 0 -200 200 200 0 P 2 6 0 0 200 0 -200 -200 P 2 6 0 0 -200 -200 -200 200 P 2 6 0 0 -30 -50 -70 50 P 2 6 0 0 -80 -50 -120 50 P 2 6 0 0 -80 -50 -30 -50 P 2 6 0 0 -30 -50 5 -50 P 2 6 0 0 -155 50 -120 50 P 2 6 0 0 -120 50 -70 50 X I 13 -400 0 200 R 40 40 6 1 I X O 12 400 0 200 L 40 40 6 1 O I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 7 0 VDD T 1 50 -155 50 0 7 0 VSS X VDD 14 0 300 200 D 40 40 7 1 W X VSS 7 0 -300 200 U 40 40 7 1 W ENDDRAW ENDDEF # # Dev Name: 40193D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 40193D IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 40193 F0 "IC" -400 525 50 H V L B F1 "40193D" -400 -700 50 H V L B F2 "40xx-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -600 400 -600 P 2 1 0 0 400 -600 400 500 P 2 1 0 0 400 500 -400 500 P 2 1 0 0 -400 500 -400 -600 X A 15 -600 400 200 R 40 40 1 1 I X B 1 -600 300 200 R 40 40 1 1 I X BORROW 13 600 -200 200 L 40 40 1 1 O I X C 10 -600 200 200 R 40 40 1 1 I X CARRY 12 600 -300 200 L 40 40 1 1 O I X CLEAR 14 -600 -500 200 R 40 40 1 1 I X D 9 -600 100 200 R 40 40 1 1 I X DOWN 4 -600 -400 200 R 40 40 1 1 I X LOAD 11 -600 -100 200 R 40 40 1 1 I I X QA 3 600 400 200 L 40 40 1 1 O X QB 2 600 300 200 L 40 40 1 1 O X QC 6 600 200 200 L 40 40 1 1 O X QD 7 600 100 200 L 40 40 1 1 O X UP 5 -600 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 40193N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF 40193N IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 40193 F0 "IC" -400 525 50 H V L B F1 "40193N" -400 -700 50 H V L B F2 "40xx-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -600 400 -600 P 2 1 0 0 400 -600 400 500 P 2 1 0 0 400 500 -400 500 P 2 1 0 0 -400 500 -400 -600 X A 15 -600 400 200 R 40 40 1 1 I X B 1 -600 300 200 R 40 40 1 1 I X BORROW 13 600 -200 200 L 40 40 1 1 O I X C 10 -600 200 200 R 40 40 1 1 I X CARRY 12 600 -300 200 L 40 40 1 1 O I X CLEAR 14 -600 -500 200 R 40 40 1 1 I X D 9 -600 100 200 R 40 40 1 1 I X DOWN 4 -600 -400 200 R 40 40 1 1 I X LOAD 11 -600 -100 200 R 40 40 1 1 I I X QA 3 600 400 200 L 40 40 1 1 O X QB 2 600 300 200 L 40 40 1 1 O X QC 6 600 200 200 L 40 40 1 1 O X QD 7 600 100 200 L 40 40 1 1 O X UP 5 -600 -300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 175 50 0 2 0 VDD T 1 50 -155 50 0 2 0 VSS X VDD 16 0 300 200 D 40 40 2 1 W X VSS 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF #End Library