EESchema-LIBRARY Version 2.3  29/04/2008-12:21:09
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 14
#
# Dev Name: A3967SLB
# Package Name: SO24W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF A3967SLB IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: A3967
F0 "IC" -600 1150 50 H V L B
F1 "A3967SLB" -600 -1300 50 H V L B
F2 "allegro-SO24W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 1100 600 1100
P 2 1 0 0 600 1100 600 -1200
P 2 1 0 0 600 -1200 -600 -1200
P 2 1 0 0 -600 -1200 -600 1100
X DIR 11 -700 400 100 R 40 40 1 1 I 
X GND@1 6 -700 -800 100 R 40 40 1 1 W 
X GND@2 7 -700 -900 100 R 40 40 1 1 W 
X GND@3 18 -700 -1000 100 R 40 40 1 1 W 
X GND@4 19 -700 -1100 100 R 40 40 1 1 W 
X LOAD-SUPPLY1 20 700 900 100 L 40 40 1 1 I 
X LOAD-SUPPLY2 5 700 -200 100 L 40 40 1 1 I 
X MS1 12 -700 300 100 R 40 40 1 1 I 
X MS2 13 -700 200 100 R 40 40 1 1 I 
X OUT1A 16 700 600 100 L 40 40 1 1 O 
X OUT1B 21 700 400 100 L 40 40 1 1 O 
X OUT2A 9 700 -500 100 L 40 40 1 1 O 
X OUT2B 4 700 -700 100 L 40 40 1 1 O 
X PFD 24 -700 -300 100 R 40 40 1 1 I 
X RC1 23 -700 -500 100 R 40 40 1 1 I 
X RC2 2 -700 -600 100 R 40 40 1 1 I 
X REF 1 -700 800 100 R 40 40 1 1 I 
X SENSE1 17 700 100 100 L 40 40 1 1 I 
X SENSE2 8 700 -1000 100 L 40 40 1 1 I 
X STEP 10 -700 500 100 R 40 40 1 1 I 
X VCC 14 -700 1000 100 R 40 40 1 1 W 
X \ENABLE 15 -700 -100 100 R 40 40 1 1 I 
X \RESET 22 -700 600 100 R 40 40 1 1 I 
X \SLEEP 3 -700 0 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: A3977
# Package Name: PLCC44
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF A3977 IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: A3977
F0 "IC" -600 1550 50 H V L B
F1 "A3977" -600 -1500 50 H V L B
F2 "allegro-PLCC44" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 1500 600 1500
P 2 1 0 0 600 1500 600 -1400
P 2 1 0 0 600 -1400 -600 -1400
P 2 1 0 0 -600 -1400 -600 1500
X CP1 37 700 1400 100 L 40 40 1 1 I 
X CP2 38 700 1300 100 L 40 40 1 1 I 
X DIR 5 -700 800 100 R 40 40 1 1 I 
X GND@1 1 -700 -200 100 R 40 40 1 1 W 
X GND@2 2 -700 -300 100 R 40 40 1 1 W 
X GND@3 44 -700 -400 100 R 40 40 1 1 W 
X GND@4 11 -700 -500 100 R 40 40 1 1 W 
X GND@5 12 -700 -600 100 R 40 40 1 1 W 
X GND@6 13 -700 -700 100 R 40 40 1 1 W 
X GND@7 22 -700 -800 100 R 40 40 1 1 W 
X GND@8 23 -700 -900 100 R 40 40 1 1 W 
X GND@9 24 -700 -1000 100 R 40 40 1 1 W 
X GND@10 33 -700 -1100 100 R 40 40 1 1 W 
X GND@11 34 -700 -1200 100 R 40 40 1 1 W 
X GND@12 35 -700 -1300 100 R 40 40 1 1 W 
X HOME 4 -700 500 100 R 40 40 1 1 I 
X LOAD-SUPPLY1 43 700 600 100 L 40 40 1 1 I 
X LOAD-SUPPLY2 25 700 -300 100 L 40 40 1 1 I 
X MS1 20 -700 700 100 R 40 40 1 1 I 
X MS2 19 -700 600 100 R 40 40 1 1 I 
X OUT1A 6 700 400 100 L 40 40 1 1 O 
X OUT1B 40 700 300 100 L 40 40 1 1 O 
X OUT2A 18 700 -500 100 L 40 40 1 1 O 
X OUT2B 28 700 -600 100 L 40 40 1 1 O 
X PFD 9 -700 0 100 R 40 40 1 1 I 
X RC1 10 700 -1100 100 L 40 40 1 1 I 
X RC2 15 700 -1300 100 L 40 40 1 1 I 
X REF 14 -700 1200 100 R 40 40 1 1 I 
X SENSE1 3 700 100 100 L 40 40 1 1 I 
X SENSE2 21 700 -800 100 L 40 40 1 1 I 
X SR 26 -700 200 100 R 40 40 1 1 I 
X STEP 31 -700 900 100 R 40 40 1 1 I 
X VCC 16 -700 1400 100 R 40 40 1 1 W 
X VCP 36 700 900 100 L 40 40 1 1 I 
X VREG 32 700 1000 100 L 40 40 1 1 I 
X \ENABLE 41 -700 300 100 R 40 40 1 1 I 
X \RESET 27 -700 1000 100 R 40 40 1 1 I 
X \SLEEP 42 -700 400 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ACS750LCA-050
# Package Name: ACS75050
# Dev Tech: L
# Dev Prefix: IC
# Gate count = 1
#
DEF ACS750LCA-050 IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ACS750XCA-050
F0 "IC" -100 350 50 H V L B
F1 "ACS750LCA-050" -100 -400 50 H V L B
F2 "allegro-ACS75050" 0 150 50 H I C C
DRAW
P 2 1 0 0 300 300 300 -300
P 2 1 0 0 300 -300 -300 -300
P 2 1 0 0 -300 -300 -300 300
P 2 1 0 0 -300 300 300 300
P 2 1 0 0 -200 175 -200 40
P 2 1 0 0 -200 12 -200 -175
A -200 -5 20 -3458 -141 1 1 0 N -180 0 -180 -10
A -199 -5 40 -3527 -72 1 1 0 N -160 0 -160 -10
P 2 1 0 0 -180 0 -160 0
P 2 1 0 0 -180 -10 -160 -10
T 0 -160 -230 60 0 1 0 IP-
T 0 -160 230 60 0 1 0 IP+
X GND 2 400 -200 100 L 40 40 1 1 W 
X IP+ 4 -200 500 200 D 40 40 1 1 P 
X IP+1 IP+1 -200 400 100 D 40 40 1 1 I 
X IP- 5 -200 -500 200 U 40 40 1 1 P 
X IP-1 IP-1 -200 -400 100 U 40 40 1 1 I 
X VCC 1 400 200 100 L 40 40 1 1 W 
X VOUT 3 400 0 100 L 40 40 1 1 O 
ENDDRAW
ENDDEF

#
# Dev Name: ACS750SCA-050
# Package Name: ACS75050
# Dev Tech: S
# Dev Prefix: IC
# Gate count = 1
#
DEF ACS750SCA-050 IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ACS750XCA-050
F0 "IC" -100 350 50 H V L B
F1 "ACS750SCA-050" -100 -400 50 H V L B
F2 "allegro-ACS75050" 0 150 50 H I C C
DRAW
P 2 1 0 0 300 300 300 -300
P 2 1 0 0 300 -300 -300 -300
P 2 1 0 0 -300 -300 -300 300
P 2 1 0 0 -300 300 300 300
P 2 1 0 0 -200 175 -200 40
P 2 1 0 0 -200 12 -200 -175
A -200 -5 20 -3458 -141 1 1 0 N -180 0 -180 -10
A -199 -5 40 -3527 -72 1 1 0 N -160 0 -160 -10
P 2 1 0 0 -180 0 -160 0
P 2 1 0 0 -180 -10 -160 -10
T 0 -160 -230 60 0 1 0 IP-
T 0 -160 230 60 0 1 0 IP+
X GND 2 400 -200 100 L 40 40 1 1 W 
X IP+ 4 -200 500 200 D 40 40 1 1 P 
X IP+1 IP+1 -200 400 100 D 40 40 1 1 I 
X IP- 5 -200 -500 200 U 40 40 1 1 P 
X IP-1 IP-1 -200 -400 100 U 40 40 1 1 I 
X VCC 1 400 200 100 L 40 40 1 1 W 
X VOUT 3 400 0 100 L 40 40 1 1 O 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7052M
# Package Name: SLA7052MLF872
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7052M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7052
F0 "IC" -500 750 50 H V L B
F1 "SLA7052M" -500 -800 50 H V L B
F2 "allegro-SLA7052MLF872" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 700 500 700
P 2 1 0 0 500 700 500 -700
P 2 1 0 0 500 -700 -500 -700
P 2 1 0 0 -500 -700 -500 700
X CLOCK 7 -600 100 100 R 40 40 1 1 W 
X DIRECTION 11 -600 0 100 R 40 40 1 1 W 
X FULL/HALF 12 -600 -200 100 R 40 40 1 1 W 
X GATEA 4 600 600 100 L 40 40 1 1 P 
X GATEB 15 600 -200 100 L 40 40 1 1 P 
X GND 10 -600 -600 100 R 40 40 1 1 W 
X OUTA 1 600 500 100 L 40 40 1 1 O 
X OUTB 18 600 -300 100 L 40 40 1 1 O 
X OUT\A 3 600 300 100 L 40 40 1 1 O 
X OUT\B 16 600 -500 100 L 40 40 1 1 O 
X REF 9 -600 -400 100 R 40 40 1 1 W 
X SENSEA 6 600 200 100 L 40 40 1 1 P 
X SENSEB 13 600 -600 100 L 40 40 1 1 P 
X SYNC 8 -600 -100 100 R 40 40 1 1 W 
X VBB 14 -600 600 100 R 40 40 1 1 W 
X VDD 5 -600 400 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7060M
# Package Name: ZIP21-SLA
# Dev Tech: 0
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7060M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7060M
F0 "IC" -600 950 50 H V L B
F1 "SLA7060M" -600 -1000 50 H V L B
F2 "allegro-ZIP21-SLA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 900 600 900
P 2 1 0 0 600 900 600 -900
P 2 1 0 0 600 -900 -600 -900
P 2 1 0 0 -600 -900 -600 900
X CLOCK 10 -700 -100 100 R 40 40 1 1 I 
X DIRECTION 9 -700 0 100 R 40 40 1 1 I 
X GND 11 -700 -800 100 R 40 40 1 1 W 
X M0 14 -700 -200 100 R 40 40 1 1 I 
X M1 13 -700 -300 100 R 40 40 1 1 I 
X M2 12 -700 -400 100 R 40 40 1 1 I 
X OUTA@1 1 700 800 100 L 40 40 1 1 O 
X OUTA@2 2 700 700 100 L 40 40 1 1 P 
X OUTB@1 21 700 -200 100 L 40 40 1 1 O 
X OUTB@2 20 700 -300 100 L 40 40 1 1 P 
X OUT\A@1 3 700 500 100 L 40 40 1 1 O 
X OUT\A@2 4 700 400 100 L 40 40 1 1 P 
X OUT\B@1 19 700 -500 100 L 40 40 1 1 O 
X OUT\B@2 18 700 -600 100 L 40 40 1 1 P 
X REFERENCE 7 -700 300 100 R 40 40 1 1 I 
X RESET 8 -700 100 100 R 40 40 1 1 I 
X SENSEA 5 700 200 100 L 40 40 1 1 I 
X SENSEB 17 700 -800 100 L 40 40 1 1 I 
X SYNC 15 -700 -500 100 R 40 40 1 1 I 
X VBB 16 -700 800 100 R 40 40 1 1 W 
X VDD 6 -700 600 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7061M
# Package Name: ZIP21-SLA
# Dev Tech: 1
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7061M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7060M
F0 "IC" -600 950 50 H V L B
F1 "SLA7061M" -600 -1000 50 H V L B
F2 "allegro-ZIP21-SLA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 900 600 900
P 2 1 0 0 600 900 600 -900
P 2 1 0 0 600 -900 -600 -900
P 2 1 0 0 -600 -900 -600 900
X CLOCK 10 -700 -100 100 R 40 40 1 1 I 
X DIRECTION 9 -700 0 100 R 40 40 1 1 I 
X GND 11 -700 -800 100 R 40 40 1 1 W 
X M0 14 -700 -200 100 R 40 40 1 1 I 
X M1 13 -700 -300 100 R 40 40 1 1 I 
X M2 12 -700 -400 100 R 40 40 1 1 I 
X OUTA@1 1 700 800 100 L 40 40 1 1 O 
X OUTA@2 2 700 700 100 L 40 40 1 1 P 
X OUTB@1 21 700 -200 100 L 40 40 1 1 O 
X OUTB@2 20 700 -300 100 L 40 40 1 1 P 
X OUT\A@1 3 700 500 100 L 40 40 1 1 O 
X OUT\A@2 4 700 400 100 L 40 40 1 1 P 
X OUT\B@1 19 700 -500 100 L 40 40 1 1 O 
X OUT\B@2 18 700 -600 100 L 40 40 1 1 P 
X REFERENCE 7 -700 300 100 R 40 40 1 1 I 
X RESET 8 -700 100 100 R 40 40 1 1 I 
X SENSEA 5 700 200 100 L 40 40 1 1 I 
X SENSEB 17 700 -800 100 L 40 40 1 1 I 
X SYNC 15 -700 -500 100 R 40 40 1 1 I 
X VBB 16 -700 800 100 R 40 40 1 1 W 
X VDD 6 -700 600 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7062M
# Package Name: ZIP21-SLA
# Dev Tech: 2
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7062M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7060M
F0 "IC" -600 950 50 H V L B
F1 "SLA7062M" -600 -1000 50 H V L B
F2 "allegro-ZIP21-SLA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 900 600 900
P 2 1 0 0 600 900 600 -900
P 2 1 0 0 600 -900 -600 -900
P 2 1 0 0 -600 -900 -600 900
X CLOCK 10 -700 -100 100 R 40 40 1 1 I 
X DIRECTION 9 -700 0 100 R 40 40 1 1 I 
X GND 11 -700 -800 100 R 40 40 1 1 W 
X M0 14 -700 -200 100 R 40 40 1 1 I 
X M1 13 -700 -300 100 R 40 40 1 1 I 
X M2 12 -700 -400 100 R 40 40 1 1 I 
X OUTA@1 1 700 800 100 L 40 40 1 1 O 
X OUTA@2 2 700 700 100 L 40 40 1 1 P 
X OUTB@1 21 700 -200 100 L 40 40 1 1 O 
X OUTB@2 20 700 -300 100 L 40 40 1 1 P 
X OUT\A@1 3 700 500 100 L 40 40 1 1 O 
X OUT\A@2 4 700 400 100 L 40 40 1 1 P 
X OUT\B@1 19 700 -500 100 L 40 40 1 1 O 
X OUT\B@2 18 700 -600 100 L 40 40 1 1 P 
X REFERENCE 7 -700 300 100 R 40 40 1 1 I 
X RESET 8 -700 100 100 R 40 40 1 1 I 
X SENSEA 5 700 200 100 L 40 40 1 1 I 
X SENSEB 17 700 -800 100 L 40 40 1 1 I 
X SYNC 15 -700 -500 100 R 40 40 1 1 I 
X VBB 16 -700 800 100 R 40 40 1 1 W 
X VDD 6 -700 600 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7070M
# Package Name: ZIP23-SLA
# Dev Tech: 0
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7070M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7070M
F0 "IC" -600 850 50 H V L B
F1 "SLA7070M" -600 -1000 50 H V L B
F2 "allegro-ZIP23-SLA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 800 500 800
P 2 1 0 0 500 800 500 -900
P 2 1 0 0 500 -900 -600 -900
P 2 1 0 0 -600 -900 -600 800
X CLOCK 10 -700 300 100 R 40 40 1 1 I 
X FLAG 18 -700 -300 100 R 40 40 1 1 I 
X F\R 16 -700 200 100 R 40 40 1 1 I 
X GND 12 -700 -800 100 R 40 40 1 1 W 
X M1 7 -700 100 100 R 40 40 1 1 I 
X M2 8 -700 0 100 R 40 40 1 1 I 
X M3 9 -700 -100 100 R 40 40 1 1 I 
X NC 6 -100 -900 0 R 40 40 1 1 U 
X OUTA@1 1 600 700 100 L 40 40 1 1 O 
X OUTA@2 2 600 600 100 L 40 40 1 1 O 
X OUTB@1 23 600 -200 100 L 40 40 1 1 O 
X OUTB@2 22 600 -300 100 L 40 40 1 1 O 
X REF/SLEEP1 13 -700 -400 100 R 40 40 1 1 W 
X RESET 15 -700 400 100 R 40 40 1 1 I 
X SENSEA 5 600 100 100 L 40 40 1 1 I 
X SENSEB 19 600 -800 100 L 40 40 1 1 I 
X SYNC 17 -700 -600 100 R 40 40 1 1 I 
X VBB 11 -700 600 100 R 40 40 1 1 W 
X VDD 14 -700 700 100 R 40 40 1 1 W 
X \OUTA@1 3 600 400 100 L 40 40 1 1 O 
X \OUTA@2 4 600 300 100 L 40 40 1 1 O 
X \OUTB@1 21 600 -500 100 L 40 40 1 1 O 
X \OUTB@2 20 600 -600 100 L 40 40 1 1 O 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7071M
# Package Name: ZIP23-SLA
# Dev Tech: 1
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7071M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7070M
F0 "IC" -600 850 50 H V L B
F1 "SLA7071M" -600 -1000 50 H V L B
F2 "allegro-ZIP23-SLA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 800 500 800
P 2 1 0 0 500 800 500 -900
P 2 1 0 0 500 -900 -600 -900
P 2 1 0 0 -600 -900 -600 800
X CLOCK 10 -700 300 100 R 40 40 1 1 I 
X FLAG 18 -700 -300 100 R 40 40 1 1 I 
X F\R 16 -700 200 100 R 40 40 1 1 I 
X GND 12 -700 -800 100 R 40 40 1 1 W 
X M1 7 -700 100 100 R 40 40 1 1 I 
X M2 8 -700 0 100 R 40 40 1 1 I 
X M3 9 -700 -100 100 R 40 40 1 1 I 
X NC 6 -100 -900 0 R 40 40 1 1 U 
X OUTA@1 1 600 700 100 L 40 40 1 1 O 
X OUTA@2 2 600 600 100 L 40 40 1 1 O 
X OUTB@1 23 600 -200 100 L 40 40 1 1 O 
X OUTB@2 22 600 -300 100 L 40 40 1 1 O 
X REF/SLEEP1 13 -700 -400 100 R 40 40 1 1 W 
X RESET 15 -700 400 100 R 40 40 1 1 I 
X SENSEA 5 600 100 100 L 40 40 1 1 I 
X SENSEB 19 600 -800 100 L 40 40 1 1 I 
X SYNC 17 -700 -600 100 R 40 40 1 1 I 
X VBB 11 -700 600 100 R 40 40 1 1 W 
X VDD 14 -700 700 100 R 40 40 1 1 W 
X \OUTA@1 3 600 400 100 L 40 40 1 1 O 
X \OUTA@2 4 600 300 100 L 40 40 1 1 O 
X \OUTB@1 21 600 -500 100 L 40 40 1 1 O 
X \OUTB@2 20 600 -600 100 L 40 40 1 1 O 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7072M
# Package Name: ZIP23-SLA
# Dev Tech: 2
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7072M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7070M
F0 "IC" -600 850 50 H V L B
F1 "SLA7072M" -600 -1000 50 H V L B
F2 "allegro-ZIP23-SLA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 800 500 800
P 2 1 0 0 500 800 500 -900
P 2 1 0 0 500 -900 -600 -900
P 2 1 0 0 -600 -900 -600 800
X CLOCK 10 -700 300 100 R 40 40 1 1 I 
X FLAG 18 -700 -300 100 R 40 40 1 1 I 
X F\R 16 -700 200 100 R 40 40 1 1 I 
X GND 12 -700 -800 100 R 40 40 1 1 W 
X M1 7 -700 100 100 R 40 40 1 1 I 
X M2 8 -700 0 100 R 40 40 1 1 I 
X M3 9 -700 -100 100 R 40 40 1 1 I 
X NC 6 -100 -900 0 R 40 40 1 1 U 
X OUTA@1 1 600 700 100 L 40 40 1 1 O 
X OUTA@2 2 600 600 100 L 40 40 1 1 O 
X OUTB@1 23 600 -200 100 L 40 40 1 1 O 
X OUTB@2 22 600 -300 100 L 40 40 1 1 O 
X REF/SLEEP1 13 -700 -400 100 R 40 40 1 1 W 
X RESET 15 -700 400 100 R 40 40 1 1 I 
X SENSEA 5 600 100 100 L 40 40 1 1 I 
X SENSEB 19 600 -800 100 L 40 40 1 1 I 
X SYNC 17 -700 -600 100 R 40 40 1 1 I 
X VBB 11 -700 600 100 R 40 40 1 1 W 
X VDD 14 -700 700 100 R 40 40 1 1 W 
X \OUTA@1 3 600 400 100 L 40 40 1 1 O 
X \OUTA@2 4 600 300 100 L 40 40 1 1 O 
X \OUTB@1 21 600 -500 100 L 40 40 1 1 O 
X \OUTB@2 20 600 -600 100 L 40 40 1 1 O 
ENDDRAW
ENDDEF

#
# Dev Name: SLA7073M
# Package Name: ZIP23-SLA
# Dev Tech: 3
# Dev Prefix: IC
# Gate count = 1
#
DEF SLA7073M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: SLA7070M
F0 "IC" -600 850 50 H V L B
F1 "SLA7073M" -600 -1000 50 H V L B
F2 "allegro-ZIP23-SLA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 800 500 800
P 2 1 0 0 500 800 500 -900
P 2 1 0 0 500 -900 -600 -900
P 2 1 0 0 -600 -900 -600 800
X CLOCK 10 -700 300 100 R 40 40 1 1 I 
X FLAG 18 -700 -300 100 R 40 40 1 1 I 
X F\R 16 -700 200 100 R 40 40 1 1 I 
X GND 12 -700 -800 100 R 40 40 1 1 W 
X M1 7 -700 100 100 R 40 40 1 1 I 
X M2 8 -700 0 100 R 40 40 1 1 I 
X M3 9 -700 -100 100 R 40 40 1 1 I 
X NC 6 -100 -900 0 R 40 40 1 1 U 
X OUTA@1 1 600 700 100 L 40 40 1 1 O 
X OUTA@2 2 600 600 100 L 40 40 1 1 O 
X OUTB@1 23 600 -200 100 L 40 40 1 1 O 
X OUTB@2 22 600 -300 100 L 40 40 1 1 O 
X REF/SLEEP1 13 -700 -400 100 R 40 40 1 1 W 
X RESET 15 -700 400 100 R 40 40 1 1 I 
X SENSEA 5 600 100 100 L 40 40 1 1 I 
X SENSEB 19 600 -800 100 L 40 40 1 1 I 
X SYNC 17 -700 -600 100 R 40 40 1 1 I 
X VBB 11 -700 600 100 R 40 40 1 1 W 
X VDD 14 -700 700 100 R 40 40 1 1 W 
X \OUTA@1 3 600 400 100 L 40 40 1 1 O 
X \OUTA@2 4 600 300 100 L 40 40 1 1 O 
X \OUTB@1 21 600 -500 100 L 40 40 1 1 O 
X \OUTB@2 20 600 -600 100 L 40 40 1 1 O 
ENDDRAW
ENDDEF

#
# Dev Name: UNC5804B
# Package Name: DIL16
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF UNC5804B IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: UNC5804
F0 "IC" -700 750 50 H V L B
F1 "UNC5804B" -700 -800 50 H V L B
F2 "allegro-DIL16" 0 150 50 H I C C
DRAW
P 2 1 0 0 -700 700 600 700
P 2 1 0 0 600 700 600 -700
P 2 1 0 0 600 -700 -700 -700
P 2 1 0 0 -700 -700 -700 700
X DIRECTION 14 -800 300 100 R 40 40 1 1 I 
X GND@1 4 -800 -300 100 R 40 40 1 1 W 
X GND@2 5 -800 -400 100 R 40 40 1 1 W 
X GND@3 12 -800 -500 100 R 40 40 1 1 W 
X GND@4 13 -800 -600 100 R 40 40 1 1 W 
X HALF-STEP 10 -800 100 100 R 40 40 1 1 I 
X KAC 7 700 400 100 L 40 40 1 1 P 
X KBD 2 700 -400 100 L 40 40 1 1 P 
X ONE-PHASE 9 -800 0 100 R 40 40 1 1 I 
X OUTPUTA 8 700 600 100 L 40 40 1 1 O 
X OUTPUTB 1 700 -200 100 L 40 40 1 1 O 
X OUTPUTC 6 700 200 100 L 40 40 1 1 O 
X OUTPUTD 3 700 -600 100 L 40 40 1 1 O 
X OUTPUT_ENABLE 15 -800 400 100 R 40 40 1 1 I 
X STEP 11 -800 200 100 R 40 40 1 1 I 
X VDD 16 -800 600 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: UNC5804LB
# Package Name: SO-16DW
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF UNC5804LB IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: UNC5804
F0 "IC" -700 750 50 H V L B
F1 "UNC5804LB" -700 -800 50 H V L B
F2 "allegro-SO-16DW" 0 150 50 H I C C
DRAW
P 2 1 0 0 -700 700 600 700
P 2 1 0 0 600 700 600 -700
P 2 1 0 0 600 -700 -700 -700
P 2 1 0 0 -700 -700 -700 700
X DIRECTION 14 -800 300 100 R 40 40 1 1 I 
X GND@1 4 -800 -300 100 R 40 40 1 1 W 
X GND@2 5 -800 -400 100 R 40 40 1 1 W 
X GND@3 12 -800 -500 100 R 40 40 1 1 W 
X GND@4 13 -800 -600 100 R 40 40 1 1 W 
X HALF-STEP 10 -800 100 100 R 40 40 1 1 I 
X KAC 7 700 400 100 L 40 40 1 1 P 
X KBD 2 700 -400 100 L 40 40 1 1 P 
X ONE-PHASE 9 -800 0 100 R 40 40 1 1 I 
X OUTPUTA 8 700 600 100 L 40 40 1 1 O 
X OUTPUTB 1 700 -200 100 L 40 40 1 1 O 
X OUTPUTC 6 700 200 100 L 40 40 1 1 O 
X OUTPUTD 3 700 -600 100 L 40 40 1 1 O 
X OUTPUT_ENABLE 15 -800 400 100 R 40 40 1 1 I 
X STEP 11 -800 200 100 R 40 40 1 1 I 
X VDD 16 -800 600 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#End Library