EESchema-LIBRARY Version 2.3  29/04/2008-12:21:24
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 6
#
# Dev Name: ATMEGA8-AU
# Package Name: TQFP32-08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATMEGA8-AU IC 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: ATMEGA8-TQFP/QFN32
F0 "IC" -1000 1300 50 H V L B
F1 "ATMEGA8-AU" -1000 -1400 50 H V L B
F2 "atmega8-TQFP32-08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1000 1200 1000 1200
P 2 1 0 0 1000 1200 1000 -1300
P 2 1 0 0 1000 -1300 -1000 -1300
P 2 1 0 0 -1000 -1300 -1000 1200
X ADC6 19 1200 500 200 L 40 40 1 1 P 
X ADC7 22 1200 400 200 L 40 40 1 1 P 
X AGND 21 -1200 -900 200 R 40 40 1 1 W 
X AREF 20 -1200 -400 200 R 40 40 1 1 P 
X AVCC 18 -1200 -300 200 R 40 40 1 1 P 
X GND@1 3 -1200 -1100 200 R 40 40 1 1 W 
X GND@2 5 -1200 -1200 200 R 40 40 1 1 W 
X PB0(ICP1) 12 1200 -700 200 L 40 40 1 1 B 
X PB1(OC1A) 13 1200 -800 200 L 40 40 1 1 B 
X PB2(SS/OC1B) 14 1200 -900 200 L 40 40 1 1 B 
X PB3(MOSI/OC2) 15 1200 -1000 200 L 40 40 1 1 B 
X PB4(MISO) 16 1200 -1100 200 L 40 40 1 1 B 
X PB5(SCK) 17 1200 -1200 200 L 40 40 1 1 B 
X PB6(XTAL1/TOSC1) 7 -1200 500 200 R 40 40 1 1 B 
X PB7(XTAL2/TOSC2) 8 -1200 300 200 R 40 40 1 1 B 
X PC0(ADC0) 23 1200 1100 200 L 40 40 1 1 B 
X PC1(ADC1) 24 1200 1000 200 L 40 40 1 1 B 
X PC2(ADC2) 25 1200 900 200 L 40 40 1 1 B 
X PC3(ADC3) 26 1200 800 200 L 40 40 1 1 B 
X PC4(ADC4/SDA) 27 1200 700 200 L 40 40 1 1 B 
X PC5(ADC5/SCL) 28 1200 600 200 L 40 40 1 1 B 
X PC6(/RESET) 29 -1200 1100 200 R 40 40 1 1 B 
X PD0(RXD) 30 1200 200 200 L 40 40 1 1 B 
X PD1(TXD) 31 1200 100 200 L 40 40 1 1 B 
X PD2(INT0) 32 1200 0 200 L 40 40 1 1 B 
X PD3(INT1) 1 1200 -100 200 L 40 40 1 1 B 
X PD4(T0/XCK) 2 1200 -200 200 L 40 40 1 1 B 
X PD5(T1) 9 1200 -300 200 L 40 40 1 1 B 
X PD6(AIN0) 10 1200 -400 200 L 40 40 1 1 B 
X PD7(AIN1) 11 1200 -500 200 L 40 40 1 1 B 
X VCC@1 4 -1200 0 200 R 40 40 1 1 W 
X VCC@2 6 -1200 -100 200 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATMEGA8-MU
# Package Name: MLF32
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATMEGA8-MU IC 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: ATMEGA8-TQFP/QFN32
F0 "IC" -1000 1300 50 H V L B
F1 "ATMEGA8-MU" -1000 -1400 50 H V L B
F2 "atmega8-MLF32" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1000 1200 1000 1200
P 2 1 0 0 1000 1200 1000 -1300
P 2 1 0 0 1000 -1300 -1000 -1300
P 2 1 0 0 -1000 -1300 -1000 1200
X ADC6 19 1200 500 200 L 40 40 1 1 P 
X ADC7 22 1200 400 200 L 40 40 1 1 P 
X AGND 21 -1200 -900 200 R 40 40 1 1 W 
X AREF 20 -1200 -400 200 R 40 40 1 1 P 
X AVCC 18 -1200 -300 200 R 40 40 1 1 P 
X GND@1 3 -1200 -1100 200 R 40 40 1 1 W 
X GND@2 5 -1200 -1200 200 R 40 40 1 1 W 
X PB0(ICP1) 12 1200 -700 200 L 40 40 1 1 B 
X PB1(OC1A) 13 1200 -800 200 L 40 40 1 1 B 
X PB2(SS/OC1B) 14 1200 -900 200 L 40 40 1 1 B 
X PB3(MOSI/OC2) 15 1200 -1000 200 L 40 40 1 1 B 
X PB4(MISO) 16 1200 -1100 200 L 40 40 1 1 B 
X PB5(SCK) 17 1200 -1200 200 L 40 40 1 1 B 
X PB6(XTAL1/TOSC1) 7 -1200 500 200 R 40 40 1 1 B 
X PB7(XTAL2/TOSC2) 8 -1200 300 200 R 40 40 1 1 B 
X PC0(ADC0) 23 1200 1100 200 L 40 40 1 1 B 
X PC1(ADC1) 24 1200 1000 200 L 40 40 1 1 B 
X PC2(ADC2) 25 1200 900 200 L 40 40 1 1 B 
X PC3(ADC3) 26 1200 800 200 L 40 40 1 1 B 
X PC4(ADC4/SDA) 27 1200 700 200 L 40 40 1 1 B 
X PC5(ADC5/SCL) 28 1200 600 200 L 40 40 1 1 B 
X PC6(/RESET) 29 -1200 1100 200 R 40 40 1 1 B 
X PD0(RXD) 30 1200 200 200 L 40 40 1 1 B 
X PD1(TXD) 31 1200 100 200 L 40 40 1 1 B 
X PD2(INT0) 32 1200 0 200 L 40 40 1 1 B 
X PD3(INT1) 1 1200 -100 200 L 40 40 1 1 B 
X PD4(T0/XCK) 2 1200 -200 200 L 40 40 1 1 B 
X PD5(T1) 9 1200 -300 200 L 40 40 1 1 B 
X PD6(AIN0) 10 1200 -400 200 L 40 40 1 1 B 
X PD7(AIN1) 11 1200 -500 200 L 40 40 1 1 B 
X VCC@1 4 -1200 0 200 R 40 40 1 1 W 
X VCC@2 6 -1200 -100 200 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATMEGA8-PU
# Package Name: DIL28-3
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATMEGA8-PU IC 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: ATMEGA8
F0 "IC" -1000 1300 50 H V L B
F1 "ATMEGA8-PU" -1000 -1400 50 H V L B
F2 "atmega8-DIL28-3" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1000 1200 1000 1200
P 2 1 0 0 1000 1200 1000 -1300
P 2 1 0 0 1000 -1300 -1000 -1300
P 2 1 0 0 -1000 -1300 -1000 1200
X AGND 22 -1200 -900 200 R 40 40 1 1 W 
X AREF 21 -1200 -400 200 R 40 40 1 1 P 
X AVCC 20 -1200 -300 200 R 40 40 1 1 P 
X GND@1 8 -1200 -1100 200 R 40 40 1 1 W 
X PB0(ICP1) 14 1200 -700 200 L 40 40 1 1 B 
X PB1(OC1A) 15 1200 -800 200 L 40 40 1 1 B 
X PB2(SS/OC1B) 16 1200 -900 200 L 40 40 1 1 B 
X PB3(MOSI/OC2) 17 1200 -1000 200 L 40 40 1 1 B 
X PB4(MISO) 18 1200 -1100 200 L 40 40 1 1 B 
X PB5(SCK) 19 1200 -1200 200 L 40 40 1 1 B 
X PB6(XTAL1/TOSC1) 9 -1200 500 200 R 40 40 1 1 B 
X PB7(XTAL2/TOSC2) 10 -1200 300 200 R 40 40 1 1 B 
X PC0(ADC0) 23 1200 1100 200 L 40 40 1 1 B 
X PC1(ADC1) 24 1200 1000 200 L 40 40 1 1 B 
X PC2(ADC2) 25 1200 900 200 L 40 40 1 1 B 
X PC3(ADC3) 26 1200 800 200 L 40 40 1 1 B 
X PC4(ADC4/SDA) 27 1200 700 200 L 40 40 1 1 B 
X PC5(ADC5/SCL) 28 1200 600 200 L 40 40 1 1 B 
X PC6(/RESET) 1 -1200 1100 200 R 40 40 1 1 B 
X PD0(RXD) 2 1200 200 200 L 40 40 1 1 B 
X PD1(TXD) 3 1200 100 200 L 40 40 1 1 B 
X PD2(INT0) 4 1200 0 200 L 40 40 1 1 B 
X PD3(INT1) 5 1200 -100 200 L 40 40 1 1 B 
X PD4(T0/XCK) 6 1200 -200 200 L 40 40 1 1 B 
X PD5(T1) 11 1200 -300 200 L 40 40 1 1 B 
X PD6(AIN0) 12 1200 -400 200 L 40 40 1 1 B 
X PD7(AIN1) 13 1200 -500 200 L 40 40 1 1 B 
X VCC@1 7 -1200 0 200 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATMEGA48/88/168-AU
# Package Name: TQFP32-08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATMEGA48/88/168-AU IC 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: ATMEGA48/88/168-TQFP/QFN32
F0 "IC" -1000 1300 50 H V L B
F1 "ATMEGA48/88/168-AU" -1000 -1400 50 H V L B
F2 "atmega8-TQFP32-08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1000 1200 1000 1200
P 2 1 0 0 1000 1200 1000 -1300
P 2 1 0 0 1000 -1300 -1000 -1300
P 2 1 0 0 -1000 -1300 -1000 1200
X ADC6 19 1200 500 200 L 40 40 1 1 P 
X ADC7 22 1200 400 200 L 40 40 1 1 P 
X AGND 21 -1200 -900 200 R 40 40 1 1 W 
X AREF 20 -1200 -400 200 R 40 40 1 1 P 
X AVCC 18 -1200 -300 200 R 40 40 1 1 P 
X GND@1 3 -1200 -1100 200 R 40 40 1 1 W 
X GND@2 5 -1200 -1200 200 R 40 40 1 1 W 
X PB0(ICP1/CLKO/PCINT0) 12 1200 -700 200 L 40 40 1 1 B 
X PB1(OC1A/PCINT1) 13 1200 -800 200 L 40 40 1 1 B 
X PB2(SS/OC1B/PCINT2) 14 1200 -900 200 L 40 40 1 1 B 
X PB3(MOSI/OC2A/PCINT3) 15 1200 -1000 200 L 40 40 1 1 B 
X PB4(MISO/PCINT4) 16 1200 -1100 200 L 40 40 1 1 B 
X PB5(SCK/PCINT5) 17 1200 -1200 200 L 40 40 1 1 B 
X PB6(XTAL1/TOSC1/PCINT6) 7 -1200 500 200 R 40 40 1 1 B 
X PB7(XTAL2/TOSC2/PCINT7) 8 -1200 300 200 R 40 40 1 1 B 
X PC0(ADC0/PCINT8) 23 1200 1100 200 L 40 40 1 1 B 
X PC1(ADC1/PCINT9) 24 1200 1000 200 L 40 40 1 1 B 
X PC2(ADC2/PCINT10) 25 1200 900 200 L 40 40 1 1 B 
X PC3(ADC3/PCINT11) 26 1200 800 200 L 40 40 1 1 B 
X PC4(ADC4/SDA/PCINT12) 27 1200 700 200 L 40 40 1 1 B 
X PC5(ADC5/SCL/PCINT13) 28 1200 600 200 L 40 40 1 1 B 
X PC6(/RESET/PCINT14) 29 -1200 1100 200 R 40 40 1 1 B 
X PD0(RXD/PCINT16) 30 1200 200 200 L 40 40 1 1 B 
X PD1(TXD/PCINT17) 31 1200 100 200 L 40 40 1 1 B 
X PD2(INT0/PCINT18) 32 1200 0 200 L 40 40 1 1 B 
X PD3(INT1/OC2B/PCINT19) 1 1200 -100 200 L 40 40 1 1 B 
X PD4(T0/XCK/PCINT20) 2 1200 -200 200 L 40 40 1 1 B 
X PD5(T1/OC0B/PCINT21) 9 1200 -300 200 L 40 40 1 1 B 
X PD6(AIN0/OC0A/PCINT22) 10 1200 -400 200 L 40 40 1 1 B 
X PD7(AIN1/PCINT23) 11 1200 -500 200 L 40 40 1 1 B 
X VCC@1 4 -1200 0 200 R 40 40 1 1 W 
X VCC@2 6 -1200 -100 200 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATMEGA48/88/168-MU
# Package Name: MLF32
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATMEGA48/88/168-MU IC 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: ATMEGA48/88/168-TQFP/QFN32
F0 "IC" -1000 1300 50 H V L B
F1 "ATMEGA48/88/168-MU" -1000 -1400 50 H V L B
F2 "atmega8-MLF32" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1000 1200 1000 1200
P 2 1 0 0 1000 1200 1000 -1300
P 2 1 0 0 1000 -1300 -1000 -1300
P 2 1 0 0 -1000 -1300 -1000 1200
X ADC6 19 1200 500 200 L 40 40 1 1 P 
X ADC7 22 1200 400 200 L 40 40 1 1 P 
X AGND 21 -1200 -900 200 R 40 40 1 1 W 
X AREF 20 -1200 -400 200 R 40 40 1 1 P 
X AVCC 18 -1200 -300 200 R 40 40 1 1 P 
X GND@1 3 -1200 -1100 200 R 40 40 1 1 W 
X GND@2 5 -1200 -1200 200 R 40 40 1 1 W 
X PB0(ICP1/CLKO/PCINT0) 12 1200 -700 200 L 40 40 1 1 B 
X PB1(OC1A/PCINT1) 13 1200 -800 200 L 40 40 1 1 B 
X PB2(SS/OC1B/PCINT2) 14 1200 -900 200 L 40 40 1 1 B 
X PB3(MOSI/OC2A/PCINT3) 15 1200 -1000 200 L 40 40 1 1 B 
X PB4(MISO/PCINT4) 16 1200 -1100 200 L 40 40 1 1 B 
X PB5(SCK/PCINT5) 17 1200 -1200 200 L 40 40 1 1 B 
X PB6(XTAL1/TOSC1/PCINT6) 7 -1200 500 200 R 40 40 1 1 B 
X PB7(XTAL2/TOSC2/PCINT7) 8 -1200 300 200 R 40 40 1 1 B 
X PC0(ADC0/PCINT8) 23 1200 1100 200 L 40 40 1 1 B 
X PC1(ADC1/PCINT9) 24 1200 1000 200 L 40 40 1 1 B 
X PC2(ADC2/PCINT10) 25 1200 900 200 L 40 40 1 1 B 
X PC3(ADC3/PCINT11) 26 1200 800 200 L 40 40 1 1 B 
X PC4(ADC4/SDA/PCINT12) 27 1200 700 200 L 40 40 1 1 B 
X PC5(ADC5/SCL/PCINT13) 28 1200 600 200 L 40 40 1 1 B 
X PC6(/RESET/PCINT14) 29 -1200 1100 200 R 40 40 1 1 B 
X PD0(RXD/PCINT16) 30 1200 200 200 L 40 40 1 1 B 
X PD1(TXD/PCINT17) 31 1200 100 200 L 40 40 1 1 B 
X PD2(INT0/PCINT18) 32 1200 0 200 L 40 40 1 1 B 
X PD3(INT1/OC2B/PCINT19) 1 1200 -100 200 L 40 40 1 1 B 
X PD4(T0/XCK/PCINT20) 2 1200 -200 200 L 40 40 1 1 B 
X PD5(T1/OC0B/PCINT21) 9 1200 -300 200 L 40 40 1 1 B 
X PD6(AIN0/OC0A/PCINT22) 10 1200 -400 200 L 40 40 1 1 B 
X PD7(AIN1/PCINT23) 11 1200 -500 200 L 40 40 1 1 B 
X VCC@1 4 -1200 0 200 R 40 40 1 1 W 
X VCC@2 6 -1200 -100 200 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATMEGA48/88/168-PU
# Package Name: DIL28-3
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATMEGA48/88/168-PU IC 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: ATMEGA48/88/168
F0 "IC" -1000 1300 50 H V L B
F1 "ATMEGA48/88/168-PU" -1000 -1400 50 H V L B
F2 "atmega8-DIL28-3" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1000 1200 1000 1200
P 2 1 0 0 1000 1200 1000 -1300
P 2 1 0 0 1000 -1300 -1000 -1300
P 2 1 0 0 -1000 -1300 -1000 1200
X AGND 22 -1200 -900 200 R 40 40 1 1 W 
X AREF 21 -1200 -400 200 R 40 40 1 1 P 
X AVCC 20 -1200 -300 200 R 40 40 1 1 P 
X GND@1 8 -1200 -1100 200 R 40 40 1 1 W 
X PB0(ICP1/CLKO/PCINT0) 14 1200 -700 200 L 40 40 1 1 B 
X PB1(OC1A/PCINT1) 15 1200 -800 200 L 40 40 1 1 B 
X PB2(SS/OC1B/PCINT2) 16 1200 -900 200 L 40 40 1 1 B 
X PB3(MOSI/OC2A/PCINT3) 17 1200 -1000 200 L 40 40 1 1 B 
X PB4(MISO/PCINT4) 18 1200 -1100 200 L 40 40 1 1 B 
X PB5(SCK/PCINT5) 19 1200 -1200 200 L 40 40 1 1 B 
X PB6(XTAL1/TOSC1/PCINT6) 9 -1200 500 200 R 40 40 1 1 B 
X PB7(XTAL2/TOSC2/PCINT7) 10 -1200 300 200 R 40 40 1 1 B 
X PC0(ADC0/PCINT8) 23 1200 1100 200 L 40 40 1 1 B 
X PC1(ADC1/PCINT9) 24 1200 1000 200 L 40 40 1 1 B 
X PC2(ADC2/PCINT10) 25 1200 900 200 L 40 40 1 1 B 
X PC3(ADC3/PCINT11) 26 1200 800 200 L 40 40 1 1 B 
X PC4(ADC4/SDA/PCINT12) 27 1200 700 200 L 40 40 1 1 B 
X PC5(ADC5/SCLPCINT13) 28 1200 600 200 L 40 40 1 1 B 
X PC6(/RESET/PCINT14) 1 -1200 1100 200 R 40 40 1 1 B 
X PD0(RXD/PCINT16) 2 1200 200 200 L 40 40 1 1 B 
X PD1(TXD/PCINT17) 3 1200 100 200 L 40 40 1 1 B 
X PD2(INT0/PCINT18) 4 1200 0 200 L 40 40 1 1 B 
X PD3(INT1/OC2B/PCINT19) 5 1200 -100 200 L 40 40 1 1 B 
X PD4(T0/XCK/PCINT20) 6 1200 -200 200 L 40 40 1 1 B 
X PD5(T1/OC0B/PCINT21) 11 1200 -300 200 L 40 40 1 1 B 
X PD6(AIN0/OC0A/PCINT22) 12 1200 -400 200 L 40 40 1 1 B 
X PD7(AIN1/PCINT23) 13 1200 -500 200 L 40 40 1 1 B 
X VCC@1 7 -1200 0 200 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#End Library