EESchema-LIBRARY Version 2.3  29/04/2008-12:21:27
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 4
#
# Dev Name: ATTINY13-20PU
# Package Name: DIL08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATTINY13-20PU IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ATTINY13
F0 "IC" -420 430 50 H V L B
F1 "ATTINY13-20PU" -500 -600 50 H V L B
F2 "attiny13-DIL08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -300 400 300 400
P 2 1 0 0 300 400 300 -500
P 2 1 0 0 300 -500 -300 -500
P 2 1 0 0 -300 -500 -300 400
X GND 4 -400 -400 100 R 40 40 1 1 W 
X MISO/PB1 6 400 100 100 L 40 40 1 1 B 
X MOSI/PB0 5 400 200 100 L 40 40 1 1 B 
X PB3 2 400 -100 100 L 40 40 1 1 B 
X PB4 3 400 -200 100 L 40 40 1 1 B 
X RST/PB5 1 400 -300 100 L 40 40 1 1 B 
X SCK/PB2 7 400 0 100 L 40 40 1 1 B 
X VCC 8 -400 300 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATTINY13-20SU
# Package Name: SOIC8
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATTINY13-20SU IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ATTINY13
F0 "IC" -420 430 50 H V L B
F1 "ATTINY13-20SU" -500 -600 50 H V L B
F2 "attiny13-SOIC8" 0 150 50 H I C C
DRAW
P 2 1 0 0 -300 400 300 400
P 2 1 0 0 300 400 300 -500
P 2 1 0 0 300 -500 -300 -500
P 2 1 0 0 -300 -500 -300 400
X GND 4 -400 -400 100 R 40 40 1 1 W 
X MISO/PB1 6 400 100 100 L 40 40 1 1 B 
X MOSI/PB0 5 400 200 100 L 40 40 1 1 B 
X PB3 2 400 -100 100 L 40 40 1 1 B 
X PB4 3 400 -200 100 L 40 40 1 1 B 
X RST/PB5 1 400 -300 100 L 40 40 1 1 B 
X SCK/PB2 7 400 0 100 L 40 40 1 1 B 
X VCC 8 -400 300 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATTINY13V-10PU
# Package Name: DIL08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATTINY13V-10PU IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ATTINY13
F0 "IC" -420 430 50 H V L B
F1 "ATTINY13V-10PU" -500 -600 50 H V L B
F2 "attiny13-DIL08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -300 400 300 400
P 2 1 0 0 300 400 300 -500
P 2 1 0 0 300 -500 -300 -500
P 2 1 0 0 -300 -500 -300 400
X GND 4 -400 -400 100 R 40 40 1 1 W 
X MISO/PB1 6 400 100 100 L 40 40 1 1 B 
X MOSI/PB0 5 400 200 100 L 40 40 1 1 B 
X PB3 2 400 -100 100 L 40 40 1 1 B 
X PB4 3 400 -200 100 L 40 40 1 1 B 
X RST/PB5 1 400 -300 100 L 40 40 1 1 B 
X SCK/PB2 7 400 0 100 L 40 40 1 1 B 
X VCC 8 -400 300 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ATTINY13V-10SU
# Package Name: SOIC8
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ATTINY13V-10SU IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ATTINY13
F0 "IC" -420 430 50 H V L B
F1 "ATTINY13V-10SU" -500 -600 50 H V L B
F2 "attiny13-SOIC8" 0 150 50 H I C C
DRAW
P 2 1 0 0 -300 400 300 400
P 2 1 0 0 300 400 300 -500
P 2 1 0 0 300 -500 -300 -500
P 2 1 0 0 -300 -500 -300 400
X GND 4 -400 -400 100 R 40 40 1 1 W 
X MISO/PB1 6 400 100 100 L 40 40 1 1 B 
X MOSI/PB0 5 400 200 100 L 40 40 1 1 B 
X PB3 2 400 -100 100 L 40 40 1 1 B 
X PB4 3 400 -200 100 L 40 40 1 1 B 
X RST/PB5 1 400 -300 100 L 40 40 1 1 B 
X SCK/PB2 7 400 0 100 L 40 40 1 1 B 
X VCC 8 -400 300 100 R 40 40 1 1 W 
ENDDRAW
ENDDEF

#End Library