EESchema-LIBRARY Version 2.3 29/04/2008-12:21:42 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 12 # # Dev Name: CC1000 # Package Name: TSSOP28 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF CC1000 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: CC1000 F0 "IC" -500 900 50 H V L B F1 "CC1000" -500 -1000 50 H V L B F2 "chipcon-ti-TSSOP28" 0 150 50 H I C C DRAW P 2 1 0 0 -500 850 500 850 P 2 1 0 0 500 850 500 -850 P 2 1 0 0 500 -850 -500 -850 P 2 1 0 0 -500 -850 -500 850 X CHP-OUT 12 -700 0 200 R 40 40 1 1 O X DCLK 24 -700 300 200 R 40 40 1 1 O X DIO 23 -700 200 200 R 40 40 1 1 B X L1 10 700 -100 200 L 40 40 1 1 I X L2 11 700 -400 200 L 40 40 1 1 I X PALE 27 -700 700 200 R 40 40 1 1 I X PCLK 25 -700 500 200 R 40 40 1 1 I X PDATA 26 -700 600 200 R 40 40 1 1 B X RBIAS 13 700 -700 200 L 40 40 1 1 O X RF-IN 3 700 700 200 L 40 40 1 1 I X RF-OUT 4 700 400 200 L 40 40 1 1 O X RSSI/IF 28 -700 -200 200 R 40 40 1 1 O X XOSC-1 18 -700 -400 200 R 40 40 1 1 I X XOSC-2 17 -700 -700 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: CC1000-PWR P 2 2 0 0 -500 650 500 650 P 2 2 0 0 500 650 500 -650 P 2 2 0 0 500 -650 -500 -650 P 2 2 0 0 -500 -650 -500 650 X AGND@1 2 700 0 200 L 40 40 2 1 W X AGND@2 6 700 -100 200 L 40 40 2 1 W X AGND@3 7 700 -200 200 L 40 40 2 1 W X AGND@4 8 700 -300 200 L 40 40 2 1 W X AGND@5 14 700 -400 200 L 40 40 2 1 W X AGND@6 16 700 -500 200 L 40 40 2 1 W X AGND@7 19 -700 -500 200 R 40 40 2 1 W X AVDD@1 1 700 500 200 L 40 40 2 1 W X AVDD@2 5 700 400 200 L 40 40 2 1 W X AVDD@3 9 700 300 200 L 40 40 2 1 W X AVDD@4 15 700 200 200 L 40 40 2 1 W X DGND@1 20 -700 0 200 R 40 40 2 1 W X DGND@2 22 -700 -100 200 R 40 40 2 1 W X DVDD 21 -700 200 200 R 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: CC1000-UCSP # Package Name: ULTRA-CSP # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF CC1000-UCSP IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: CC1000 F0 "IC" -500 900 50 H V L B F1 "CC1000-UCSP" -500 -1000 50 H V L B F2 "chipcon-ti-ULTRA-CSP" 0 150 50 H I C C DRAW P 2 1 0 0 -500 850 500 850 P 2 1 0 0 500 850 500 -850 P 2 1 0 0 500 -850 -500 -850 P 2 1 0 0 -500 -850 -500 850 X CHP-OUT B2@6 -700 0 200 R 40 40 1 1 O X DCLK F4@24 -700 300 200 R 40 40 1 1 O X DIO E4@20 -700 200 200 R 40 40 1 1 B X L1 B1@5 700 -100 200 L 40 40 1 1 I X L2 A1@1 700 -400 200 L 40 40 1 1 I X PALE D2@14 -700 700 200 R 40 40 1 1 I X PCLK G4@28 -700 500 200 R 40 40 1 1 I X PDATA D3@15 -700 600 200 R 40 40 1 1 B X RBIAS C2@10 700 -700 200 L 40 40 1 1 O X RF-IN G2@26 700 700 200 L 40 40 1 1 I X RF-OUT G1@25 700 400 200 L 40 40 1 1 O X RSSI/IF E3@19 -700 -200 200 R 40 40 1 1 O X XOSC-1 A4@4 -700 -400 200 R 40 40 1 1 I X XOSC-2 A3@3 -700 -700 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: CC1000-PWR P 2 2 0 0 -500 650 500 650 P 2 2 0 0 500 650 500 -650 P 2 2 0 0 500 -650 -500 -650 P 2 2 0 0 -500 -650 -500 650 X AGND@1 F2@22 700 0 200 L 40 40 2 1 W X AGND@2 E2@18 700 -100 200 L 40 40 2 1 W X AGND@3 E1@17 700 -200 200 L 40 40 2 1 W X AGND@4 D1@13 700 -300 200 L 40 40 2 1 W X AGND@5 F3@23 700 -400 200 L 40 40 2 1 W X AGND@6 B3@7 700 -500 200 L 40 40 2 1 W X AGND@7 B4@8 -700 -500 200 R 40 40 2 1 W X AVDD@1 G3@27 700 500 200 L 40 40 2 1 W X AVDD@2 F1@21 700 400 200 L 40 40 2 1 W X AVDD@3 C1@9 700 300 200 L 40 40 2 1 W X AVDD@4 A2@2 700 200 200 L 40 40 2 1 W X DGND@1 C3@11 -700 0 200 R 40 40 2 1 W X DGND@2 D4@16 -700 -100 200 R 40 40 2 1 W X DVDD C4@12 -700 200 200 R 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: CC1020 # Package Name: QFN-32 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CC1020 IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CC1020 F0 "IC" -500 900 50 H V L B F1 "CC1020" -500 -1000 50 H V L B F2 "chipcon-ti-QFN-32" 0 150 50 H I C C DRAW P 2 1 0 0 -500 850 500 850 P 2 1 0 0 500 850 500 -850 P 2 1 0 0 500 -850 -500 -850 P 2 1 0 0 -500 -850 -500 850 X CHP-OUT 28 700 -500 200 L 40 40 1 1 O X DCLK 7 -700 300 200 R 40 40 1 1 O X DIO 8 -700 200 200 R 40 40 1 1 B X LNA-EN 14 -700 -100 200 R 40 40 1 1 O X LOCK 9 -700 0 200 R 40 40 1 1 O X PA-EN 15 -700 -200 200 R 40 40 1 1 O X PCLK 1 -700 600 200 R 40 40 1 1 I X PDI 2 -700 500 200 R 40 40 1 1 I X PDO 3 -700 400 200 R 40 40 1 1 O X PSEL 32 -700 700 200 R 40 40 1 1 I X R-BIAS 17 700 -700 200 L 40 40 1 1 O X RF-IN 19 700 700 200 L 40 40 1 1 I X RF-OUT 21 700 400 200 L 40 40 1 1 O X VC 24 700 -300 200 L 40 40 1 1 I X XOSC-Q1 10 -700 -400 200 R 40 40 1 1 I X XOSC-Q2 11 -700 -700 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: CC1020-PWR P 2 2 0 0 -500 850 500 850 P 2 2 0 0 500 850 500 -750 P 2 2 0 0 500 -750 -500 -750 P 2 2 0 0 -500 -750 -500 850 X AD-REF 26 -700 -600 200 R 40 40 2 1 W X AGND 25 700 300 200 L 40 40 2 1 W X AVDD@1 16 -700 400 200 R 40 40 2 1 W X AVDD@2 12 -700 300 200 R 40 40 2 1 W X AVDD@3 13 -700 200 200 R 40 40 2 1 W X AVDD@4 18 -700 100 200 R 40 40 2 1 W X AVDD@5 20 -700 0 200 R 40 40 2 1 W X AVDD@6 22 -700 -100 200 R 40 40 2 1 W X AVDD@7 23 -700 -200 200 R 40 40 2 1 W X AVDD@8 27 -700 -300 200 R 40 40 2 1 W X AVDD@9 29 -700 -400 200 R 40 40 2 1 W X DGND@1 4 700 700 200 L 40 40 2 1 W X DGND@2 6 700 600 200 L 40 40 2 1 W X DGND@3 30 700 500 200 L 40 40 2 1 W X DVDD@1 5 -700 700 200 R 40 40 2 1 W X DVDD@2 31 -700 600 200 R 40 40 2 1 W # Gate Name: PL # Symbol Name: PLANE-QFN32 P 2 3 0 0 -500 150 500 150 P 2 3 0 0 500 150 500 -100 P 2 3 0 0 500 -100 -500 -100 P 2 3 0 0 -500 -100 -500 150 T 0 25 85 70 0 3 0 PLANE T 0 0 -25 50 0 3 0 AGND X AGND@1 33 -400 -300 200 U 40 40 3 1 W X AGND@2 34 -300 -300 200 U 40 40 3 1 W X AGND@3 35 -200 -300 200 U 40 40 3 1 W X AGND@4 36 -100 -300 200 U 40 40 3 1 W X AGND@5 37 0 -300 200 U 40 40 3 1 W X AGND@6 38 100 -300 200 U 40 40 3 1 W X AGND@7 39 300 -300 200 U 40 40 3 1 W X AGND@8 40 200 -300 200 U 40 40 3 1 W X AGND@9 41 400 -300 200 U 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CC1050 # Package Name: TSSOP24 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF CC1050 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: CC1050 F0 "IC" -500 900 50 H V L B F1 "CC1050" -500 -1000 50 H V L B F2 "chipcon-ti-TSSOP24" 0 150 50 H I C C DRAW P 2 1 0 0 -500 850 500 850 P 2 1 0 0 500 850 500 -850 P 2 1 0 0 500 -850 -500 -850 P 2 1 0 0 -500 -850 -500 850 X CHP-OUT 8 -700 0 200 R 40 40 1 1 O X DCLK 20 -700 300 200 R 40 40 1 1 O X DI 19 -700 200 200 R 40 40 1 1 I X L1 5 700 -100 200 L 40 40 1 1 I X L2 6 700 -400 200 L 40 40 1 1 I X PALE 23 -700 700 200 R 40 40 1 1 I X PCLK 21 -700 500 200 R 40 40 1 1 I X PDATA 22 -700 600 200 R 40 40 1 1 B X RBIAS 9 700 -700 200 L 40 40 1 1 O X RF-OUT 24 700 700 200 L 40 40 1 1 O X XOSC-1 14 -700 -400 200 R 40 40 1 1 I X XOSC-2 13 -700 -700 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: CC1050-PWR P 2 2 0 0 -500 650 500 650 P 2 2 0 0 500 650 500 -650 P 2 2 0 0 500 -650 -500 -650 P 2 2 0 0 -500 -650 -500 650 X AGND@1 2 700 0 200 L 40 40 2 1 W X AGND@2 3 700 -100 200 L 40 40 2 1 W X AGND@3 4 700 -200 200 L 40 40 2 1 W X AGND@4 10 700 -300 200 L 40 40 2 1 W X AGND@5 12 700 -400 200 L 40 40 2 1 W X AGND@6 15 700 -500 200 L 40 40 2 1 W X AVDD@1 1 700 500 200 L 40 40 2 1 W X AVDD@2 7 700 400 200 L 40 40 2 1 W X AVDD@3 11 700 300 200 L 40 40 2 1 W X DGND@1 16 -700 0 200 R 40 40 2 1 W X DGND@2 18 -700 -100 200 R 40 40 2 1 W X DVDD 17 -700 200 200 R 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: CC1100 # Package Name: QLP-20 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF CC1100 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: CC1100 F0 "IC" -500 700 50 H V L B F1 "CC1100" -500 -900 50 H V L B F2 "chipcon-ti-QLP-20" 0 150 50 H I C C DRAW P 2 1 0 0 -500 650 500 650 P 2 1 0 0 500 650 500 -750 P 2 1 0 0 500 -750 -500 -750 P 2 1 0 0 -500 -750 -500 650 X CS 7 -700 200 200 R 40 40 1 1 I I X DCOUPL 5 700 -300 200 L 40 40 1 1 w X DGUARD 18 700 -200 200 L 40 40 1 1 W X GDO0 6 -700 0 200 R 40 40 1 1 O X GDO2 3 -700 -100 200 R 40 40 1 1 O X RBIAS 17 700 -600 200 L 40 40 1 1 B X RF-N 13 700 300 200 L 40 40 1 1 B X RF-P 12 700 500 200 L 40 40 1 1 B X SCLK 1 -700 500 200 R 40 40 1 1 I X SI 20 -700 300 200 R 40 40 1 1 I X SO/GDO1 2 -700 400 200 R 40 40 1 1 O X XOSC-1 8 -700 -300 200 R 40 40 1 1 I X XOSC-2 10 -700 -600 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: CC1100-PWR P 2 2 0 0 -500 450 500 450 P 2 2 0 0 500 450 500 -400 P 2 2 0 0 500 -400 -500 -400 P 2 2 0 0 -500 -400 -500 450 T 0 -10 -315 70 0 2 0 AGND X AGND 21 0 -500 100 U 40 40 2 1 W X AVDD@1 9 -700 300 200 R 40 40 2 1 W X AVDD@2 11 -700 200 200 R 40 40 2 1 W X AVDD@3 14 700 300 200 L 40 40 2 1 W X AVDD@4 15 700 200 200 L 40 40 2 1 W X DVDD 4 -700 -100 200 R 40 40 2 1 W X GND@1 16 700 0 200 L 40 40 2 1 W X GND@2 19 700 -100 200 L 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: CC1110 # Package Name: QLP-36 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF CC1110 IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: CC1110 F0 "IC" -700 1600 50 H V L B F1 "CC1110" 0 0 50 H V L B F2 "chipcon-ti-QLP-36" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1550 700 1550 P 2 1 0 0 700 1550 700 -1500 P 2 1 0 0 700 -1500 350 -1500 P 2 1 0 0 350 -1500 -350 -1500 P 2 1 0 0 -350 -1500 -700 -1500 P 2 1 0 0 -700 -1500 -700 1550 P 2 1 0 0 -350 -1500 -350 -1350 P 2 1 0 0 -350 -1350 350 -1350 P 2 1 0 0 350 -1350 350 -1500 T 0 47 -1417 66 0 1 0 GND-PLANE T 0 675 -1665 70 0 1 0 VALUE X AVDD-DREG 29 900 1400 200 L 40 40 1 1 W X AVDD@1 19 -900 1200 200 R 40 40 1 1 W X AVDD@2 22 -900 1100 200 R 40 40 1 1 W X AVDD@3 25 900 1200 200 L 40 40 1 1 W X AVDD@4 26 900 1100 200 L 40 40 1 1 W X DCOUPL 30 900 1000 200 L 40 40 1 1 B X DVDD@1 2 -900 1400 200 R 40 40 1 1 W X DVDD@2 10 -900 1300 200 R 40 40 1 1 W X GND@1 40 -300 -1700 200 U 40 40 1 1 W X GND@2 39 -100 -1700 200 U 40 40 1 1 W X GND@3 38 100 -1700 200 U 40 40 1 1 W X GND@4 37 300 -1700 200 U 40 40 1 1 W X GUARD 28 900 1300 200 L 40 40 1 1 W X P0.0 5 -900 900 200 R 40 40 1 1 B X P0.1 6 -900 800 200 R 40 40 1 1 B X P0.2 7 -900 700 200 R 40 40 1 1 B X P0.3 8 -900 600 200 R 40 40 1 1 B X P0.4 9 -900 500 200 R 40 40 1 1 B X P0.5 11 -900 400 200 R 40 40 1 1 B X P0.6 12 -900 300 200 R 40 40 1 1 B X P0.7 13 -900 200 200 R 40 40 1 1 B X P1.0 4 -900 0 200 R 40 40 1 1 B X P1.1 3 -900 -100 200 R 40 40 1 1 B X P1.2 1 -900 -200 200 R 40 40 1 1 B X P1.3 36 -900 -300 200 R 40 40 1 1 B X P1.4 35 -900 -400 200 R 40 40 1 1 B X P1.5 34 -900 -500 200 R 40 40 1 1 B X P1.6 33 -900 -600 200 R 40 40 1 1 B X P1.7 32 -900 -700 200 R 40 40 1 1 B X P2.0 14 -900 -900 200 R 40 40 1 1 B X P2.1 15 -900 -1000 200 R 40 40 1 1 B X P2.2 16 -900 -1100 200 R 40 40 1 1 B X P2.3/XOSC32-1 17 900 -100 200 L 40 40 1 1 B X P2.4/XOSC32-2 18 900 -400 200 L 40 40 1 1 B X RBIAS 27 900 -1300 200 L 40 40 1 1 B X RESET 31 -900 -1300 200 R 40 40 1 1 I I X RF-N 24 900 300 200 L 40 40 1 1 B X RF-P 23 900 600 200 L 40 40 1 1 B X XOSC1 21 900 -1000 200 L 40 40 1 1 B X XOSC2 20 900 -700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: CC1150 # Package Name: QLP-16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF CC1150 IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: CC1150 F0 "IC" -500 1000 50 H V L B F1 "CC1150" 200 -1000 50 H V L B F2 "chipcon-ti-QLP-16" 0 150 50 H I C C DRAW P 2 1 0 0 -500 950 500 950 P 2 1 0 0 500 950 500 -800 P 2 1 0 0 500 -800 -500 -800 P 2 1 0 0 -500 -800 -500 950 T 0 -1 -717 66 0 1 0 GND X AVDD@1 6 700 -300 200 L 40 40 1 1 W X AVDD@2 12 700 -400 200 L 40 40 1 1 W X AVDD@3 13 700 -500 200 L 40 40 1 1 W X CS 9 -700 500 200 R 40 40 1 1 I I X DCOUPL 4 -700 0 200 R 40 40 1 1 B X DGUARD 15 700 -600 200 L 40 40 1 1 W X DVDD 3 700 -200 200 L 40 40 1 1 W X GDO0/ATEST 8 -700 200 200 R 40 40 1 1 O X GND 17 0 -900 100 U 40 40 1 1 W X RBIAS 14 -700 -200 200 R 40 40 1 1 B X RF-N 11 700 800 200 L 40 40 1 1 B X RF-P 10 700 600 200 L 40 40 1 1 B X SCLK 1 -700 800 200 R 40 40 1 1 I X SI 16 -700 600 200 R 40 40 1 1 I X SO/GDO1 2 -700 700 200 R 40 40 1 1 O X XOSC1 5 -700 -400 200 R 40 40 1 1 I X XOSC2 7 -700 -600 200 R 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: CC2430 # Package Name: QLP-48 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF CC2430 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: CC2430 F0 "IC" -700 1400 50 H V L B F1 "CC2430" 0 0 50 H V L B F2 "chipcon-ti-QLP-48" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1350 700 1350 P 2 1 0 0 700 1350 700 -1350 P 2 1 0 0 700 -1350 -700 -1350 P 2 1 0 0 -700 -1350 -700 1350 T 0 -525 -1465 70 0 1 0 VALUE X DCOUPL 42 900 -800 200 L 40 40 1 1 B X P0.0 11 -900 1200 200 R 40 40 1 1 B X P0.1 12 -900 1100 200 R 40 40 1 1 B X P0.2 13 -900 1000 200 R 40 40 1 1 B X P0.3 14 -900 900 200 R 40 40 1 1 B X P0.4 15 -900 800 200 R 40 40 1 1 B X P0.5 16 -900 700 200 R 40 40 1 1 B X P0.6 17 -900 600 200 R 40 40 1 1 B X P0.7 18 -900 500 200 R 40 40 1 1 B X P1.0 9 -900 200 200 R 40 40 1 1 B X P1.1 8 -900 100 200 R 40 40 1 1 B X P1.2 6 -900 0 200 R 40 40 1 1 B X P1.3 5 -900 -100 200 R 40 40 1 1 B X P1.4 4 -900 -200 200 R 40 40 1 1 B X P1.5 3 -900 -300 200 R 40 40 1 1 B X P1.6 2 -900 -400 200 R 40 40 1 1 B X P1.7 1 -900 -500 200 R 40 40 1 1 B X P2.0 48 -900 -700 200 R 40 40 1 1 B X P2.1 46 -900 -800 200 R 40 40 1 1 B X P2.2 45 -900 -900 200 R 40 40 1 1 B X RBIAS1 22 900 -1200 200 L 40 40 1 1 B X RBIAS2 26 900 -1000 200 L 40 40 1 1 W X RESET 10 -900 -1200 200 R 40 40 1 1 I I X RF-N 34 900 1200 200 L 40 40 1 1 B X RF-P 32 900 800 200 L 40 40 1 1 B X TXRX-SWITCH 33 900 1000 200 L 40 40 1 1 O X XOSC1 21 900 -500 200 L 40 40 1 1 B X XOSC2 19 900 -200 200 L 40 40 1 1 B X XOSC32-1\P2.3 44 900 400 200 L 40 40 1 1 B X XOSC32-2\P2.4 43 900 100 200 L 40 40 1 1 B # Gate Name: P # Symbol Name: CC2430-PWR P 2 2 0 0 -800 750 800 750 P 2 2 0 0 800 750 800 -750 P 2 2 0 0 800 -750 -100 -750 P 2 2 0 0 -100 -750 -800 -750 P 2 2 0 0 -800 -750 -800 -100 P 2 2 0 0 -800 -100 -800 750 P 2 2 0 0 -800 -100 -100 -100 P 2 2 0 0 -100 -100 -100 -750 X AGND@1 49 -1000 -300 200 R 40 40 2 1 W X AGND@2 50 -1000 -400 200 R 40 40 2 1 W X AGND@3 51 -1000 -500 200 R 40 40 2 1 W X AGND@4 52 -1000 -600 200 R 40 40 2 1 W X AVDD-ADC 38 1000 -400 200 L 40 40 2 1 W X AVDD-CHP 27 1000 400 200 L 40 40 2 1 W X AVDD-DGUARD 40 1000 -600 200 L 40 40 2 1 W X AVDD-DREG 41 -1000 600 200 R 40 40 2 1 W X AVDD-IF1 25 1000 500 200 L 40 40 2 1 W X AVDD-IF2 37 1000 -300 200 L 40 40 2 1 W X AVDD-PRE 30 1000 100 200 L 40 40 2 1 W X AVDD-RF1 31 1000 0 200 L 40 40 2 1 W X AVDD-RF2 36 1000 -200 200 L 40 40 2 1 W X AVDD-RREG 23 -1000 200 200 R 40 40 2 1 W X AVDD-SOC 20 -1000 300 200 R 40 40 2 1 W X AVDD-SW 35 1000 -100 200 L 40 40 2 1 W X AVDD-VCO 29 1000 200 200 L 40 40 2 1 W X DVDD-ADC 39 1000 -500 200 L 40 40 2 1 W X DVDD@1 7 -1000 500 200 R 40 40 2 1 W X DVDD@2 47 -1000 400 200 R 40 40 2 1 W X RREG-OUT 24 1000 600 200 L 40 40 2 1 w X VCO-GUARD 28 1000 300 200 L 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: CC2500 # Package Name: QLP-20 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF CC2500 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: CC1100 F0 "IC" -500 700 50 H V L B F1 "CC2500" -500 -900 50 H V L B F2 "chipcon-ti-QLP-20" 0 150 50 H I C C DRAW P 2 1 0 0 -500 650 500 650 P 2 1 0 0 500 650 500 -750 P 2 1 0 0 500 -750 -500 -750 P 2 1 0 0 -500 -750 -500 650 X CS 7 -700 200 200 R 40 40 1 1 I I X DCOUPL 5 700 -300 200 L 40 40 1 1 w X DGUARD 18 700 -200 200 L 40 40 1 1 W X GDO0 6 -700 0 200 R 40 40 1 1 O X GDO2 3 -700 -100 200 R 40 40 1 1 O X RBIAS 17 700 -600 200 L 40 40 1 1 B X RF-N 13 700 300 200 L 40 40 1 1 B X RF-P 12 700 500 200 L 40 40 1 1 B X SCLK 1 -700 500 200 R 40 40 1 1 I X SI 20 -700 300 200 R 40 40 1 1 I X SO/GDO1 2 -700 400 200 R 40 40 1 1 O X XOSC-1 8 -700 -300 200 R 40 40 1 1 I X XOSC-2 10 -700 -600 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: CC1100-PWR P 2 2 0 0 -500 450 500 450 P 2 2 0 0 500 450 500 -400 P 2 2 0 0 500 -400 -500 -400 P 2 2 0 0 -500 -400 -500 450 T 0 -10 -315 70 0 2 0 AGND X AGND 21 0 -500 100 U 40 40 2 1 W X AVDD@1 9 -700 300 200 R 40 40 2 1 W X AVDD@2 11 -700 200 200 R 40 40 2 1 W X AVDD@3 14 700 300 200 L 40 40 2 1 W X AVDD@4 15 700 200 200 L 40 40 2 1 W X DVDD 4 -700 -100 200 R 40 40 2 1 W X GND@1 16 700 0 200 L 40 40 2 1 W X GND@2 19 700 -100 200 L 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: CC2510 # Package Name: QLP-36 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF CC2510 IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: CC1110 F0 "IC" -700 1600 50 H V L B F1 "CC2510" 0 0 50 H V L B F2 "chipcon-ti-QLP-36" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1550 700 1550 P 2 1 0 0 700 1550 700 -1500 P 2 1 0 0 700 -1500 350 -1500 P 2 1 0 0 350 -1500 -350 -1500 P 2 1 0 0 -350 -1500 -700 -1500 P 2 1 0 0 -700 -1500 -700 1550 P 2 1 0 0 -350 -1500 -350 -1350 P 2 1 0 0 -350 -1350 350 -1350 P 2 1 0 0 350 -1350 350 -1500 T 0 47 -1417 66 0 1 0 GND-PLANE T 0 675 -1665 70 0 1 0 VALUE X AVDD-DREG 29 900 1400 200 L 40 40 1 1 W X AVDD@1 19 -900 1200 200 R 40 40 1 1 W X AVDD@2 22 -900 1100 200 R 40 40 1 1 W X AVDD@3 25 900 1200 200 L 40 40 1 1 W X AVDD@4 26 900 1100 200 L 40 40 1 1 W X DCOUPL 30 900 1000 200 L 40 40 1 1 B X DVDD@1 2 -900 1400 200 R 40 40 1 1 W X DVDD@2 10 -900 1300 200 R 40 40 1 1 W X GND@1 40 -300 -1700 200 U 40 40 1 1 W X GND@2 39 -100 -1700 200 U 40 40 1 1 W X GND@3 38 100 -1700 200 U 40 40 1 1 W X GND@4 37 300 -1700 200 U 40 40 1 1 W X GUARD 28 900 1300 200 L 40 40 1 1 W X P0.0 5 -900 900 200 R 40 40 1 1 B X P0.1 6 -900 800 200 R 40 40 1 1 B X P0.2 7 -900 700 200 R 40 40 1 1 B X P0.3 8 -900 600 200 R 40 40 1 1 B X P0.4 9 -900 500 200 R 40 40 1 1 B X P0.5 11 -900 400 200 R 40 40 1 1 B X P0.6 12 -900 300 200 R 40 40 1 1 B X P0.7 13 -900 200 200 R 40 40 1 1 B X P1.0 4 -900 0 200 R 40 40 1 1 B X P1.1 3 -900 -100 200 R 40 40 1 1 B X P1.2 1 -900 -200 200 R 40 40 1 1 B X P1.3 36 -900 -300 200 R 40 40 1 1 B X P1.4 35 -900 -400 200 R 40 40 1 1 B X P1.5 34 -900 -500 200 R 40 40 1 1 B X P1.6 33 -900 -600 200 R 40 40 1 1 B X P1.7 32 -900 -700 200 R 40 40 1 1 B X P2.0 14 -900 -900 200 R 40 40 1 1 B X P2.1 15 -900 -1000 200 R 40 40 1 1 B X P2.2 16 -900 -1100 200 R 40 40 1 1 B X P2.3/XOSC32-1 17 900 -100 200 L 40 40 1 1 B X P2.4/XOSC32-2 18 900 -400 200 L 40 40 1 1 B X RBIAS 27 900 -1300 200 L 40 40 1 1 B X RESET 31 -900 -1300 200 R 40 40 1 1 I I X RF-N 24 900 300 200 L 40 40 1 1 B X RF-P 23 900 600 200 L 40 40 1 1 B X XOSC1 21 900 -1000 200 L 40 40 1 1 B X XOSC2 20 900 -700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: CC2511 # Package Name: QLP-36 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF CC2511 IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: CC2511 F0 "IC" -700 1600 50 H V L B F1 "CC2511" 0 0 50 H V L B F2 "chipcon-ti-QLP-36" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1550 700 1550 P 2 1 0 0 700 1550 700 -1500 P 2 1 0 0 700 -1500 350 -1500 P 2 1 0 0 350 -1500 -350 -1500 P 2 1 0 0 -350 -1500 -700 -1500 P 2 1 0 0 -700 -1500 -700 1550 P 2 1 0 0 -350 -1500 -350 -1350 P 2 1 0 0 -350 -1350 350 -1350 P 2 1 0 0 350 -1350 350 -1500 T 0 47 -1417 66 0 1 0 GND-PLANE T 0 675 -1665 70 0 1 0 VALUE X AVDD-DREG 29 900 1400 200 L 40 40 1 1 W X AVDD@1 19 -900 1200 200 R 40 40 1 1 W X AVDD@2 22 -900 1100 200 R 40 40 1 1 W X AVDD@3 25 900 1200 200 L 40 40 1 1 W X AVDD@4 26 900 1100 200 L 40 40 1 1 W X DCOUPL 30 900 1000 200 L 40 40 1 1 B X DM 11 -900 900 200 R 40 40 1 1 B X DP 10 -900 800 200 R 40 40 1 1 B X DVDD@1 2 -900 1400 200 R 40 40 1 1 W X DVDD@2 12 -900 1300 200 R 40 40 1 1 W X GND@1 40 -300 -1700 200 U 40 40 1 1 W X GND@2 39 -100 -1700 200 U 40 40 1 1 W X GND@3 38 100 -1700 200 U 40 40 1 1 W X GND@4 37 300 -1700 200 U 40 40 1 1 W X GUARD 28 900 1300 200 L 40 40 1 1 W X P0.0 5 -900 700 200 R 40 40 1 1 B X P0.1 6 -900 600 200 R 40 40 1 1 B X P0.2 7 -900 500 200 R 40 40 1 1 B X P0.3 8 -900 400 200 R 40 40 1 1 B X P0.4 9 -900 300 200 R 40 40 1 1 B X P0.5 13 -900 200 200 R 40 40 1 1 B X P1.0 4 -900 0 200 R 40 40 1 1 B X P1.1 3 -900 -100 200 R 40 40 1 1 B X P1.2 1 -900 -200 200 R 40 40 1 1 B X P1.3 36 -900 -300 200 R 40 40 1 1 B X P1.4 35 -900 -400 200 R 40 40 1 1 B X P1.5 34 -900 -500 200 R 40 40 1 1 B X P1.6 33 -900 -600 200 R 40 40 1 1 B X P1.7 32 -900 -700 200 R 40 40 1 1 B X P2.0 14 -900 -900 200 R 40 40 1 1 B X P2.1 15 -900 -1000 200 R 40 40 1 1 B X P2.2 16 -900 -1100 200 R 40 40 1 1 B X P2.3/XOSC32-1 17 900 -100 200 L 40 40 1 1 B X P2.4/XOSC32-2 18 900 -400 200 L 40 40 1 1 B X RBIAS 27 900 -1300 200 L 40 40 1 1 B X RESET 31 -900 -1300 200 R 40 40 1 1 I I X RF-N 24 900 300 200 L 40 40 1 1 B X RF-P 23 900 600 200 L 40 40 1 1 B X XOSC1 21 900 -1000 200 L 40 40 1 1 B X XOSC2 20 900 -700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: CC2550 # Package Name: QLP-16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF CC2550 IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: CC1150 F0 "IC" -500 1000 50 H V L B F1 "CC2550" 200 -1000 50 H V L B F2 "chipcon-ti-QLP-16" 0 150 50 H I C C DRAW P 2 1 0 0 -500 950 500 950 P 2 1 0 0 500 950 500 -800 P 2 1 0 0 500 -800 -500 -800 P 2 1 0 0 -500 -800 -500 950 T 0 -1 -717 66 0 1 0 GND X AVDD@1 6 700 -300 200 L 40 40 1 1 W X AVDD@2 12 700 -400 200 L 40 40 1 1 W X AVDD@3 13 700 -500 200 L 40 40 1 1 W X CS 9 -700 500 200 R 40 40 1 1 I I X DCOUPL 4 -700 0 200 R 40 40 1 1 B X DGUARD 15 700 -600 200 L 40 40 1 1 W X DVDD 3 700 -200 200 L 40 40 1 1 W X GDO0/ATEST 8 -700 200 200 R 40 40 1 1 O X GND 17 0 -900 100 U 40 40 1 1 W X RBIAS 14 -700 -200 200 R 40 40 1 1 B X RF-N 11 700 800 200 L 40 40 1 1 B X RF-P 10 700 600 200 L 40 40 1 1 B X SCLK 1 -700 800 200 R 40 40 1 1 I X SI 16 -700 600 200 R 40 40 1 1 I X SO/GDO1 2 -700 700 200 R 40 40 1 1 O X XOSC1 5 -700 -400 200 R 40 40 1 1 I X XOSC2 7 -700 -600 200 R 40 40 1 1 O ENDDRAW ENDDEF #End Library