EESchema-LIBRARY Version 2.3 29/04/2008-12:22:12 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 11 # # Dev Name: CY8C21534-24PVXI # Package Name: SSOP28 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF CY8C21534-24PVXI IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: CY8C21534 F0 "IC" 0 0 50 H V C C F1 "CY8C21534-24PVXI" 0 0 50 H V C C F2 "cypressmicro-SSOP28" 0 150 50 H I C C DRAW P 2 1 0 0 -800 800 -800 -700 P 2 1 0 0 -800 -700 800 -700 P 2 1 0 0 800 -700 800 800 P 2 1 0 0 800 800 -800 800 C -750 760 14 1 1 0 N T 0 -235 895 70 0 1 0 >name T 0 -230 -815 70 0 1 0 >value X P0.0/AIM 24 900 300 100 L 40 40 1 1 B X P0.1/AIM 4 -900 400 100 R 40 40 1 1 B X P0.2/AIM 25 900 400 100 L 40 40 1 1 B X P0.3/AIM 3 -900 500 100 R 40 40 1 1 B X P0.4/AIM 26 900 500 100 L 40 40 1 1 B X P0.5/AIM 2 -900 600 100 R 40 40 1 1 B X P0.6/AIM 27 900 600 100 L 40 40 1 1 B X P0.7/AIM 1 -900 700 100 R 40 40 1 1 B X P1.0/I2C_SDA/M 15 900 -600 100 L 40 40 1 1 B X P1.1/M/I2C_SCL 13 -900 -500 100 R 40 40 1 1 B X P1.2/M 16 900 -500 100 L 40 40 1 1 B X P1.3/M 12 -900 -400 100 R 40 40 1 1 B X P1.4/EXTCLK/M 17 900 -400 100 L 40 40 1 1 B X P1.5/M/I2C_SDA 11 -900 -300 100 R 40 40 1 1 B X P1.6/M 18 900 -300 100 L 40 40 1 1 B X P1.7/M/I2C_SCL 10 -900 -200 100 R 40 40 1 1 B X P2.0/M 20 900 -100 100 L 40 40 1 1 B X P2.1/M 8 -900 0 100 R 40 40 1 1 B X P2.2/M 21 900 0 100 L 40 40 1 1 B X P2.3/M 7 -900 100 100 R 40 40 1 1 B X P2.4/M 22 900 100 100 L 40 40 1 1 B X P2.5/M 6 -900 200 100 R 40 40 1 1 B X P2.6/M 23 900 200 100 L 40 40 1 1 B X P2.7/M 5 -900 300 100 R 40 40 1 1 B X VDD 28 900 700 100 L 40 40 1 1 B X VSS 9 -900 -100 100 R 40 40 1 1 B X VSS@1 14 -900 -600 100 R 40 40 1 1 B X XRES 19 900 -200 100 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: CY8C25122-24PI # Package Name: PDIP08 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C25122-24PI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C25122 F0 "IC" -150 325 50 H V L B F1 "CY8C25122-24PI" -150 -625 50 H V L B F2 "cypressmicro-PDIP08" 0 150 50 H I C C DRAW P 2 1 0 0 300 300 300 -500 P 2 1 0 0 300 -500 -200 -500 P 2 1 0 0 -200 -500 -200 300 P 2 1 0 0 -200 300 300 300 X P0-2 6 -400 200 200 R 40 40 1 1 B X P0-4 7 -400 0 200 R 40 40 1 1 B X P0-5 2 -400 -200 200 R 40 40 1 1 B X P0-7 1 -400 -400 200 R 40 40 1 1 B X P1-0 5 500 200 200 L 40 40 1 1 B X P1-1 3 500 0 200 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: GND X GND 4 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 8 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26233-24PI # Package Name: PDIP20 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26233-24PI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26233 F0 "IC" -600 1100 50 V V L B F1 "CY8C26233-24PI" -300 -100 50 V V L B F2 "cypressmicro-PDIP20" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 1000 X P0(0) 16 -900 700 200 R 40 40 1 1 B X P0(1) 4 -900 500 200 R 40 40 1 1 B X P0(2) 17 -900 300 200 R 40 40 1 1 B X P0(3) 3 -900 100 200 R 40 40 1 1 B X P0(4) 18 -900 -100 200 R 40 40 1 1 B X P0(5) 2 -900 -300 200 R 40 40 1 1 B X P0(6) 19 -900 -500 200 R 40 40 1 1 B X P0(7) 1 -900 -700 200 R 40 40 1 1 B X P1(0) 11 900 -700 200 L 40 40 1 1 B X P1(1) 9 900 -500 200 L 40 40 1 1 B X P1(2) 12 900 -300 200 L 40 40 1 1 B X P1(3) 8 900 -100 200 L 40 40 1 1 B X P1(4) 13 900 100 200 L 40 40 1 1 B X P1(5) 7 900 300 200 L 40 40 1 1 B X P1(6) 14 900 500 200 L 40 40 1 1 B X P1(7) 6 900 700 200 L 40 40 1 1 B X SMP 5 100 -1200 200 U 40 40 1 1 O X XRES 15 -100 -1200 200 U 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 10 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 20 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26233-24PVI # Package Name: SSOP20 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26233-24PVI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26233 F0 "IC" -600 1100 50 V V L B F1 "CY8C26233-24PVI" -300 -100 50 V V L B F2 "cypressmicro-SSOP20" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 1000 X P0(0) 16 -900 700 200 R 40 40 1 1 B X P0(1) 4 -900 500 200 R 40 40 1 1 B X P0(2) 17 -900 300 200 R 40 40 1 1 B X P0(3) 3 -900 100 200 R 40 40 1 1 B X P0(4) 18 -900 -100 200 R 40 40 1 1 B X P0(5) 2 -900 -300 200 R 40 40 1 1 B X P0(6) 19 -900 -500 200 R 40 40 1 1 B X P0(7) 1 -900 -700 200 R 40 40 1 1 B X P1(0) 11 900 -700 200 L 40 40 1 1 B X P1(1) 9 900 -500 200 L 40 40 1 1 B X P1(2) 12 900 -300 200 L 40 40 1 1 B X P1(3) 8 900 -100 200 L 40 40 1 1 B X P1(4) 13 900 100 200 L 40 40 1 1 B X P1(5) 7 900 300 200 L 40 40 1 1 B X P1(6) 14 900 500 200 L 40 40 1 1 B X P1(7) 6 900 700 200 L 40 40 1 1 B X SMP 5 100 -1200 200 U 40 40 1 1 O X XRES 15 -100 -1200 200 U 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 10 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 20 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26233-24SI # Package Name: SOIC20 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26233-24SI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26233 F0 "IC" -600 1100 50 V V L B F1 "CY8C26233-24SI" -300 -100 50 V V L B F2 "cypressmicro-SOIC20" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 1000 X P0(0) 16 -900 700 200 R 40 40 1 1 B X P0(1) 4 -900 500 200 R 40 40 1 1 B X P0(2) 17 -900 300 200 R 40 40 1 1 B X P0(3) 3 -900 100 200 R 40 40 1 1 B X P0(4) 18 -900 -100 200 R 40 40 1 1 B X P0(5) 2 -900 -300 200 R 40 40 1 1 B X P0(6) 19 -900 -500 200 R 40 40 1 1 B X P0(7) 1 -900 -700 200 R 40 40 1 1 B X P1(0) 11 900 -700 200 L 40 40 1 1 B X P1(1) 9 900 -500 200 L 40 40 1 1 B X P1(2) 12 900 -300 200 L 40 40 1 1 B X P1(3) 8 900 -100 200 L 40 40 1 1 B X P1(4) 13 900 100 200 L 40 40 1 1 B X P1(5) 7 900 300 200 L 40 40 1 1 B X P1(6) 14 900 500 200 L 40 40 1 1 B X P1(7) 6 900 700 200 L 40 40 1 1 B X SMP 5 100 -1200 200 U 40 40 1 1 O X XRES 15 -100 -1200 200 U 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 10 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 20 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26443-24PI # Package Name: PDIP28 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26443-24PI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26443 F0 "IC" -300 200 50 H V L B F1 "CY8C26443-24PI" -300 -300 50 H V L B F2 "cypressmicro-PDIP28" 0 150 50 H I C C DRAW P 2 1 0 0 -800 800 1100 800 P 2 1 0 0 1100 800 1100 -800 P 2 1 0 0 1100 -800 -800 -800 P 2 1 0 0 -800 -800 -800 800 X P0(0) 24 -700 -1000 200 U 40 40 1 1 B X P0(1) 4 -500 -1000 200 U 40 40 1 1 B X P0(2) 25 -300 -1000 200 U 40 40 1 1 B X P0(3) 3 -100 -1000 200 U 40 40 1 1 B X P0(4) 26 100 -1000 200 U 40 40 1 1 B X P0(5) 2 300 -1000 200 U 40 40 1 1 B X P0(6) 27 500 -1000 200 U 40 40 1 1 B X P0(7) 1 700 -1000 200 U 40 40 1 1 B X P1(0) 15 1300 -700 200 L 40 40 1 1 B X P1(1) 13 1300 -500 200 L 40 40 1 1 B X P1(2) 16 1300 -300 200 L 40 40 1 1 B X P1(3) 12 1300 -100 200 L 40 40 1 1 B X P1(4) 17 1300 100 200 L 40 40 1 1 B X P1(5) 11 1300 300 200 L 40 40 1 1 B X P1(6) 18 1300 500 200 L 40 40 1 1 B X P1(7) 10 1300 700 200 L 40 40 1 1 B X P2(0) 20 -700 1000 200 D 40 40 1 1 B X P2(1) 8 -500 1000 200 D 40 40 1 1 B X P2(2) 21 -300 1000 200 D 40 40 1 1 B X P2(3) 7 -100 1000 200 D 40 40 1 1 B X P2(4) 22 100 1000 200 D 40 40 1 1 B X P2(5) 6 300 1000 200 D 40 40 1 1 B X P2(6) 23 500 1000 200 D 40 40 1 1 B X P2(7) 5 700 1000 200 D 40 40 1 1 B X SMP 9 -1000 -300 200 R 40 40 1 1 O X XRES 19 -1000 300 200 R 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 14 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 28 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26443-24PVI # Package Name: SSOP28 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26443-24PVI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26443 F0 "IC" -300 200 50 H V L B F1 "CY8C26443-24PVI" -300 -300 50 H V L B F2 "cypressmicro-SSOP28" 0 150 50 H I C C DRAW P 2 1 0 0 -800 800 1100 800 P 2 1 0 0 1100 800 1100 -800 P 2 1 0 0 1100 -800 -800 -800 P 2 1 0 0 -800 -800 -800 800 X P0(0) 24 -700 -1000 200 U 40 40 1 1 B X P0(1) 4 -500 -1000 200 U 40 40 1 1 B X P0(2) 25 -300 -1000 200 U 40 40 1 1 B X P0(3) 3 -100 -1000 200 U 40 40 1 1 B X P0(4) 26 100 -1000 200 U 40 40 1 1 B X P0(5) 2 300 -1000 200 U 40 40 1 1 B X P0(6) 27 500 -1000 200 U 40 40 1 1 B X P0(7) 1 700 -1000 200 U 40 40 1 1 B X P1(0) 15 1300 -700 200 L 40 40 1 1 B X P1(1) 13 1300 -500 200 L 40 40 1 1 B X P1(2) 16 1300 -300 200 L 40 40 1 1 B X P1(3) 12 1300 -100 200 L 40 40 1 1 B X P1(4) 17 1300 100 200 L 40 40 1 1 B X P1(5) 11 1300 300 200 L 40 40 1 1 B X P1(6) 18 1300 500 200 L 40 40 1 1 B X P1(7) 10 1300 700 200 L 40 40 1 1 B X P2(0) 20 -700 1000 200 D 40 40 1 1 B X P2(1) 8 -500 1000 200 D 40 40 1 1 B X P2(2) 21 -300 1000 200 D 40 40 1 1 B X P2(3) 7 -100 1000 200 D 40 40 1 1 B X P2(4) 22 100 1000 200 D 40 40 1 1 B X P2(5) 6 300 1000 200 D 40 40 1 1 B X P2(6) 23 500 1000 200 D 40 40 1 1 B X P2(7) 5 700 1000 200 D 40 40 1 1 B X SMP 9 -1000 -300 200 R 40 40 1 1 O X XRES 19 -1000 300 200 R 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 14 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 28 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26443-24SI # Package Name: SOIC28 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26443-24SI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26443 F0 "IC" -300 200 50 H V L B F1 "CY8C26443-24SI" -300 -300 50 H V L B F2 "cypressmicro-SOIC28" 0 150 50 H I C C DRAW P 2 1 0 0 -800 800 1100 800 P 2 1 0 0 1100 800 1100 -800 P 2 1 0 0 1100 -800 -800 -800 P 2 1 0 0 -800 -800 -800 800 X P0(0) 24 -700 -1000 200 U 40 40 1 1 B X P0(1) 4 -500 -1000 200 U 40 40 1 1 B X P0(2) 25 -300 -1000 200 U 40 40 1 1 B X P0(3) 3 -100 -1000 200 U 40 40 1 1 B X P0(4) 26 100 -1000 200 U 40 40 1 1 B X P0(5) 2 300 -1000 200 U 40 40 1 1 B X P0(6) 27 500 -1000 200 U 40 40 1 1 B X P0(7) 1 700 -1000 200 U 40 40 1 1 B X P1(0) 15 1300 -700 200 L 40 40 1 1 B X P1(1) 13 1300 -500 200 L 40 40 1 1 B X P1(2) 16 1300 -300 200 L 40 40 1 1 B X P1(3) 12 1300 -100 200 L 40 40 1 1 B X P1(4) 17 1300 100 200 L 40 40 1 1 B X P1(5) 11 1300 300 200 L 40 40 1 1 B X P1(6) 18 1300 500 200 L 40 40 1 1 B X P1(7) 10 1300 700 200 L 40 40 1 1 B X P2(0) 20 -700 1000 200 D 40 40 1 1 B X P2(1) 8 -500 1000 200 D 40 40 1 1 B X P2(2) 21 -300 1000 200 D 40 40 1 1 B X P2(3) 7 -100 1000 200 D 40 40 1 1 B X P2(4) 22 100 1000 200 D 40 40 1 1 B X P2(5) 6 300 1000 200 D 40 40 1 1 B X P2(6) 23 500 1000 200 D 40 40 1 1 B X P2(7) 5 700 1000 200 D 40 40 1 1 B X SMP 9 -1000 -300 200 R 40 40 1 1 O X XRES 19 -1000 300 200 R 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 14 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 28 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26643-24PI # Package Name: PDIP48 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26643-24PI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26663 F0 "IC" -500 1300 50 H V L B F1 "CY8C26643-24PI" -500 -1800 50 H V L B F2 "cypressmicro-PDIP48" 0 150 50 H I C C DRAW P 2 1 0 0 -800 2000 800 2000 P 2 1 0 0 800 2000 800 -2200 P 2 1 0 0 800 -2200 -800 -2200 P 2 1 0 0 -800 -2200 -800 2000 X P0-0 44 -1000 1400 200 R 40 40 1 1 B X P0-1 4 -1000 1200 200 R 40 40 1 1 B X P0-2 45 -1000 1000 200 R 40 40 1 1 B X P0-3 3 -1000 800 200 R 40 40 1 1 B X P0-4 46 -1000 600 200 R 40 40 1 1 B X P0-5 2 -1000 400 200 R 40 40 1 1 B X P0-6 47 -1000 200 200 R 40 40 1 1 B X P0-7 1 -1000 0 200 R 40 40 1 1 B X P1-0 25 -1000 -200 200 R 40 40 1 1 B X P1-1 23 -1000 -400 200 R 40 40 1 1 B X P1-2 26 -1000 -600 200 R 40 40 1 1 B X P1-3 22 -1000 -800 200 R 40 40 1 1 B X P1-4 27 -1000 -1000 200 R 40 40 1 1 B X P1-5 21 -1000 -1200 200 R 40 40 1 1 B X P1-6 28 -1000 -1400 200 R 40 40 1 1 B X P1-7 20 -1000 -1600 200 R 40 40 1 1 B X P2-0 40 -700 -2400 200 U 40 40 1 1 B X P2-1 8 -500 -2400 200 U 40 40 1 1 B X P2-2 41 -300 -2400 200 U 40 40 1 1 B X P2-3 7 -100 -2400 200 U 40 40 1 1 B X P2-4 42 100 -2400 200 U 40 40 1 1 B X P2-5 6 300 -2400 200 U 40 40 1 1 B X P2-6 43 500 -2400 200 U 40 40 1 1 B X P2-7 5 700 -2400 200 U 40 40 1 1 B X P3-0 36 1000 -1600 200 L 40 40 1 1 B X P3-1 12 1000 -1400 200 L 40 40 1 1 B X P3-2 37 1000 -1200 200 L 40 40 1 1 B X P3-3 11 1000 -1000 200 L 40 40 1 1 B X P3-4 38 1000 -800 200 L 40 40 1 1 B X P3-5 10 1000 -600 200 L 40 40 1 1 B X P3-6 39 1000 -400 200 L 40 40 1 1 B X P3-7 9 1000 -200 200 L 40 40 1 1 B X P4-0 31 1000 0 200 L 40 40 1 1 B X P4-1 17 1000 200 200 L 40 40 1 1 B X P4-2 32 1000 400 200 L 40 40 1 1 B X P4-3 16 1000 600 200 L 40 40 1 1 B X P4-4 33 1000 800 200 L 40 40 1 1 B X P4-5 15 1000 1000 200 L 40 40 1 1 B X P4-6 34 1000 1200 200 L 40 40 1 1 B X P4-7 14 1000 1400 200 L 40 40 1 1 B X P5-0 29 500 2200 200 D 40 40 1 1 B X P5-1 19 300 2200 200 D 40 40 1 1 B X P5-2 30 100 2200 200 D 40 40 1 1 B X P5-3 18 -100 2200 200 D 40 40 1 1 B X SMP 13 -300 2200 200 D 40 40 1 1 O X XRES 35 -500 2200 200 D 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 24 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 48 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26643-24PVI # Package Name: SSOP48 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26643-24PVI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26663 F0 "IC" -500 1300 50 H V L B F1 "CY8C26643-24PVI" -500 -1800 50 H V L B F2 "cypressmicro-SSOP48" 0 150 50 H I C C DRAW P 2 1 0 0 -800 2000 800 2000 P 2 1 0 0 800 2000 800 -2200 P 2 1 0 0 800 -2200 -800 -2200 P 2 1 0 0 -800 -2200 -800 2000 X P0-0 44 -1000 1400 200 R 40 40 1 1 B X P0-1 4 -1000 1200 200 R 40 40 1 1 B X P0-2 45 -1000 1000 200 R 40 40 1 1 B X P0-3 3 -1000 800 200 R 40 40 1 1 B X P0-4 46 -1000 600 200 R 40 40 1 1 B X P0-5 2 -1000 400 200 R 40 40 1 1 B X P0-6 47 -1000 200 200 R 40 40 1 1 B X P0-7 1 -1000 0 200 R 40 40 1 1 B X P1-0 25 -1000 -200 200 R 40 40 1 1 B X P1-1 23 -1000 -400 200 R 40 40 1 1 B X P1-2 26 -1000 -600 200 R 40 40 1 1 B X P1-3 22 -1000 -800 200 R 40 40 1 1 B X P1-4 27 -1000 -1000 200 R 40 40 1 1 B X P1-5 21 -1000 -1200 200 R 40 40 1 1 B X P1-6 28 -1000 -1400 200 R 40 40 1 1 B X P1-7 20 -1000 -1600 200 R 40 40 1 1 B X P2-0 40 -700 -2400 200 U 40 40 1 1 B X P2-1 8 -500 -2400 200 U 40 40 1 1 B X P2-2 41 -300 -2400 200 U 40 40 1 1 B X P2-3 7 -100 -2400 200 U 40 40 1 1 B X P2-4 42 100 -2400 200 U 40 40 1 1 B X P2-5 6 300 -2400 200 U 40 40 1 1 B X P2-6 43 500 -2400 200 U 40 40 1 1 B X P2-7 5 700 -2400 200 U 40 40 1 1 B X P3-0 36 1000 -1600 200 L 40 40 1 1 B X P3-1 12 1000 -1400 200 L 40 40 1 1 B X P3-2 37 1000 -1200 200 L 40 40 1 1 B X P3-3 11 1000 -1000 200 L 40 40 1 1 B X P3-4 38 1000 -800 200 L 40 40 1 1 B X P3-5 10 1000 -600 200 L 40 40 1 1 B X P3-6 39 1000 -400 200 L 40 40 1 1 B X P3-7 9 1000 -200 200 L 40 40 1 1 B X P4-0 31 1000 0 200 L 40 40 1 1 B X P4-1 17 1000 200 200 L 40 40 1 1 B X P4-2 32 1000 400 200 L 40 40 1 1 B X P4-3 16 1000 600 200 L 40 40 1 1 B X P4-4 33 1000 800 200 L 40 40 1 1 B X P4-5 15 1000 1000 200 L 40 40 1 1 B X P4-6 34 1000 1200 200 L 40 40 1 1 B X P4-7 14 1000 1400 200 L 40 40 1 1 B X P5-0 29 500 2200 200 D 40 40 1 1 B X P5-1 19 300 2200 200 D 40 40 1 1 B X P5-2 30 100 2200 200 D 40 40 1 1 B X P5-3 18 -100 2200 200 D 40 40 1 1 B X SMP 13 -300 2200 200 D 40 40 1 1 O X XRES 35 -500 2200 200 D 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 24 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 48 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: CY8C26643-24AI # Package Name: TQFP44 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF CY8C26643-24AI IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: CY8C26643-AI F0 "IC" -500 1300 50 H V L B F1 "CY8C26643-24AI" -500 -1800 50 H V L B F2 "cypressmicro-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 2000 800 2000 P 2 1 0 0 800 2000 800 -2200 P 2 1 0 0 800 -2200 -800 -2200 P 2 1 0 0 -800 -2200 -800 2000 X P0-0 35 -1000 1400 200 R 40 40 1 1 B X P0-1 43 -1000 1200 200 R 40 40 1 1 B X P0-2 36 -1000 1000 200 R 40 40 1 1 B X P0-3 42 -1000 800 200 R 40 40 1 1 B X P0-4 37 -1000 600 200 R 40 40 1 1 B X P0-5 41 -1000 400 200 R 40 40 1 1 B X P0-6 38 -1000 200 200 R 40 40 1 1 B X P0-7 40 -1000 0 200 R 40 40 1 1 B X P1-0 18 -1000 -200 200 R 40 40 1 1 B X P1-1 16 -1000 -400 200 R 40 40 1 1 B X P1-2 19 -1000 -600 200 R 40 40 1 1 B X P1-3 15 -1000 -800 200 R 40 40 1 1 B X P1-4 20 -1000 -1000 200 R 40 40 1 1 B X P1-5 14 -1000 -1200 200 R 40 40 1 1 B X P1-6 21 -1000 -1400 200 R 40 40 1 1 B X P1-7 13 -1000 -1600 200 R 40 40 1 1 B X P2-0 31 -700 -2400 200 U 40 40 1 1 B X P2-1 3 -500 -2400 200 U 40 40 1 1 B X P2-2 32 -300 -2400 200 U 40 40 1 1 B X P2-3 2 -100 -2400 200 U 40 40 1 1 B X P2-4 33 100 -2400 200 U 40 40 1 1 B X P2-5 1 300 -2400 200 U 40 40 1 1 B X P2-6 34 500 -2400 200 U 40 40 1 1 B X P2-7 44 700 -2400 200 U 40 40 1 1 B X P3-0 27 1000 -1600 200 L 40 40 1 1 B X P3-1 7 1000 -1400 200 L 40 40 1 1 B X P3-2 28 1000 -1200 200 L 40 40 1 1 B X P3-3 6 1000 -1000 200 L 40 40 1 1 B X P3-4 29 1000 -800 200 L 40 40 1 1 B X P3-5 5 1000 -600 200 L 40 40 1 1 B X P3-6 30 1000 -400 200 L 40 40 1 1 B X P3-7 4 1000 -200 200 L 40 40 1 1 B X P4-0 22 1000 0 200 L 40 40 1 1 B X P4-1 12 1000 200 200 L 40 40 1 1 B X P4-2 23 1000 400 200 L 40 40 1 1 B X P4-3 11 1000 600 200 L 40 40 1 1 B X P4-4 24 1000 800 200 L 40 40 1 1 B X P4-5 10 1000 1000 200 L 40 40 1 1 B X P4-6 25 1000 1200 200 L 40 40 1 1 B X P4-7 9 1000 1400 200 L 40 40 1 1 B X SMP 8 500 2200 200 D 40 40 1 1 O X XRES 26 -500 2200 200 D 40 40 1 1 I # Gate Name: G$2 # Symbol Name: GND X GND 17 0 100 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VCC X VCC 39 0 100 200 D 40 40 3 1 W ENDDRAW ENDDEF #End Library