EESchema-LIBRARY Version 2.3  29/04/2008-12:22:17
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 1
#
# Dev Name: DSP56F8323
# Package Name: LQFP64-10X10
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF DSP56F8323 IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DSP56F8323
F0 "IC" 100 2150 50 H V L B
F1 "DSP56F8323" 0 -2900 50 H V L B
F2 "dsp56f8323-LQFP64-10X10" 0 150 50 H I C C
DRAW
P 2 1 0 0 -600 2100 800 2100
P 2 1 0 0 800 2100 800 -2800
P 2 1 0 0 800 -2800 -600 -2800
P 2 1 0 0 -600 -2800 -600 2100
X ANA0 26 -800 -600 200 R 40 40 1 1 B 
X ANA1 27 -800 -700 200 R 40 40 1 1 B 
X ANA2 28 -800 -800 200 R 40 40 1 1 B 
X ANA3 29 -800 -900 200 R 40 40 1 1 B 
X ANA4 30 -800 -1000 200 R 40 40 1 1 B 
X ANA5 31 -800 -1100 200 R 40 40 1 1 B 
X ANA6 32 -800 -1200 200 R 40 40 1 1 B 
X ANA7 33 -800 -1300 200 R 40 40 1 1 B 
X CAN_RX/PC2 61 1000 -2000 200 L 40 40 1 1 B 
X CAN_TX/PC3 62 1000 -1900 200 L 40 40 1 1 B 
X EXTAL/PC0 46 -800 -2700 200 R 40 40 1 1 B 
X FAULT0/PA6 13 -800 1400 200 R 40 40 1 1 B 
X FAULT1/PA7 14 -800 1300 200 R 40 40 1 1 B 
X FAULT2/PA8 15 -800 1200 200 R 40 40 1 1 B 
X HOME0/TA3/PB4 49 -800 300 200 R 40 40 1 1 B 
X INDEX0/TA2/PB5 50 -800 200 200 R 40 40 1 1 B 
X IRQA* 12 -800 -1600 200 R 40 40 1 1 B I
X ISA0/PA9 16 -800 1100 200 R 40 40 1 1 B 
X ISA1/PA10 18 -800 1000 200 R 40 40 1 1 B 
X ISA2/PA11 19 -800 900 200 R 40 40 1 1 B 
X MISO0/RXD1/PB1 22 -800 600 200 R 40 40 1 1 B 
X MOSI0/PB2 24 -800 500 200 R 40 40 1 1 B 
X OCR_DIS 45 -800 -1800 200 R 40 40 1 1 B 
X PHASEA0/TA0/PB7 52 -800 0 200 R 40 40 1 1 B 
X PHASEB0/TA1/PB6 51 -800 100 200 R 40 40 1 1 B 
X PWMA0/PA0 3 -800 2000 200 R 40 40 1 1 B 
X PWMA1/PA1 4 -800 1900 200 R 40 40 1 1 B 
X PWMA2/SS1*/PA2 7 -800 1800 200 R 40 40 1 1 B 
X PWMA3/MISO1/PA3 8 -800 1700 200 R 40 40 1 1 B 
X PWMA4/MISI1/PA4 9 -800 1600 200 R 40 40 1 1 B 
X PWMA5/SCLK1/PA5 10 -800 1500 200 R 40 40 1 1 B 
X RESET* 2 -800 -1500 200 R 40 40 1 1 B I
X SCLK0/PB3 25 -800 400 200 R 40 40 1 1 B 
X SS0*/TXD1/PB0 21 -800 700 200 R 40 40 1 1 B 
X TC0/TXD0/PC6 1 -800 -400 200 R 40 40 1 1 B 
X TC1/RXD0/PC5 64 -800 -300 200 R 40 40 1 1 B 
X TC3/PC4 63 -800 -200 200 R 40 40 1 1 B 
X TCK 53 -800 -2100 200 R 40 40 1 1 B 
X TD0 56 -800 -2400 200 R 40 40 1 1 B 
X TDI 55 -800 -2300 200 R 40 40 1 1 B 
X TEMP_SENSE 34 -800 -1700 200 R 40 40 1 1 B 
X TMS 54 -800 -2200 200 R 40 40 1 1 B 
X TRST* 58 -800 -1900 200 R 40 40 1 1 B I
X VCAP1 57 1000 -1100 200 L 40 40 1 1 W 
X VCAP2 23 1000 -1300 200 L 40 40 1 1 W 
X VCAP3 5 1000 -1500 200 L 40 40 1 1 W 
X VCAP4 43 1000 -1700 200 L 40 40 1 1 W 
X VDDA_ADC 41 1000 1400 200 L 40 40 1 1 W 
X VDDA_OSC_PLL 42 1000 800 200 L 40 40 1 1 W 
X VDIO1 6 1000 2000 200 L 40 40 1 1 W 
X VDIO2 20 1000 1900 200 L 40 40 1 1 W 
X VDIO3 48 1000 1800 200 L 40 40 1 1 W 
X VDIO4 59 1000 1700 200 L 40 40 1 1 W 
X VREFH 40 1000 1200 200 L 40 40 1 1 I 
X VREFLO 38 1000 -800 200 L 40 40 1 1 B 
X VREFMID 36 1000 -400 200 L 40 40 1 1 B 
X VREFN 35 1000 -200 200 L 40 40 1 1 B 
X VREFP 37 1000 -600 200 L 40 40 1 1 B 
X VSS1 11 1000 -2300 200 L 40 40 1 1 W 
X VSS2 17 1000 -2400 200 L 40 40 1 1 W 
X VSS3 44 1000 -2500 200 L 40 40 1 1 W 
X VSS4 60 1000 -2600 200 L 40 40 1 1 W 
X VSSA_ADC 39 1000 -2700 200 L 40 40 1 1 W 
X XTAL/PC1 47 -800 -2600 200 R 40 40 1 1 B 
ENDDRAW
ENDDEF

#End Library