EESchema-LIBRARY Version 2.3 29/04/2008-12:22:17 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 27 # # Dev Name: MC10119 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10119 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10119 F0 "IC" -300 625 50 H V L B F1 "MC10119" -300 -800 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 200 -700 P 2 1 0 0 200 -700 200 600 P 2 1 0 0 200 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X A0 3 -500 500 200 R 40 40 1 1 I X A1 4 -500 400 200 R 40 40 1 1 I X A2 5 -500 300 200 R 40 40 1 1 I X A3 6 -500 200 200 R 40 40 1 1 I X B/C 10 -500 -100 200 R 40 40 1 1 I X B0 7 -500 100 200 R 40 40 1 1 I X B1 9 -500 0 200 R 40 40 1 1 I X C1 11 -500 -200 200 R 40 40 1 1 I X C2 12 -500 -300 200 R 40 40 1 1 I X D0 13 -500 -400 200 R 40 40 1 1 I X D1 14 -500 -500 200 R 40 40 1 1 I X D2 15 -500 -600 200 R 40 40 1 1 I X O 2 400 0 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10121 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10121 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10121 F0 "IC" -300 625 50 H V L B F1 "MC10121" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 200 -600 P 2 1 0 0 200 -600 200 600 P 2 1 0 0 200 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A0 4 -500 500 200 R 40 40 1 1 I X A1 5 -500 400 200 R 40 40 1 1 I X A2 6 -500 300 200 R 40 40 1 1 I X B/C 10 -500 0 200 R 40 40 1 1 I X B1 7 -500 200 200 R 40 40 1 1 I X B2 9 -500 100 200 R 40 40 1 1 I X C1 11 -500 -100 200 R 40 40 1 1 I X C2 12 -500 -200 200 R 40 40 1 1 I X D1 13 -500 -300 200 R 40 40 1 1 I X D2 14 -500 -400 200 R 40 40 1 1 I X D3 15 -500 -500 200 R 40 40 1 1 I X O 2 400 100 200 L 40 40 1 1 O X O\ 3 400 -100 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10124 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10124 IC 0 40 Y Y 2 L N # Gate Name: A1 # Symbol Name: MC10124 F0 "IC" -300 525 50 H V L B F1 "MC10124" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X I0 5 -500 400 200 R 40 40 1 1 I X I1 7 -500 200 200 R 40 40 1 1 I X I2 10 -500 0 200 R 40 40 1 1 I X I3 11 -500 -200 200 R 40 40 1 1 I X INCOMMON 6 -500 -400 200 R 40 40 1 1 I X O0 2 500 300 200 L 40 40 1 1 O X O0\ 4 500 400 200 L 40 40 1 1 O X O1 1 500 100 200 L 40 40 1 1 O X O1\ 3 500 200 200 L 40 40 1 1 O X O2 15 500 -100 200 L 40 40 1 1 O X O2\ 12 500 0 200 L 40 40 1 1 O X O3 14 500 -300 200 L 40 40 1 1 O X O3\ 13 500 -200 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: VCCVEEGN T 1 50 175 50 0 2 0 VCC T 1 -50 -155 50 0 2 0 VEE T 1 150 -155 50 0 2 0 GND X GND 16 100 -300 200 U 40 40 2 1 W X VCC 9 0 300 200 D 40 40 2 1 W X VEE 8 -100 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10130 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF MC10130 IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: MC10130 F0 "IC" 100 325 50 H V L B F1 "MC10130" 100 -300 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -400 -200 400 -200 P 2 1 0 0 400 -200 400 300 P 2 1 0 0 400 300 -400 300 P 2 1 0 0 -400 300 -400 -200 X CE 11 -600 -100 200 R 40 40 1 1 I I X D 10 -600 200 200 R 40 40 1 1 I X Q 15 600 200 200 L 40 40 1 1 O X Q\ 14 600 -100 200 L 40 40 1 1 O X R 13 0 -400 200 U 40 40 1 1 I X S 12 0 500 200 D 40 40 1 1 I # Gate Name: B # Symbol Name: MC10130 P 2 2 0 0 -400 -200 400 -200 P 2 2 0 0 400 -200 400 300 P 2 2 0 0 400 300 -400 300 P 2 2 0 0 -400 300 -400 -200 X CE 6 -600 -100 200 R 40 40 2 1 I I X D 7 -600 200 200 R 40 40 2 1 I X Q 2 600 200 200 L 40 40 2 1 O X Q\ 3 600 -100 200 L 40 40 2 1 O X R 4 0 -400 200 U 40 40 2 1 I X S 5 0 500 200 D 40 40 2 1 I # Gate Name: C # Symbol Name: CLK X CLK 9 -200 0 200 R 40 40 3 1 I C # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 4 0 VCC T 1 50 -155 50 0 4 0 VEE X VCC@1 1 0 300 200 D 40 40 4 1 W X VCC@2 16 100 300 200 D 40 40 4 1 W X VEE 8 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: MC10135 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF MC10135 IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: MC10135 F0 "IC" 100 325 50 H V L B F1 "MC10135" 100 -400 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 400 -300 P 2 1 0 0 400 -300 400 300 P 2 1 0 0 400 300 -300 300 P 2 1 0 0 -300 300 -300 -300 X J 7 -500 200 200 R 40 40 1 1 I I X K 6 -500 -200 200 R 40 40 1 1 I I X Q 2 600 200 200 L 40 40 1 1 O X Q\ 3 600 -200 200 L 40 40 1 1 O X R 4 0 -500 200 U 40 40 1 1 I X S 5 0 500 200 D 40 40 1 1 I # Gate Name: A1 # Symbol Name: CLK X CLK 9 -200 0 200 R 40 40 2 1 I C # Gate Name: B # Symbol Name: MC10135 P 2 3 0 0 -300 -300 400 -300 P 2 3 0 0 400 -300 400 300 P 2 3 0 0 400 300 -300 300 P 2 3 0 0 -300 300 -300 -300 X J 10 -500 200 200 R 40 40 3 1 I I X K 11 -500 -200 200 R 40 40 3 1 I I X Q 15 600 200 200 L 40 40 3 1 O X Q\ 14 600 -200 200 L 40 40 3 1 O X R 13 0 -500 200 U 40 40 3 1 I X S 12 0 500 200 D 40 40 3 1 I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 4 0 VCC T 1 50 -155 50 0 4 0 VEE X VCC@1 1 0 300 200 D 40 40 4 1 W X VCC@2 16 100 300 200 D 40 40 4 1 W X VEE 8 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: MC10136 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10136 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10136 F0 "IC" -300 525 50 H V L B F1 "MC10136" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X CIN 10 -500 -200 200 R 40 40 1 1 I I X CLK 13 -500 400 200 R 40 40 1 1 I C X COUT 4 500 -200 200 L 40 40 1 1 O I X D0 12 -500 300 200 R 40 40 1 1 I X D1 11 -500 200 200 R 40 40 1 1 I X D2 6 -500 100 200 R 40 40 1 1 I X D3 5 -500 0 200 R 40 40 1 1 I X Q0 14 500 300 200 L 40 40 1 1 O X Q1 15 500 200 200 L 40 40 1 1 O X Q2 2 500 100 200 L 40 40 1 1 O X Q3 3 500 0 200 L 40 40 1 1 O X S1 9 -500 -300 200 R 40 40 1 1 I X S2 7 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10141 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10141 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10141 F0 "IC" -300 525 50 H V L B F1 "MC10141" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 4 -500 400 200 R 40 40 1 1 I C X D0 12 -500 300 200 R 40 40 1 1 I X D1 11 -500 200 200 R 40 40 1 1 I X D2 9 -500 100 200 R 40 40 1 1 I X D3 6 -500 0 200 R 40 40 1 1 I X DL 13 -500 -300 200 R 40 40 1 1 I X DR 5 -500 -200 200 R 40 40 1 1 I X Q0 14 500 300 200 L 40 40 1 1 O X Q1 15 500 200 200 L 40 40 1 1 O X Q2 2 500 100 200 L 40 40 1 1 O X Q3 3 500 0 200 L 40 40 1 1 O X S1 10 -500 -400 200 R 40 40 1 1 I X S2 7 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10158 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10158 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10158 F0 "IC" -300 525 50 H V L B F1 "MC10158" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X D00 6 -500 400 200 R 40 40 1 1 I X D01 5 -500 300 200 R 40 40 1 1 I X D10 4 -500 200 200 R 40 40 1 1 I X D11 3 -500 100 200 R 40 40 1 1 I X D20 13 -500 0 200 R 40 40 1 1 I X D21 12 -500 -100 200 R 40 40 1 1 I X D30 11 -500 -200 200 R 40 40 1 1 I X D31 10 -500 -300 200 R 40 40 1 1 I X Q0 1 500 400 200 L 40 40 1 1 O X Q1 2 500 200 200 L 40 40 1 1 O X Q2 15 500 0 200 L 40 40 1 1 O X Q3 14 500 -200 200 L 40 40 1 1 O X SEL 9 -500 -500 200 R 40 40 1 1 I I # Gate Name: P # Symbol Name: 1VCC1VEE T 1 50 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC 16 0 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10159 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10159 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10159 F0 "IC" -300 625 50 H V L B F1 "MC10159" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X D00 6 -500 500 200 R 40 40 1 1 I X D01 5 -500 400 200 R 40 40 1 1 I X D10 4 -500 300 200 R 40 40 1 1 I X D11 3 -500 200 200 R 40 40 1 1 I X D20 13 -500 100 200 R 40 40 1 1 I X D21 12 -500 0 200 R 40 40 1 1 I X D30 11 -500 -100 200 R 40 40 1 1 I X D31 10 -500 -200 200 R 40 40 1 1 I X ENABLE 7 -500 -500 200 R 40 40 1 1 I I X Q0 1 500 500 200 L 40 40 1 1 O I X Q1 2 500 300 200 L 40 40 1 1 O I X Q2 15 500 100 200 L 40 40 1 1 O I X Q3 14 500 -100 200 L 40 40 1 1 O I X SEL 9 -500 -400 200 R 40 40 1 1 I I # Gate Name: P # Symbol Name: 1VCC1VEE T 1 50 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC 16 0 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10160 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10160 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10160 F0 "IC" -300 625 50 H V L B F1 "MC10160" -300 -800 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X I1 3 -500 500 200 R 40 40 1 1 I X I2 4 -500 400 200 R 40 40 1 1 I X I3 5 -500 300 200 R 40 40 1 1 I X I4 6 -500 200 200 R 40 40 1 1 I X I5 7 -500 100 200 R 40 40 1 1 I X I6 9 -500 0 200 R 40 40 1 1 I X I7 10 -500 -100 200 R 40 40 1 1 I X I8 11 -500 -200 200 R 40 40 1 1 I X I9 12 -500 -300 200 R 40 40 1 1 I X I10 13 -500 -400 200 R 40 40 1 1 I X I11 14 -500 -500 200 R 40 40 1 1 I X I12 15 -500 -600 200 R 40 40 1 1 I X OUT 2 500 0 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10161 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10161 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10161 F0 "IC" -300 425 50 H V L B F1 "MC10161" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A 7 -500 0 200 R 40 40 1 1 I X B 9 -500 -200 200 R 40 40 1 1 I X C 14 -500 -400 200 R 40 40 1 1 I X E0 2 -500 300 200 R 40 40 1 1 I I X E1 15 -500 200 200 R 40 40 1 1 I I X Q0 6 500 300 200 L 40 40 1 1 O X Q1 5 500 200 200 L 40 40 1 1 O X Q2 4 500 100 200 L 40 40 1 1 O X Q3 3 500 0 200 L 40 40 1 1 O X Q4 13 500 -100 200 L 40 40 1 1 O X Q5 12 500 -200 200 L 40 40 1 1 O X Q6 11 500 -300 200 L 40 40 1 1 O X Q7 10 500 -400 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10162 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10162 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10162 F0 "IC" -300 425 50 H V L B F1 "MC10162" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A 7 -500 0 200 R 40 40 1 1 I X B 9 -500 -200 200 R 40 40 1 1 I X C 14 -500 -400 200 R 40 40 1 1 I X E0 2 -500 300 200 R 40 40 1 1 I I X E1 15 -500 200 200 R 40 40 1 1 I I X Q0 6 500 300 200 L 40 40 1 1 O I X Q1 5 500 200 200 L 40 40 1 1 O I X Q2 4 500 100 200 L 40 40 1 1 O I X Q3 3 500 0 200 L 40 40 1 1 O I X Q4 13 500 -100 200 L 40 40 1 1 O I X Q5 12 500 -200 200 L 40 40 1 1 O I X Q6 11 500 -300 200 L 40 40 1 1 O I X Q7 10 500 -400 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10164 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10164 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10164 F0 "IC" -300 725 50 H V L B F1 "MC10164" -300 -800 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 700 P 2 1 0 0 300 700 -300 700 P 2 1 0 0 -300 700 -300 -700 X A 7 -500 600 200 R 40 40 1 1 I X B 9 -500 500 200 R 40 40 1 1 I X C 10 -500 400 200 R 40 40 1 1 I X ENABLE 2 -500 300 200 R 40 40 1 1 I I X X0 6 -500 100 200 R 40 40 1 1 I X X1 5 -500 0 200 R 40 40 1 1 I X X2 4 -500 -100 200 R 40 40 1 1 I X X3 3 -500 -200 200 R 40 40 1 1 I X X4 11 -500 -300 200 R 40 40 1 1 I X X5 12 -500 -400 200 R 40 40 1 1 I X X6 13 -500 -500 200 R 40 40 1 1 I X X7 14 -500 -600 200 R 40 40 1 1 I X Z 15 500 500 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10165 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10165 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10165 F0 "IC" -300 525 50 H V L B F1 "MC10165" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 4 -500 400 200 R 40 40 1 1 I C X D0 5 -500 200 200 R 40 40 1 1 I X D1 7 -500 100 200 R 40 40 1 1 I X D2 13 -500 0 200 R 40 40 1 1 I X D3 10 -500 -100 200 R 40 40 1 1 I X D4 11 -500 -200 200 R 40 40 1 1 I X D5 12 -500 -300 200 R 40 40 1 1 I X D6 9 -500 -400 200 R 40 40 1 1 I X D7 6 -500 -500 200 R 40 40 1 1 I X Q0 3 500 200 200 L 40 40 1 1 O X Q1 2 500 100 200 L 40 40 1 1 O X Q2 15 500 0 200 L 40 40 1 1 O X Q3 14 500 -100 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10166 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10166 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10166 F0 "IC" -300 625 50 H V L B F1 "MC10166" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A0 5 -500 500 200 R 40 40 1 1 I X A1 6 -500 300 200 R 40 40 1 1 I X A2 13 -500 100 200 R 40 40 1 1 I X A3 12 -500 -100 200 R 40 40 1 1 I X A4 9 -500 -300 200 R 40 40 1 1 I X AB 2 500 300 200 L 40 40 1 1 O I X B0 4 -500 400 200 R 40 40 1 1 I X B1 7 -500 200 200 R 40 40 1 1 I X B2 14 -500 0 200 R 40 40 1 1 I X B3 11 -500 -200 200 R 40 40 1 1 I X B4 10 -500 -400 200 R 40 40 1 1 I X EN\ 15 -500 -500 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10170 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10170 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10170 F0 "IC" -300 625 50 H V L B F1 "MC10170" -300 -800 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -700 300 -700 P 2 1 0 0 300 -700 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -700 X D0 3 -500 500 200 R 40 40 1 1 I X D1 4 -500 400 200 R 40 40 1 1 I X D2 5 -500 300 200 R 40 40 1 1 I X D3 6 -500 200 200 R 40 40 1 1 I X D4 7 -500 100 200 R 40 40 1 1 I X D5 9 -500 0 200 R 40 40 1 1 I X D6 10 -500 -100 200 R 40 40 1 1 I X D7 11 -500 -200 200 R 40 40 1 1 I X D8 12 -500 -300 200 R 40 40 1 1 I X EVEN 15 500 300 200 L 40 40 1 1 O X HI 13 -500 -500 200 R 40 40 1 1 I X LO 14 -500 -600 200 R 40 40 1 1 I X ODD 2 500 -300 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10171 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10171 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10171 F0 "IC" -300 425 50 H V L B F1 "MC10171" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A 9 -500 100 200 R 40 40 1 1 I X B 7 -500 0 200 R 40 40 1 1 I X E 15 -500 -200 200 R 40 40 1 1 I I X E0 14 -500 300 200 R 40 40 1 1 I I X E1 2 -500 -400 200 R 40 40 1 1 I I X Q00 13 500 300 200 L 40 40 1 1 O X Q01 12 500 200 200 L 40 40 1 1 O X Q02 11 500 100 200 L 40 40 1 1 O X Q03 10 500 0 200 L 40 40 1 1 O X Q10 6 500 -100 200 L 40 40 1 1 O X Q11 5 500 -200 200 L 40 40 1 1 O X Q12 4 500 -300 200 L 40 40 1 1 O X Q13 3 500 -400 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10172 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10172 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10172 F0 "IC" -300 425 50 H V L B F1 "MC10172" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A 9 -500 100 200 R 40 40 1 1 I X B 7 -500 0 200 R 40 40 1 1 I X E 15 -500 -200 200 R 40 40 1 1 I I X E0 14 -500 300 200 R 40 40 1 1 I I X E1 2 -500 -400 200 R 40 40 1 1 I I X Q00 13 500 300 200 L 40 40 1 1 O I X Q01 12 500 200 200 L 40 40 1 1 O I X Q02 11 500 100 200 L 40 40 1 1 O I X Q03 10 500 0 200 L 40 40 1 1 O I X Q10 6 500 -100 200 L 40 40 1 1 O I X Q11 5 500 -200 200 L 40 40 1 1 O I X Q12 4 500 -300 200 L 40 40 1 1 O I X Q13 3 500 -400 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10173 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10173 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10173 F0 "IC" -300 525 50 H V L B F1 "MC10173" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -600 X CLK 7 -500 400 200 R 40 40 1 1 I C X D00 6 -500 200 200 R 40 40 1 1 I X D01 5 -500 100 200 R 40 40 1 1 I X D10 4 -500 0 200 R 40 40 1 1 I X D11 3 -500 -100 200 R 40 40 1 1 I X D20 13 -500 -200 200 R 40 40 1 1 I X D21 12 -500 -300 200 R 40 40 1 1 I X D30 11 -500 -400 200 R 40 40 1 1 I X D31 10 -500 -500 200 R 40 40 1 1 I X Q0 1 500 100 200 L 40 40 1 1 O X Q1 2 500 -100 200 L 40 40 1 1 O X Q2 15 500 -300 200 L 40 40 1 1 O X Q3 14 500 -500 200 L 40 40 1 1 O X SELECT 9 -500 300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: 1VCC1VEE T 1 50 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC 16 0 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10174 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10174 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10174 F0 "IC" -300 625 50 H V L B F1 "MC10174" -300 -700 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -600 300 -600 P 2 1 0 0 300 -600 300 600 P 2 1 0 0 300 600 -300 600 P 2 1 0 0 -300 600 -300 -600 X A 7 -500 100 200 R 40 40 1 1 I X B 9 -500 0 200 R 40 40 1 1 I X D00 3 -500 500 200 R 40 40 1 1 I X D01 5 -500 400 200 R 40 40 1 1 I X D02 4 -500 300 200 R 40 40 1 1 I X D03 6 -500 200 200 R 40 40 1 1 I X D10 13 -500 -100 200 R 40 40 1 1 I X D11 11 -500 -200 200 R 40 40 1 1 I X D12 12 -500 -300 200 R 40 40 1 1 I X D13 10 -500 -400 200 R 40 40 1 1 I X ENABLE 14 -500 -500 200 R 40 40 1 1 I I X Q0 2 500 300 200 L 40 40 1 1 O I X Q1 15 500 -300 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10175 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10175 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10175 F0 "IC" -300 525 50 H V L B F1 "MC10175" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X CLK0 6 -500 -200 200 R 40 40 1 1 I C X CLK1 7 -500 -300 200 R 40 40 1 1 I C X D0 10 -500 400 200 R 40 40 1 1 I X D1 12 -500 300 200 R 40 40 1 1 I X D2 13 -500 200 200 R 40 40 1 1 I X D3 9 -500 100 200 R 40 40 1 1 I X D4 5 -500 0 200 R 40 40 1 1 I X Q0 14 500 400 200 L 40 40 1 1 O X Q1 15 500 300 200 L 40 40 1 1 O X Q2 2 500 200 200 L 40 40 1 1 O X Q3 3 500 100 200 L 40 40 1 1 O X Q4 4 500 0 200 L 40 40 1 1 O X RESET 11 -500 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10176 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10176 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10176 F0 "IC" -300 425 50 H V L B F1 "MC10176" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X CLK 9 -500 -400 200 R 40 40 1 1 I C X D0 5 -500 300 200 R 40 40 1 1 I X D1 6 -500 200 200 R 40 40 1 1 I X D2 7 -500 100 200 R 40 40 1 1 I X D3 10 -500 0 200 R 40 40 1 1 I X D4 11 -500 -100 200 R 40 40 1 1 I X D5 12 -500 -200 200 R 40 40 1 1 I X Q0 2 500 300 200 L 40 40 1 1 O X Q1 3 500 200 200 L 40 40 1 1 O X Q2 4 500 100 200 L 40 40 1 1 O X Q3 13 500 0 200 L 40 40 1 1 O X Q4 14 500 -100 200 L 40 40 1 1 O X Q5 15 500 -200 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10180 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 4 # DEF MC10180 IC 0 40 Y Y 4 L N # Gate Name: A # Symbol Name: MC10180 F0 "IC" -300 325 50 H V L B F1 "MC10180" -300 -400 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -300 300 -300 P 2 1 0 0 300 -300 300 300 P 2 1 0 0 300 300 -300 300 P 2 1 0 0 -300 300 -300 -300 X A 5 -500 200 200 R 40 40 1 1 I X B 6 -500 100 200 R 40 40 1 1 I X CI 4 -500 0 200 R 40 40 1 1 I X CO 3 500 0 200 L 40 40 1 1 O X S 15 500 200 200 L 40 40 1 1 O X S\ 2 500 100 200 L 40 40 1 1 O # Gate Name: A1 # Symbol Name: SELAB X SELA 7 -200 0 200 R 40 40 2 1 I X SELB 9 -200 -100 200 R 40 40 2 1 I # Gate Name: B # Symbol Name: MC10180 P 2 3 0 0 -300 -300 300 -300 P 2 3 0 0 300 -300 300 300 P 2 3 0 0 300 300 -300 300 P 2 3 0 0 -300 300 -300 -300 X A 11 -500 200 200 R 40 40 3 1 I X B 10 -500 100 200 R 40 40 3 1 I X CI 12 -500 0 200 R 40 40 3 1 I X CO 13 500 0 200 L 40 40 3 1 O X S 14 500 200 200 L 40 40 3 1 O X S\ 1 500 100 200 L 40 40 3 1 O # Gate Name: P # Symbol Name: 1VCC1VEE T 1 50 175 50 0 4 0 VCC T 1 50 -155 50 0 4 0 VEE X VCC 16 0 300 200 D 40 40 4 1 W X VEE 8 0 -300 200 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: MC10186 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10186 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10186 F0 "IC" -300 525 50 H V L B F1 "MC10186" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 500 P 2 1 0 0 300 500 -300 500 P 2 1 0 0 -300 500 -300 -500 X CLK 9 -500 400 200 R 40 40 1 1 I C X D0 5 -500 100 200 R 40 40 1 1 I X D1 6 -500 0 200 R 40 40 1 1 I X D2 7 -500 -100 200 R 40 40 1 1 I X D3 10 -500 -200 200 R 40 40 1 1 I X D4 11 -500 -300 200 R 40 40 1 1 I X D5 12 -500 -400 200 R 40 40 1 1 I X Q0 2 500 100 200 L 40 40 1 1 O X Q1 3 500 0 200 L 40 40 1 1 O X Q2 4 500 -100 200 L 40 40 1 1 O X Q3 13 500 -200 200 L 40 40 1 1 O X Q4 14 500 -300 200 L 40 40 1 1 O X Q5 15 500 -400 200 L 40 40 1 1 O X RESET 1 -500 300 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: 1VCC1VEE T 1 50 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC 16 0 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10188 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10188 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10188 F0 "IC" -300 425 50 H V L B F1 "MC10188" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X AI 5 -500 300 200 R 40 40 1 1 I X AO 2 500 300 200 L 40 40 1 1 O X BI 6 -500 200 200 R 40 40 1 1 I X BO 3 500 200 200 L 40 40 1 1 O X CI 7 -500 100 200 R 40 40 1 1 I X CO 4 500 100 200 L 40 40 1 1 O X DI 10 -500 0 200 R 40 40 1 1 I X DO 13 500 0 200 L 40 40 1 1 O X EI 11 -500 -100 200 R 40 40 1 1 I X ENABLE 9 -500 -400 200 R 40 40 1 1 I I X EO 14 500 -100 200 L 40 40 1 1 O X FI 12 -500 -200 200 R 40 40 1 1 I X FO 15 500 -200 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10189 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10189 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10189 F0 "IC" -300 425 50 H V L B F1 "MC10189" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X AI 5 -500 300 200 R 40 40 1 1 I X AO 2 500 300 200 L 40 40 1 1 O I X BI 6 -500 200 200 R 40 40 1 1 I X BO 3 500 200 200 L 40 40 1 1 O I X CI 7 -500 100 200 R 40 40 1 1 I X CO 4 500 100 200 L 40 40 1 1 O I X DI 10 -500 0 200 R 40 40 1 1 I X DO 13 500 0 200 L 40 40 1 1 O I X EI 11 -500 -100 200 R 40 40 1 1 I X ENABLE 9 -500 -400 200 R 40 40 1 1 I X EO 14 500 -100 200 L 40 40 1 1 O I X FI 12 -500 -200 200 R 40 40 1 1 I X FO 15 500 -200 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MC10195 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF MC10195 IC 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: MC10195 F0 "IC" -300 425 50 H V L B F1 "MC10195" -300 -600 50 H V L B F2 "ecl-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 -300 -500 300 -500 P 2 1 0 0 300 -500 300 400 P 2 1 0 0 300 400 -300 400 P 2 1 0 0 -300 400 -300 -500 X A 9 -500 -400 200 R 40 40 1 1 I X B1 5 -500 300 200 R 40 40 1 1 I X B2 6 -500 200 200 R 40 40 1 1 I X B3 7 -500 100 200 R 40 40 1 1 I X B4 10 -500 0 200 R 40 40 1 1 I X B5 11 -500 -100 200 R 40 40 1 1 I X B6 12 -500 -200 200 R 40 40 1 1 I X Q1 2 500 300 200 L 40 40 1 1 O I X Q2 3 500 200 200 L 40 40 1 1 O I X Q3 4 500 100 200 L 40 40 1 1 O I X Q4 13 500 0 200 L 40 40 1 1 O I X Q5 14 500 -100 200 L 40 40 1 1 O I X Q6 15 500 -200 200 L 40 40 1 1 O I # Gate Name: P # Symbol Name: 2VCC1VEE T 1 150 175 50 0 2 0 VCC T 1 50 -155 50 0 2 0 VEE X VCC@1 1 0 300 200 D 40 40 2 1 W X VCC@2 16 100 300 200 D 40 40 2 1 W X VEE 8 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF #End Library