EESchema-LIBRARY Version 2.3 29/04/2008-12:22:20 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 8 # # Dev Name: FT232BL # Package Name: LQFP32 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF FT232BL IC 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: FT232BL F0 "IC" -200 -50 50 H V L B F1 "FT232BL" -300 -200 50 H V L B F2 "ftdichip-2-LQFP32" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1000 600 1000 P 2 1 0 0 600 1000 600 -1100 P 2 1 0 0 600 -1100 -600 -1100 P 2 1 0 0 -600 -1100 -600 1000 X 3V3OUT 6 -800 700 200 R 40 40 1 1 O X AGND 29 -800 -1000 200 R 40 40 1 1 W X AVCC 30 -800 900 200 R 40 40 1 1 W X EECS 32 -800 -500 200 R 40 40 1 1 B X EEDATA 2 -800 -700 200 R 40 40 1 1 B X EESK 1 -800 -600 200 R 40 40 1 1 O X GND@1 17 -100 -1300 200 U 40 40 1 1 W X GND@2 9 -200 -1300 200 U 40 40 1 1 W X PWRCTL 14 800 -700 200 L 40 40 1 1 I X RXD 24 800 800 200 L 40 40 1 1 I X TEST 31 -800 -900 200 R 40 40 1 1 I X TXD 25 800 900 200 L 40 40 1 1 O X TXDEN 16 800 0 200 L 40 40 1 1 O X USBDM 8 -800 500 200 R 40 40 1 1 B X USBDP 7 -800 400 200 R 40 40 1 1 B X VCC@1 3 0 1200 200 D 40 40 1 1 W X VCC@2 26 -100 1200 200 D 40 40 1 1 W X VCCIO 13 -800 800 200 R 40 40 1 1 W X XTIN 27 -800 -100 200 R 40 40 1 1 I X XTOUT 28 -800 -300 200 R 40 40 1 1 O X _CTS 22 800 600 200 L 40 40 1 1 I X _DCD 19 800 300 200 L 40 40 1 1 I X _DSR 20 800 400 200 L 40 40 1 1 I X _DTR 21 800 500 200 L 40 40 1 1 O X _PWREN 15 800 -900 200 L 40 40 1 1 O X _RESET 4 -800 100 200 R 40 40 1 1 I X _RI 18 800 200 200 L 40 40 1 1 I X _RSTOUT 5 -800 200 200 R 40 40 1 1 O X _RTS 23 800 700 200 L 40 40 1 1 O X _RXLED 11 800 -500 200 L 40 40 1 1 C X _SLEEP 10 800 -1000 200 L 40 40 1 1 O X _TXLED 12 800 -400 200 L 40 40 1 1 C ENDDRAW ENDDEF # # Dev Name: FT232RL # Package Name: SSOP28DB # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF FT232RL IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: FT232R F0 "IC" -600 1050 50 H V L B F1 "FT232RL" 0 0 50 H V L B F2 "ftdichip-2-SSOP28DB" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -1100 P 2 1 0 0 700 -1100 -700 -1100 P 2 1 0 0 -700 -1100 -700 1000 X 3V3OUT 17 -900 900 200 R 40 40 1 1 O X AGND 25 -300 -1300 200 U 40 40 1 1 W X CBUS0 23 900 -200 200 L 40 40 1 1 B X CBUS1 22 900 -400 200 L 40 40 1 1 B X CBUS2 13 900 -600 200 L 40 40 1 1 B X CBUS3 14 900 -800 200 L 40 40 1 1 B X CBUS4 12 900 -1000 200 L 40 40 1 1 B X GND1 7 -100 -1300 200 U 40 40 1 1 W X GND2 18 100 -1300 200 U 40 40 1 1 W X GND3 21 300 -1300 200 U 40 40 1 1 W X OSCI 27 -900 -200 200 R 40 40 1 1 I X OSCO 28 -900 -600 200 R 40 40 1 1 O X RXD 5 900 800 200 L 40 40 1 1 I X TEST 26 -900 -900 200 R 40 40 1 1 I X TXD 1 900 900 200 L 40 40 1 1 O X USBDM 16 -900 700 200 R 40 40 1 1 B X USBDP 15 -900 400 200 R 40 40 1 1 B X VCC 20 100 1200 200 D 40 40 1 1 W X VCCIO 4 -100 1200 200 D 40 40 1 1 W X _CTS 11 900 600 200 L 40 40 1 1 I X _DCD 10 900 300 200 L 40 40 1 1 I X _DSR 9 900 400 200 L 40 40 1 1 I X _DTR 2 900 500 200 L 40 40 1 1 O X _RESET 19 -900 100 200 R 40 40 1 1 I X _RI 6 900 200 200 L 40 40 1 1 I X _RTS 3 900 700 200 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: FT232RQ # Package Name: MLF32 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF FT232RQ IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: FT232R F0 "IC" -600 1050 50 H V L B F1 "FT232RQ" 0 0 50 H V L B F2 "ftdichip-2-MLF32" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -1100 P 2 1 0 0 700 -1100 -700 -1100 P 2 1 0 0 -700 -1100 -700 1000 X 3V3OUT 16 -900 900 200 R 40 40 1 1 O X AGND 24 -300 -1300 200 U 40 40 1 1 W X CBUS0 22 900 -200 200 L 40 40 1 1 B X CBUS1 21 900 -400 200 L 40 40 1 1 B X CBUS2 10 900 -600 200 L 40 40 1 1 B X CBUS3 11 900 -800 200 L 40 40 1 1 B X CBUS4 9 900 -1000 200 L 40 40 1 1 B X GND1 4 -100 -1300 200 U 40 40 1 1 W X GND2 17 100 -1300 200 U 40 40 1 1 W X GND3 20 300 -1300 200 U 40 40 1 1 W X OSCI 27 -900 -200 200 R 40 40 1 1 I X OSCO 28 -900 -600 200 R 40 40 1 1 O X RXD 2 900 800 200 L 40 40 1 1 I X TEST 26 -900 -900 200 R 40 40 1 1 I X TXD 30 900 900 200 L 40 40 1 1 O X USBDM 15 -900 700 200 R 40 40 1 1 B X USBDP 14 -900 400 200 R 40 40 1 1 B X VCC 19 100 1200 200 D 40 40 1 1 W X VCCIO 1 -100 1200 200 D 40 40 1 1 W X _CTS 8 900 600 200 L 40 40 1 1 I X _DCD 7 900 300 200 L 40 40 1 1 I X _DSR 6 900 400 200 L 40 40 1 1 I X _DTR 31 900 500 200 L 40 40 1 1 O X _RESET 18 -900 100 200 R 40 40 1 1 I X _RI 3 900 200 200 L 40 40 1 1 I X _RTS 32 900 700 200 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: FT245BL # Package Name: LQFP32 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF FT245BL IC 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: FT245BL F0 "IC" -200 -150 50 H V L B F1 "FT245BL" -410 -430 50 H V L B F2 "ftdichip-2-LQFP32" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1000 600 1000 P 2 1 0 0 600 1000 600 -1100 P 2 1 0 0 600 -1100 -600 -1100 P 2 1 0 0 -600 -1100 -600 1000 X 3V3OUT 6 -800 700 200 R 40 40 1 1 O X AGND 29 -800 -1000 200 R 40 40 1 1 W X AVCC 30 -800 900 200 R 40 40 1 1 W X D0 25 800 900 200 L 40 40 1 1 B X D1 24 800 800 200 L 40 40 1 1 B X D2 23 800 700 200 L 40 40 1 1 B X D3 22 800 600 200 L 40 40 1 1 B X D4 21 800 500 200 L 40 40 1 1 B X D5 20 800 400 200 L 40 40 1 1 B X D6 19 800 300 200 L 40 40 1 1 B X D7 18 800 200 200 L 40 40 1 1 B X EECS 32 -800 -500 200 R 40 40 1 1 B X EEDATA 2 -800 -700 200 R 40 40 1 1 B X EESK 1 -800 -600 200 R 40 40 1 1 O X GND@1 17 -200 -1300 200 U 40 40 1 1 W X GND@2 9 -100 -1300 200 U 40 40 1 1 W X SI/WU 11 800 -1000 200 L 40 40 1 1 I X TEST 31 -800 -900 200 R 40 40 1 1 I X USBDM 8 -800 500 200 R 40 40 1 1 B X USBDP 7 -800 400 200 R 40 40 1 1 B X VCC@1 3 0 1200 200 D 40 40 1 1 W X VCC@2 26 -100 1200 200 D 40 40 1 1 W X VCCIO 13 -800 800 200 R 40 40 1 1 W X WR 15 800 -100 200 L 40 40 1 1 I X XTIN 27 -800 -100 200 R 40 40 1 1 I X XTOUT 28 -800 -300 200 R 40 40 1 1 O X _PWREN 10 800 -900 200 L 40 40 1 1 O X _RD 16 800 0 200 L 40 40 1 1 I X _RESET 4 -800 100 200 R 40 40 1 1 I X _RSTOUT 5 -800 200 200 R 40 40 1 1 O X _RXF 12 800 -300 200 L 40 40 1 1 O X _TXE 14 800 -200 200 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: FT245RL # Package Name: SSOP28DB # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF FT245RL IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: FT245R F0 "IC" -600 1050 50 H V L B F1 "FT245RL" 0 0 50 H V L B F2 "ftdichip-2-SSOP28DB" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -1100 P 2 1 0 0 700 -1100 -700 -1100 P 2 1 0 0 -700 -1100 -700 1000 X 3V3OUT 17 -900 900 200 R 40 40 1 1 O X AGND 25 -300 -1300 200 U 40 40 1 1 W X D0 1 900 900 200 L 40 40 1 1 O X D1 5 900 800 200 L 40 40 1 1 I X D2 3 900 700 200 L 40 40 1 1 O X D3 11 900 600 200 L 40 40 1 1 I X D4 2 900 500 200 L 40 40 1 1 O X D5 9 900 400 200 L 40 40 1 1 I X D6 10 900 300 200 L 40 40 1 1 I X D7 6 900 200 200 L 40 40 1 1 I X GND1 7 -100 -1300 200 U 40 40 1 1 W X GND2 18 100 -1300 200 U 40 40 1 1 W X GND3 21 300 -1300 200 U 40 40 1 1 W X OSCI 27 -900 -200 200 R 40 40 1 1 I X OSCO 28 -900 -600 200 R 40 40 1 1 O X PWEN 12 900 -1000 200 L 40 40 1 1 B X TEST 26 -900 -900 200 R 40 40 1 1 I X USBDM 16 -900 700 200 R 40 40 1 1 B X USBDP 15 -900 400 200 R 40 40 1 1 B X VCC 20 100 1200 200 D 40 40 1 1 W X VCCIO 4 -100 1200 200 D 40 40 1 1 W X WR 14 900 -800 200 L 40 40 1 1 B X _RD 13 900 -600 200 L 40 40 1 1 B X _RESET 19 -900 100 200 R 40 40 1 1 I X _RXF 23 900 -200 200 L 40 40 1 1 B X _TXE 22 900 -400 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: FT245RQ # Package Name: MLF32 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF FT245RQ IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: FT245R F0 "IC" -600 1050 50 H V L B F1 "FT245RQ" 0 0 50 H V L B F2 "ftdichip-2-MLF32" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -1100 P 2 1 0 0 700 -1100 -700 -1100 P 2 1 0 0 -700 -1100 -700 1000 X 3V3OUT 16 -900 900 200 R 40 40 1 1 O X AGND 24 -300 -1300 200 U 40 40 1 1 W X D0 30 900 900 200 L 40 40 1 1 O X D1 2 900 800 200 L 40 40 1 1 I X D2 32 900 700 200 L 40 40 1 1 O X D3 8 900 600 200 L 40 40 1 1 I X D4 31 900 500 200 L 40 40 1 1 O X D5 6 900 400 200 L 40 40 1 1 I X D6 7 900 300 200 L 40 40 1 1 I X D7 3 900 200 200 L 40 40 1 1 I X GND1 4 -100 -1300 200 U 40 40 1 1 W X GND2 17 100 -1300 200 U 40 40 1 1 W X GND3 20 300 -1300 200 U 40 40 1 1 W X OSCI 27 -900 -200 200 R 40 40 1 1 I X OSCO 28 -900 -600 200 R 40 40 1 1 O X PWEN 9 900 -1000 200 L 40 40 1 1 B X TEST 26 -900 -900 200 R 40 40 1 1 I X USBDM 15 -900 700 200 R 40 40 1 1 B X USBDP 14 -900 400 200 R 40 40 1 1 B X VCC 19 100 1200 200 D 40 40 1 1 W X VCCIO 1 -100 1200 200 D 40 40 1 1 W X WR 11 900 -800 200 L 40 40 1 1 B X _RD 10 900 -600 200 L 40 40 1 1 B X _RESET 18 -900 100 200 R 40 40 1 1 I X _RXF 22 900 -200 200 L 40 40 1 1 B X _TXE 21 900 -400 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: FT2232L # Package Name: LQFP48 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF FT2232L IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: FT2232C F0 "IC" 0 0 50 H V C C F1 "FT2232L" 0 0 50 H V C C F2 "ftdichip-2-LQFP48" 0 150 50 H I C C DRAW P 2 1 0 0 800 1500 -800 1500 P 2 1 0 0 -800 1500 -800 -1600 P 2 1 0 0 -800 -1600 800 -1600 P 2 1 0 0 800 -1600 800 1500 X 3V3OUT 6 -1000 1100 200 R 40 40 1 1 B X ACBUS0 15 1000 500 200 L 40 40 1 1 B X ACBUS1 13 1000 400 200 L 40 40 1 1 B X ACBUS2 12 1000 300 200 L 40 40 1 1 B X ACBUS3 11 1000 200 200 L 40 40 1 1 B X ADBUS0 24 1000 1400 200 L 40 40 1 1 B X ADBUS1 23 1000 1300 200 L 40 40 1 1 B X ADBUS2 22 1000 1200 200 L 40 40 1 1 B X ADBUS3 21 1000 1100 200 L 40 40 1 1 B X ADBUS4 20 1000 1000 200 L 40 40 1 1 B X ADBUS5 19 1000 900 200 L 40 40 1 1 B X ADBUS6 17 1000 800 200 L 40 40 1 1 B X ADBUS7 16 1000 700 200 L 40 40 1 1 B X AGND 45 -300 -1800 200 U 40 40 1 1 B X AVVC 46 -300 1700 200 D 40 40 1 1 B X BCBUS0 30 1000 -1000 200 L 40 40 1 1 B X BCBUS1 29 1000 -1100 200 L 40 40 1 1 B X BCBUS2 28 1000 -1200 200 L 40 40 1 1 B X BCBUS3 27 1000 -1300 200 L 40 40 1 1 B X BDBUS0 40 1000 -100 200 L 40 40 1 1 B X BDBUS1 39 1000 -200 200 L 40 40 1 1 B X BDBUS2 38 1000 -300 200 L 40 40 1 1 B X BDBUS3 37 1000 -400 200 L 40 40 1 1 B X BDBUS4 36 1000 -500 200 L 40 40 1 1 B X BDBUS5 35 1000 -600 200 L 40 40 1 1 B X BDBUS6 33 1000 -700 200 L 40 40 1 1 B X BDBUS7 32 1000 -800 200 L 40 40 1 1 B X EECS 48 -1000 -700 200 R 40 40 1 1 B X EEDATA 2 -1000 -900 200 R 40 40 1 1 B X EESK 1 -1000 -800 200 R 40 40 1 1 B X GND0 9 200 -1800 200 U 40 40 1 1 B X GND1 18 100 -1800 200 U 40 40 1 1 B X GND2 25 0 -1800 200 U 40 40 1 1 B X GND3 34 -100 -1800 200 U 40 40 1 1 B X PWREN# 41 1000 -1500 200 L 40 40 1 1 B X RESET# 4 -1000 0 200 R 40 40 1 1 B X RSTOUT# 5 -1000 200 200 R 40 40 1 1 B X SI/WUA 10 1000 100 200 L 40 40 1 1 B X SI/WUB 26 1000 -1400 200 L 40 40 1 1 B X TEST 47 -1000 -1000 200 R 40 40 1 1 B X USBDM 8 -1000 800 200 R 40 40 1 1 B X USBDP 7 -1000 500 200 R 40 40 1 1 B X VCC0 3 -100 1700 200 D 40 40 1 1 B X VCC1 42 0 1700 200 D 40 40 1 1 B X VCCIOA 14 100 1700 200 D 40 40 1 1 B X VCCIOB 31 200 1700 200 D 40 40 1 1 B X XTIN 43 -1000 -300 200 R 40 40 1 1 B X XTOUT 44 -1000 -600 200 R 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: VNC1L-1A # Package Name: LQFP48 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF VNC1L-1A IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: VNC1L F0 "IC" 200 -1900 50 H V L B F1 "VNC1L-1A" 200 1500 50 H V L B F2 "ftdichip-2-LQFP48" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1800 P 2 1 0 0 600 -1800 -600 -1800 P 2 1 0 0 -600 -1800 -600 1400 X ACBUS0 41 800 400 200 L 40 40 1 1 B X ACBUS1 42 800 300 200 L 40 40 1 1 B X ACBUS2 43 800 200 200 L 40 40 1 1 B X ACBUS3 44 800 100 200 L 40 40 1 1 B X ACBUS4 45 800 0 200 L 40 40 1 1 B X ACBUS5 46 800 -100 200 L 40 40 1 1 B X ACBUS6 47 800 -200 200 L 40 40 1 1 B X ACBUS7 48 800 -300 200 L 40 40 1 1 B X ADBUS0 31 800 1300 200 L 40 40 1 1 B X ADBUS1 32 800 1200 200 L 40 40 1 1 B X ADBUS2 33 800 1100 200 L 40 40 1 1 B X ADBUS3 34 800 1000 200 L 40 40 1 1 B X ADBUS4 35 800 900 200 L 40 40 1 1 B X ADBUS5 36 800 800 200 L 40 40 1 1 B X ADBUS6 37 800 700 200 L 40 40 1 1 B X ADBUS7 38 800 600 200 L 40 40 1 1 B X AGND 6 -500 -2000 200 U 40 40 1 1 W X AVCC 3 0 1600 200 D 40 40 1 1 W X BCBUS0 20 800 -1400 200 L 40 40 1 1 B X BCBUS1 21 800 -1500 200 L 40 40 1 1 B X BCBUS2 22 800 -1600 200 L 40 40 1 1 B X BCBUS3 23 800 -1700 200 L 40 40 1 1 B X BDBUS0 11 800 -500 200 L 40 40 1 1 B X BDBUS1 12 800 -600 200 L 40 40 1 1 B X BDBUS2 13 800 -700 200 L 40 40 1 1 B X BDBUS3 14 800 -800 200 L 40 40 1 1 B X BDBUS4 15 800 -900 200 L 40 40 1 1 B X BDBUS5 16 800 -1000 200 L 40 40 1 1 B X BDBUS6 18 800 -1100 200 L 40 40 1 1 B X BDBUS7 19 800 -1200 200 L 40 40 1 1 B X GND 1 -300 -2000 200 U 40 40 1 1 W X GND1 24 -200 -2000 200 U 40 40 1 1 W X GND2 27 -100 -2000 200 U 40 40 1 1 W X GND3 39 0 -2000 200 U 40 40 1 1 W X PLLFLTR 7 -800 -800 200 R 40 40 1 1 I X PROG# 10 -800 -500 200 R 40 40 1 1 I I X RESET# 9 -800 -300 200 R 40 40 1 1 I I X TEST 8 -800 -1000 200 R 40 40 1 1 I X USB1DM 26 -800 800 200 R 40 40 1 1 B X USB1DP 25 -800 700 200 R 40 40 1 1 B X USB2DM 29 -800 600 200 R 40 40 1 1 B X USB2DP 28 -800 500 200 R 40 40 1 1 B X VCC 2 -100 1600 200 D 40 40 1 1 W X VCCIO 17 -500 1600 200 D 40 40 1 1 W X VCCIO1 30 -400 1600 200 D 40 40 1 1 W X VCCIO2 40 -300 1600 200 D 40 40 1 1 W X XTIN 4 -800 200 200 R 40 40 1 1 I X XTOUT 5 -800 0 200 R 40 40 1 1 O ENDDRAW ENDDEF #End Library