EESchema-LIBRARY Version 2.3  29/04/2008-12:22:25
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 106
#
# Dev Name: ISD5102E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5102E IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5102E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 1 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 28 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 27 800 -800 100 L 40 40 4 1 O 
X A0 11 -800 600 100 R 40 40 4 1 I 
X A1 9 -800 500 100 R 40 40 4 1 I 
X ACAP 20 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 25 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 18 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 19 800 -600 100 L 40 40 4 1 O 
X AUX_IN 26 -800 0 100 R 40 40 4 1 I 
X INT 4 800 700 100 L 40 40 4 1 O I
X MIC+ 16 -800 -200 100 R 40 40 4 1 I 
X MIC- 17 -800 -400 100 R 40 40 4 1 I 
X RAC 3 800 800 100 L 40 40 4 1 O 
X SCL 8 -800 800 100 R 40 40 4 1 I C
X SDA 10 -800 700 100 R 40 40 4 1 I 
X SP+ 23 800 -1000 100 L 40 40 4 1 O 
X SP- 21 800 -1200 100 L 40 40 4 1 O 
X VCCA 24 800 300 100 L 40 40 4 1 O 
X VCCD@1 6 800 500 100 L 40 40 4 1 O 
X VCCD@2 7 800 400 100 L 40 40 4 1 O 
X VSSA@1 2 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 22 800 -100 100 L 40 40 4 1 O 
X VSSD@1 12 800 -200 100 L 40 40 4 1 O 
X VSSD@2 13 800 -300 100 L 40 40 4 1 O 
X XCLK 5 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5102S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5102S IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5102S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 7 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 21 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 22 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 20 800 -800 100 L 40 40 4 1 O 
X A0 4 -800 600 100 R 40 40 4 1 I 
X A1 2 -800 500 100 R 40 40 4 1 I 
X ACAP 13 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 18 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 11 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 12 800 -600 100 L 40 40 4 1 O 
X AUX_IN 19 -800 0 100 R 40 40 4 1 I 
X INT 25 800 700 100 L 40 40 4 1 O I
X MIC+ 8 -800 -200 100 R 40 40 4 1 I 
X MIC- 10 -800 -400 100 R 40 40 4 1 I 
X RAC 24 800 800 100 L 40 40 4 1 O 
X SCL 1 -800 800 100 R 40 40 4 1 I C
X SDA 3 -800 700 100 R 40 40 4 1 I 
X SP+ 16 800 -1000 100 L 40 40 4 1 O 
X SP- 14 800 -1200 100 L 40 40 4 1 O 
X VCCA 17 800 300 100 L 40 40 4 1 O 
X VCCD@1 27 800 500 100 L 40 40 4 1 O 
X VCCD@2 28 800 400 100 L 40 40 4 1 O 
X VSSA@1 9 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 23 800 -100 100 L 40 40 4 1 O 
X VSSD@1 5 800 -200 100 L 40 40 4 1 O 
X VSSD@2 6 800 -300 100 L 40 40 4 1 O 
X XCLK 26 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5104E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5104E IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5104E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 1 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 28 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 27 800 -800 100 L 40 40 4 1 O 
X A0 11 -800 600 100 R 40 40 4 1 I 
X A1 9 -800 500 100 R 40 40 4 1 I 
X ACAP 20 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 25 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 18 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 19 800 -600 100 L 40 40 4 1 O 
X AUX_IN 26 -800 0 100 R 40 40 4 1 I 
X INT 4 800 700 100 L 40 40 4 1 O I
X MIC+ 16 -800 -200 100 R 40 40 4 1 I 
X MIC- 17 -800 -400 100 R 40 40 4 1 I 
X RAC 3 800 800 100 L 40 40 4 1 O 
X SCL 8 -800 800 100 R 40 40 4 1 I C
X SDA 10 -800 700 100 R 40 40 4 1 I 
X SP+ 23 800 -1000 100 L 40 40 4 1 O 
X SP- 21 800 -1200 100 L 40 40 4 1 O 
X VCCA 24 800 300 100 L 40 40 4 1 O 
X VCCD@1 6 800 500 100 L 40 40 4 1 O 
X VCCD@2 7 800 400 100 L 40 40 4 1 O 
X VSSA@1 2 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 22 800 -100 100 L 40 40 4 1 O 
X VSSD@1 12 800 -200 100 L 40 40 4 1 O 
X VSSD@2 13 800 -300 100 L 40 40 4 1 O 
X XCLK 5 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5104S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5104S IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5104S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 7 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 21 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 22 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 20 800 -800 100 L 40 40 4 1 O 
X A0 4 -800 600 100 R 40 40 4 1 I 
X A1 2 -800 500 100 R 40 40 4 1 I 
X ACAP 13 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 18 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 11 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 12 800 -600 100 L 40 40 4 1 O 
X AUX_IN 19 -800 0 100 R 40 40 4 1 I 
X INT 25 800 700 100 L 40 40 4 1 O I
X MIC+ 8 -800 -200 100 R 40 40 4 1 I 
X MIC- 10 -800 -400 100 R 40 40 4 1 I 
X RAC 24 800 800 100 L 40 40 4 1 O 
X SCL 1 -800 800 100 R 40 40 4 1 I C
X SDA 3 -800 700 100 R 40 40 4 1 I 
X SP+ 16 800 -1000 100 L 40 40 4 1 O 
X SP- 14 800 -1200 100 L 40 40 4 1 O 
X VCCA 17 800 300 100 L 40 40 4 1 O 
X VCCD@1 27 800 500 100 L 40 40 4 1 O 
X VCCD@2 28 800 400 100 L 40 40 4 1 O 
X VSSA@1 9 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 23 800 -100 100 L 40 40 4 1 O 
X VSSD@1 5 800 -200 100 L 40 40 4 1 O 
X VSSD@2 6 800 -300 100 L 40 40 4 1 O 
X XCLK 26 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5108E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5108E IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5108E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 1 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 28 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 27 800 -800 100 L 40 40 4 1 O 
X A0 11 -800 600 100 R 40 40 4 1 I 
X A1 9 -800 500 100 R 40 40 4 1 I 
X ACAP 20 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 25 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 18 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 19 800 -600 100 L 40 40 4 1 O 
X AUX_IN 26 -800 0 100 R 40 40 4 1 I 
X INT 4 800 700 100 L 40 40 4 1 O I
X MIC+ 16 -800 -200 100 R 40 40 4 1 I 
X MIC- 17 -800 -400 100 R 40 40 4 1 I 
X RAC 3 800 800 100 L 40 40 4 1 O 
X SCL 8 -800 800 100 R 40 40 4 1 I C
X SDA 10 -800 700 100 R 40 40 4 1 I 
X SP+ 23 800 -1000 100 L 40 40 4 1 O 
X SP- 21 800 -1200 100 L 40 40 4 1 O 
X VCCA 24 800 300 100 L 40 40 4 1 O 
X VCCD@1 6 800 500 100 L 40 40 4 1 O 
X VCCD@2 7 800 400 100 L 40 40 4 1 O 
X VSSA@1 2 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 22 800 -100 100 L 40 40 4 1 O 
X VSSD@1 12 800 -200 100 L 40 40 4 1 O 
X VSSD@2 13 800 -300 100 L 40 40 4 1 O 
X XCLK 5 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5108S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5108S IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5108S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 7 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 21 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 22 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 20 800 -800 100 L 40 40 4 1 O 
X A0 4 -800 600 100 R 40 40 4 1 I 
X A1 2 -800 500 100 R 40 40 4 1 I 
X ACAP 13 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 18 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 11 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 12 800 -600 100 L 40 40 4 1 O 
X AUX_IN 19 -800 0 100 R 40 40 4 1 I 
X INT 25 800 700 100 L 40 40 4 1 O I
X MIC+ 8 -800 -200 100 R 40 40 4 1 I 
X MIC- 10 -800 -400 100 R 40 40 4 1 I 
X RAC 24 800 800 100 L 40 40 4 1 O 
X SCL 1 -800 800 100 R 40 40 4 1 I C
X SDA 3 -800 700 100 R 40 40 4 1 I 
X SP+ 16 800 -1000 100 L 40 40 4 1 O 
X SP- 14 800 -1200 100 L 40 40 4 1 O 
X VCCA 17 800 300 100 L 40 40 4 1 O 
X VCCD@1 27 800 500 100 L 40 40 4 1 O 
X VCCD@2 28 800 400 100 L 40 40 4 1 O 
X VSSA@1 9 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 23 800 -100 100 L 40 40 4 1 O 
X VSSD@1 5 800 -200 100 L 40 40 4 1 O 
X VSSD@2 6 800 -300 100 L 40 40 4 1 O 
X XCLK 26 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5116E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5116E IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5116E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 1 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 28 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 27 800 -800 100 L 40 40 4 1 O 
X A0 11 -800 600 100 R 40 40 4 1 I 
X A1 9 -800 500 100 R 40 40 4 1 I 
X ACAP 20 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 25 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 18 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 19 800 -600 100 L 40 40 4 1 O 
X AUX_IN 26 -800 0 100 R 40 40 4 1 I 
X INT 4 800 700 100 L 40 40 4 1 O I
X MIC+ 16 -800 -200 100 R 40 40 4 1 I 
X MIC- 17 -800 -400 100 R 40 40 4 1 I 
X RAC 3 800 800 100 L 40 40 4 1 O 
X SCL 8 -800 800 100 R 40 40 4 1 I C
X SDA 10 -800 700 100 R 40 40 4 1 I 
X SP+ 23 800 -1000 100 L 40 40 4 1 O 
X SP- 21 800 -1200 100 L 40 40 4 1 O 
X VCCA 24 800 300 100 L 40 40 4 1 O 
X VCCD@1 6 800 500 100 L 40 40 4 1 O 
X VCCD@2 7 800 400 100 L 40 40 4 1 O 
X VSSA@1 2 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 22 800 -100 100 L 40 40 4 1 O 
X VSSD@1 12 800 -200 100 L 40 40 4 1 O 
X VSSD@2 13 800 -300 100 L 40 40 4 1 O 
X XCLK 5 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5116P
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5116P IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5116P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 7 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 21 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 22 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 20 800 -800 100 L 40 40 4 1 O 
X A0 4 -800 600 100 R 40 40 4 1 I 
X A1 2 -800 500 100 R 40 40 4 1 I 
X ACAP 13 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 18 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 11 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 12 800 -600 100 L 40 40 4 1 O 
X AUX_IN 19 -800 0 100 R 40 40 4 1 I 
X INT 25 800 700 100 L 40 40 4 1 O I
X MIC+ 8 -800 -200 100 R 40 40 4 1 I 
X MIC- 10 -800 -400 100 R 40 40 4 1 I 
X RAC 24 800 800 100 L 40 40 4 1 O 
X SCL 1 -800 800 100 R 40 40 4 1 I C
X SDA 3 -800 700 100 R 40 40 4 1 I 
X SP+ 16 800 -1000 100 L 40 40 4 1 O 
X SP- 14 800 -1200 100 L 40 40 4 1 O 
X VCCA 17 800 300 100 L 40 40 4 1 O 
X VCCD@1 27 800 500 100 L 40 40 4 1 O 
X VCCD@2 28 800 400 100 L 40 40 4 1 O 
X VSSA@1 9 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 23 800 -100 100 L 40 40 4 1 O 
X VSSD@1 5 800 -200 100 L 40 40 4 1 O 
X VSSD@2 6 800 -300 100 L 40 40 4 1 O 
X XCLK 26 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD5116S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 4
#
DEF ISD5116S IC 0 40 Y Y 4 L N
# Gate Name: G$2
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD5116S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 7 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 21 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 22 -100 0 100 R 40 40 3 1 U 
# Gate Name: IC
# Symbol Name: ISD5100
P 2 4 0 0 -700 900 -700 -1300
P 2 4 0 0 -700 -1300 700 -1300
P 2 4 0 0 700 -1300 700 900
P 2 4 0 0 700 900 -700 900
P 2 4 0 0 600 750 480 750
X <U>AUX_OUT</U> 20 800 -800 100 L 40 40 4 1 O 
X A0 4 -800 600 100 R 40 40 4 1 I 
X A1 2 -800 500 100 R 40 40 4 1 I 
X ACAP 13 -800 -600 100 R 40 40 4 1 I 
X ANA_IN 18 -800 200 100 R 40 40 4 1 I 
X ANA_OUT+ 11 800 -500 100 L 40 40 4 1 O 
X ANA_OUT- 12 800 -600 100 L 40 40 4 1 O 
X AUX_IN 19 -800 0 100 R 40 40 4 1 I 
X INT 25 800 700 100 L 40 40 4 1 O I
X MIC+ 8 -800 -200 100 R 40 40 4 1 I 
X MIC- 10 -800 -400 100 R 40 40 4 1 I 
X RAC 24 800 800 100 L 40 40 4 1 O 
X SCL 1 -800 800 100 R 40 40 4 1 I C
X SDA 3 -800 700 100 R 40 40 4 1 I 
X SP+ 16 800 -1000 100 L 40 40 4 1 O 
X SP- 14 800 -1200 100 L 40 40 4 1 O 
X VCCA 17 800 300 100 L 40 40 4 1 O 
X VCCD@1 27 800 500 100 L 40 40 4 1 O 
X VCCD@2 28 800 400 100 L 40 40 4 1 O 
X VSSA@1 9 800 100 100 L 40 40 4 1 O 
X VSSA@2 15 800 0 100 L 40 40 4 1 O 
X VSSA@3 23 800 -100 100 L 40 40 4 1 O 
X VSSD@1 5 800 -200 100 L 40 40 4 1 O 
X VSSD@2 6 800 -300 100 L 40 40 4 1 O 
X XCLK 26 -800 -1200 100 R 40 40 4 1 I C
ENDDRAW
ENDDEF

#
# Dev Name: ISD1400D
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 5
#
DEF ISD1400D IC 0 40 Y Y 5 L N
# Gate Name: G$1
# Symbol Name: ISD1400
F0 "IC" -1300 950 50 H V L B
F1 "ISD1400D" -450 950 50 H V L B
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1300 900 -1300 700
P 2 1 0 0 -1300 700 -1300 400
P 2 1 0 0 -1300 400 -1300 200
P 2 1 0 0 -1300 200 -1300 0
P 2 1 0 0 -1300 0 -1300 -200
P 2 1 0 0 -1300 -200 -1300 -400
P 2 1 0 0 -1300 -400 -1300 -900
P 2 1 0 0 -1300 -900 -1200 -900
P 2 1 0 0 -1200 -900 -400 -900
P 2 1 0 0 -400 -900 -300 -900
P 2 1 0 0 -300 -900 600 -900
P 2 1 0 0 600 -900 700 -900
P 2 1 0 0 700 -900 1200 -900
P 2 1 0 0 1200 -900 1300 -900
P 2 1 0 0 1300 -900 1300 100
P 2 1 0 0 1300 100 1300 300
P 2 1 0 0 1300 300 1300 900
P 2 1 0 0 1300 900 -1300 900
P 2 1 0 0 -1300 700 -1000 700
P 2 1 0 0 -1300 400 -900 400
P 2 1 0 0 -900 400 -900 500
P 2 1 0 0 -900 500 -700 400
P 2 1 0 0 -700 400 -900 300
P 2 1 0 0 -900 300 -900 400
P 2 1 0 0 -1300 0 -1100 0
P 2 1 0 0 -1300 -200 -1100 -200
P 2 1 0 0 -1100 100 -1100 -300
P 2 1 0 0 -1100 -300 -900 -200
P 2 1 0 0 -900 -200 -700 -100
P 2 1 0 0 -700 -100 -1100 100
P 2 1 0 0 -700 -100 -670 -100
P 2 1 0 0 -670 -100 -670 200
P 2 1 0 0 -670 200 -1300 200
P 2 1 0 0 -1300 -400 -900 -400
P 2 1 0 0 -900 -400 -800 -400
P 2 1 0 0 -900 -200 -900 -400
P 2 1 0 0 -800 -300 -800 -500
P 2 1 0 0 -800 -500 -500 -500
P 2 1 0 0 -500 -500 -500 -300
P 2 1 0 0 -500 -300 -600 -300
P 2 1 0 0 -600 -300 -800 -300
P 2 1 0 0 -600 -300 -600 400
P 2 1 0 0 -600 400 -700 400
P 2 1 0 0 -600 400 -500 400
P 2 1 0 0 -500 500 -500 300
P 2 1 0 0 -500 300 -300 300
P 2 1 0 0 -300 300 -300 400
P 2 1 0 0 -300 400 -300 500
P 2 1 0 0 -300 500 -500 500
P 2 1 0 0 -1000 800 -1000 600
P 2 1 0 0 -1000 600 -800 600
P 2 1 0 0 -800 600 -800 700
P 2 1 0 0 -800 700 -800 800
P 2 1 0 0 -800 800 -1000 800
P 2 1 0 0 -800 700 -700 700
P 2 1 0 0 -700 800 -700 600
P 2 1 0 0 -700 600 -500 600
P 2 1 0 0 -500 600 -500 700
P 2 1 0 0 -500 700 -500 800
P 2 1 0 0 -500 800 -700 800
P 2 1 0 0 -500 700 -300 700
P 2 1 0 0 -300 800 -300 600
P 2 1 0 0 -300 600 -100 600
P 2 1 0 0 -100 600 -100 700
P 2 1 0 0 -100 700 -100 800
P 2 1 0 0 -100 800 -300 800
P 2 1 0 0 -100 700 100 700
P 2 1 0 0 100 700 100 500
P 2 1 0 0 -200 500 -200 400
P 2 1 0 0 -200 400 -200 300
P 2 1 0 0 -200 300 -200 -100
P 2 1 0 0 -200 -100 -100 -100
P 2 1 0 0 -100 -100 0 -100
P 2 1 0 0 0 -100 400 -100
P 2 1 0 0 400 -100 400 300
P 2 1 0 0 400 300 400 400
P 2 1 0 0 400 400 400 500
P 2 1 0 0 400 500 0 500
P 2 1 0 0 0 500 -200 500
P 2 1 0 0 0 500 0 -100
P 2 1 0 0 -200 300 400 300
P 2 1 0 0 -400 -900 -400 -550
P 2 1 0 0 -400 -550 -1200 -550
P 2 1 0 0 -1200 -550 -1200 -900
P 2 1 0 0 -300 -900 -300 -600
P 2 1 0 0 -300 -600 -100 -600
P 2 1 0 0 -100 -600 600 -600
P 2 1 0 0 600 -600 600 -900
P 2 1 0 0 700 -900 700 -400
P 2 1 0 0 900 300 900 200
P 2 1 0 0 900 200 900 100
P 2 1 0 0 900 100 1000 150
P 2 1 0 0 1000 150 1100 200
P 2 1 0 0 1100 200 1000 250
P 2 1 0 0 1000 250 900 300
P 2 1 0 0 900 200 700 200
P 2 1 0 0 700 300 700 100
P 2 1 0 0 700 100 500 100
P 2 1 0 0 500 100 500 300
P 2 1 0 0 500 300 600 300
P 2 1 0 0 600 300 700 300
P 2 1 0 0 400 400 600 400
P 2 1 0 0 600 400 600 300
P 2 1 0 0 700 -400 1200 -400
P 2 1 0 0 1200 -400 1200 -900
P 2 1 0 0 -300 400 -200 400
P 2 1 0 0 -100 -100 -100 -600
P 2 1 0 0 1000 300 1300 300
P 2 1 0 0 1000 100 1300 100
P 2 1 0 0 1000 300 1000 250
P 2 1 0 0 1000 100 1000 150
P 2 1 0 0 760 -810 760 -650
P 2 1 0 0 860 -810 860 -540
P 2 1 0 0 960 -810 960 -540
P 2 1 0 0 1060 -810 1060 -490
C -900 -400 10 1 1 0 N
C -600 400 10 1 1 0 N
T 0 -1158 748 56 0 1 0 XCLK
T 0 -1102 448 56 0 1 0 ANA_IN
T 0 -1074 248 56 0 1 0 ANA_OUT
T 0 -1186 48 56 0 1 0 MIC
T 0 -1186 -152 56 0 1 0 MIC
T 0 -1186 -262 56 0 1 0 REF
T 0 -1186 -462 56 0 1 0 AGC
T 0 1114 358 56 0 1 0 SP+
T 0 1114 28 56 0 1 0 SP-
X A0 1 -200 -1100 200 U 40 40 1 1 O 
X A1 2 -100 -1100 200 U 40 40 1 1 O 
X A2 3 0 -1100 200 U 40 40 1 1 O 
X A3 4 100 -1100 200 U 40 40 1 1 O 
X A4 5 200 -1100 200 U 40 40 1 1 O 
X A5 6 300 -1100 200 U 40 40 1 1 O 
X A6 9 400 -1100 200 U 40 40 1 1 O 
X A7 10 500 -1100 200 U 40 40 1 1 O 
X AGC 19 -1500 -400 200 R 40 40 1 1 P 
X ANA_IN 20 -1500 400 200 R 40 40 1 1 I 
X ANA_OUT 21 -1500 200 200 R 40 40 1 1 O 
X MIC 17 -1500 0 200 R 40 40 1 1 I 
X MIC_REF 18 -1500 -200 200 R 40 40 1 1 I 
X PLAYE 24 900 -1100 200 U 40 40 1 1 I 
X PLAYL 23 1000 -1100 200 U 40 40 1 1 I 
X REC 27 800 -1100 200 U 40 40 1 1 I 
X RECLED 25 1100 -1100 200 U 40 40 1 1 O 
X SP+ 14 1500 300 200 L 40 40 1 1 O 
X SP- 15 1500 100 200 L 40 40 1 1 O 
X VCCA 16 -1100 -1100 200 U 40 40 1 1 W 
X VCCD 28 -500 -1100 200 U 40 40 1 1 W 
X VSSA 13 -900 -1100 200 U 40 40 1 1 W 
X VSSD 12 -700 -1100 200 U 40 40 1 1 W 
X XCLK 26 -1500 700 200 R 40 40 1 1 I 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 11 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 22 -100 0 100 R 40 40 5 1 U 
ENDDRAW
ENDDEF

#
# Dev Name: ISD1400S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 5
#
DEF ISD1400S IC 0 40 Y Y 5 L N
# Gate Name: G$1
# Symbol Name: ISD1400
F0 "IC" -1300 950 50 H V L B
F1 "ISD1400S" -450 950 50 H V L B
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1300 900 -1300 700
P 2 1 0 0 -1300 700 -1300 400
P 2 1 0 0 -1300 400 -1300 200
P 2 1 0 0 -1300 200 -1300 0
P 2 1 0 0 -1300 0 -1300 -200
P 2 1 0 0 -1300 -200 -1300 -400
P 2 1 0 0 -1300 -400 -1300 -900
P 2 1 0 0 -1300 -900 -1200 -900
P 2 1 0 0 -1200 -900 -400 -900
P 2 1 0 0 -400 -900 -300 -900
P 2 1 0 0 -300 -900 600 -900
P 2 1 0 0 600 -900 700 -900
P 2 1 0 0 700 -900 1200 -900
P 2 1 0 0 1200 -900 1300 -900
P 2 1 0 0 1300 -900 1300 100
P 2 1 0 0 1300 100 1300 300
P 2 1 0 0 1300 300 1300 900
P 2 1 0 0 1300 900 -1300 900
P 2 1 0 0 -1300 700 -1000 700
P 2 1 0 0 -1300 400 -900 400
P 2 1 0 0 -900 400 -900 500
P 2 1 0 0 -900 500 -700 400
P 2 1 0 0 -700 400 -900 300
P 2 1 0 0 -900 300 -900 400
P 2 1 0 0 -1300 0 -1100 0
P 2 1 0 0 -1300 -200 -1100 -200
P 2 1 0 0 -1100 100 -1100 -300
P 2 1 0 0 -1100 -300 -900 -200
P 2 1 0 0 -900 -200 -700 -100
P 2 1 0 0 -700 -100 -1100 100
P 2 1 0 0 -700 -100 -670 -100
P 2 1 0 0 -670 -100 -670 200
P 2 1 0 0 -670 200 -1300 200
P 2 1 0 0 -1300 -400 -900 -400
P 2 1 0 0 -900 -400 -800 -400
P 2 1 0 0 -900 -200 -900 -400
P 2 1 0 0 -800 -300 -800 -500
P 2 1 0 0 -800 -500 -500 -500
P 2 1 0 0 -500 -500 -500 -300
P 2 1 0 0 -500 -300 -600 -300
P 2 1 0 0 -600 -300 -800 -300
P 2 1 0 0 -600 -300 -600 400
P 2 1 0 0 -600 400 -700 400
P 2 1 0 0 -600 400 -500 400
P 2 1 0 0 -500 500 -500 300
P 2 1 0 0 -500 300 -300 300
P 2 1 0 0 -300 300 -300 400
P 2 1 0 0 -300 400 -300 500
P 2 1 0 0 -300 500 -500 500
P 2 1 0 0 -1000 800 -1000 600
P 2 1 0 0 -1000 600 -800 600
P 2 1 0 0 -800 600 -800 700
P 2 1 0 0 -800 700 -800 800
P 2 1 0 0 -800 800 -1000 800
P 2 1 0 0 -800 700 -700 700
P 2 1 0 0 -700 800 -700 600
P 2 1 0 0 -700 600 -500 600
P 2 1 0 0 -500 600 -500 700
P 2 1 0 0 -500 700 -500 800
P 2 1 0 0 -500 800 -700 800
P 2 1 0 0 -500 700 -300 700
P 2 1 0 0 -300 800 -300 600
P 2 1 0 0 -300 600 -100 600
P 2 1 0 0 -100 600 -100 700
P 2 1 0 0 -100 700 -100 800
P 2 1 0 0 -100 800 -300 800
P 2 1 0 0 -100 700 100 700
P 2 1 0 0 100 700 100 500
P 2 1 0 0 -200 500 -200 400
P 2 1 0 0 -200 400 -200 300
P 2 1 0 0 -200 300 -200 -100
P 2 1 0 0 -200 -100 -100 -100
P 2 1 0 0 -100 -100 0 -100
P 2 1 0 0 0 -100 400 -100
P 2 1 0 0 400 -100 400 300
P 2 1 0 0 400 300 400 400
P 2 1 0 0 400 400 400 500
P 2 1 0 0 400 500 0 500
P 2 1 0 0 0 500 -200 500
P 2 1 0 0 0 500 0 -100
P 2 1 0 0 -200 300 400 300
P 2 1 0 0 -400 -900 -400 -550
P 2 1 0 0 -400 -550 -1200 -550
P 2 1 0 0 -1200 -550 -1200 -900
P 2 1 0 0 -300 -900 -300 -600
P 2 1 0 0 -300 -600 -100 -600
P 2 1 0 0 -100 -600 600 -600
P 2 1 0 0 600 -600 600 -900
P 2 1 0 0 700 -900 700 -400
P 2 1 0 0 900 300 900 200
P 2 1 0 0 900 200 900 100
P 2 1 0 0 900 100 1000 150
P 2 1 0 0 1000 150 1100 200
P 2 1 0 0 1100 200 1000 250
P 2 1 0 0 1000 250 900 300
P 2 1 0 0 900 200 700 200
P 2 1 0 0 700 300 700 100
P 2 1 0 0 700 100 500 100
P 2 1 0 0 500 100 500 300
P 2 1 0 0 500 300 600 300
P 2 1 0 0 600 300 700 300
P 2 1 0 0 400 400 600 400
P 2 1 0 0 600 400 600 300
P 2 1 0 0 700 -400 1200 -400
P 2 1 0 0 1200 -400 1200 -900
P 2 1 0 0 -300 400 -200 400
P 2 1 0 0 -100 -100 -100 -600
P 2 1 0 0 1000 300 1300 300
P 2 1 0 0 1000 100 1300 100
P 2 1 0 0 1000 300 1000 250
P 2 1 0 0 1000 100 1000 150
P 2 1 0 0 760 -810 760 -650
P 2 1 0 0 860 -810 860 -540
P 2 1 0 0 960 -810 960 -540
P 2 1 0 0 1060 -810 1060 -490
C -900 -400 10 1 1 0 N
C -600 400 10 1 1 0 N
T 0 -1158 748 56 0 1 0 XCLK
T 0 -1102 448 56 0 1 0 ANA_IN
T 0 -1074 248 56 0 1 0 ANA_OUT
T 0 -1186 48 56 0 1 0 MIC
T 0 -1186 -152 56 0 1 0 MIC
T 0 -1186 -262 56 0 1 0 REF
T 0 -1186 -462 56 0 1 0 AGC
T 0 1114 358 56 0 1 0 SP+
T 0 1114 28 56 0 1 0 SP-
X A0 1 -200 -1100 200 U 40 40 1 1 O 
X A1 2 -100 -1100 200 U 40 40 1 1 O 
X A2 3 0 -1100 200 U 40 40 1 1 O 
X A3 4 100 -1100 200 U 40 40 1 1 O 
X A4 5 200 -1100 200 U 40 40 1 1 O 
X A5 6 300 -1100 200 U 40 40 1 1 O 
X A6 9 400 -1100 200 U 40 40 1 1 O 
X A7 10 500 -1100 200 U 40 40 1 1 O 
X AGC 19 -1500 -400 200 R 40 40 1 1 P 
X ANA_IN 20 -1500 400 200 R 40 40 1 1 I 
X ANA_OUT 21 -1500 200 200 R 40 40 1 1 O 
X MIC 17 -1500 0 200 R 40 40 1 1 I 
X MIC_REF 18 -1500 -200 200 R 40 40 1 1 I 
X PLAYE 24 900 -1100 200 U 40 40 1 1 I 
X PLAYL 23 1000 -1100 200 U 40 40 1 1 I 
X REC 27 800 -1100 200 U 40 40 1 1 I 
X RECLED 25 1100 -1100 200 U 40 40 1 1 O 
X SP+ 14 1500 300 200 L 40 40 1 1 O 
X SP- 15 1500 100 200 L 40 40 1 1 O 
X VCCA 16 -1100 -1100 200 U 40 40 1 1 W 
X VCCD 28 -500 -1100 200 U 40 40 1 1 W 
X VSSA 13 -900 -1100 200 U 40 40 1 1 W 
X VSSD 12 -700 -1100 200 U 40 40 1 1 W 
X XCLK 26 -1500 700 200 R 40 40 1 1 I 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 11 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 22 -100 0 100 R 40 40 5 1 U 
ENDDRAW
ENDDEF

#
# Dev Name: ISD1700E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: 
# Gate count = 1
#
DEF ISD1700E ?? 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ISD1700
DRAW
P 2 1 0 0 -700 1000 -700 -1100
P 2 1 0 0 -700 -1100 300 -1100
P 2 1 0 0 300 -1100 300 1000
P 2 1 0 0 300 1000 -700 1000
P 2 1 0 0 -600 150 -500 150
P 2 1 0 0 -600 550 -400 550
P 2 1 0 0 -600 650 -400 650
P 2 1 0 0 -600 950 -400 950
P 2 1 0 0 -600 750 -400 750
P 2 1 0 0 -600 850 -400 850
P 2 1 0 0 -100 950 200 950
P 2 1 0 0 100 750 200 750
P 2 1 0 0 -100 -850 0 -850
P 2 1 0 0 0 750 100 750
P 2 1 0 0 -600 450 -500 450
X AGC 18 -800 -1000 100 R 40 40 1 1 P 
X ANALN 9 -800 -700 100 R 40 40 1 1 I 
X AUD/AUX 17 400 -700 100 L 40 40 1 1 O 
X ERASE 25 -800 700 100 R 40 40 1 1 I I
X FT 22 -800 400 100 R 40 40 1 1 I I
X FWD 26 -800 600 100 R 40 40 1 1 I I
X INT/RDY 27 400 -900 100 L 40 40 1 1 B 
X LED 2 400 700 100 L 40 40 1 1 I I
X MIC+ 10 -800 -400 100 R 40 40 1 1 I 
X MIC- 11 -800 -500 100 R 40 40 1 1 I 
X MISO 4 -800 -200 100 R 40 40 1 1 I 
X MOSI 5 -800 -100 100 R 40 40 1 1 I 
X PLAY 23 -800 800 100 R 40 40 1 1 I I
X REC 24 -800 900 100 R 40 40 1 1 I I
X RESET 3 400 900 100 L 40 40 1 1 I I
X R_OSC 20 -800 -900 100 R 40 40 1 1 P 
X SCLK 6 -800 0 100 R 40 40 1 1 I C
X SP+ 15 400 -400 100 L 40 40 1 1 O 
X SP- 13 400 -500 100 L 40 40 1 1 O 
X SS 7 -800 100 100 R 40 40 1 1 I I
X VCCA 21 400 200 100 L 40 40 1 1 W 
X VCCD 1 400 500 100 L 40 40 1 1 W 
X VCCP 14 400 0 100 L 40 40 1 1 W 
X VOL 19 -800 500 100 R 40 40 1 1 I I
X VSSA 8 400 100 100 L 40 40 1 1 W 
X VSSD 28 400 400 100 L 40 40 1 1 W 
X VSSP1 16 400 -100 100 L 40 40 1 1 W 
X VSSP2 12 400 -200 100 L 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISD1700P
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: 
# Gate count = 1
#
DEF ISD1700P ?? 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ISD1700
DRAW
P 2 1 0 0 -700 1000 -700 -1100
P 2 1 0 0 -700 -1100 300 -1100
P 2 1 0 0 300 -1100 300 1000
P 2 1 0 0 300 1000 -700 1000
P 2 1 0 0 -600 150 -500 150
P 2 1 0 0 -600 550 -400 550
P 2 1 0 0 -600 650 -400 650
P 2 1 0 0 -600 950 -400 950
P 2 1 0 0 -600 750 -400 750
P 2 1 0 0 -600 850 -400 850
P 2 1 0 0 -100 950 200 950
P 2 1 0 0 100 750 200 750
P 2 1 0 0 -100 -850 0 -850
P 2 1 0 0 0 750 100 750
P 2 1 0 0 -600 450 -500 450
X AGC 18 -800 -1000 100 R 40 40 1 1 P 
X ANALN 9 -800 -700 100 R 40 40 1 1 I 
X AUD/AUX 17 400 -700 100 L 40 40 1 1 O 
X ERASE 25 -800 700 100 R 40 40 1 1 I I
X FT 22 -800 400 100 R 40 40 1 1 I I
X FWD 26 -800 600 100 R 40 40 1 1 I I
X INT/RDY 27 400 -900 100 L 40 40 1 1 B 
X LED 2 400 700 100 L 40 40 1 1 I I
X MIC+ 10 -800 -400 100 R 40 40 1 1 I 
X MIC- 11 -800 -500 100 R 40 40 1 1 I 
X MISO 4 -800 -200 100 R 40 40 1 1 I 
X MOSI 5 -800 -100 100 R 40 40 1 1 I 
X PLAY 23 -800 800 100 R 40 40 1 1 I I
X REC 24 -800 900 100 R 40 40 1 1 I I
X RESET 3 400 900 100 L 40 40 1 1 I I
X R_OSC 20 -800 -900 100 R 40 40 1 1 P 
X SCLK 6 -800 0 100 R 40 40 1 1 I C
X SP+ 15 400 -400 100 L 40 40 1 1 O 
X SP- 13 400 -500 100 L 40 40 1 1 O 
X SS 7 -800 100 100 R 40 40 1 1 I I
X VCCA 21 400 200 100 L 40 40 1 1 W 
X VCCD 1 400 500 100 L 40 40 1 1 W 
X VCCP 14 400 0 100 L 40 40 1 1 W 
X VOL 19 -800 500 100 R 40 40 1 1 I I
X VSSA 8 400 100 100 L 40 40 1 1 W 
X VSSD 28 400 400 100 L 40 40 1 1 W 
X VSSP1 16 400 -100 100 L 40 40 1 1 W 
X VSSP2 12 400 -200 100 L 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISD1700SY
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: 
# Gate count = 1
#
DEF ISD1700SY ?? 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ISD1700
DRAW
P 2 1 0 0 -700 1000 -700 -1100
P 2 1 0 0 -700 -1100 300 -1100
P 2 1 0 0 300 -1100 300 1000
P 2 1 0 0 300 1000 -700 1000
P 2 1 0 0 -600 150 -500 150
P 2 1 0 0 -600 550 -400 550
P 2 1 0 0 -600 650 -400 650
P 2 1 0 0 -600 950 -400 950
P 2 1 0 0 -600 750 -400 750
P 2 1 0 0 -600 850 -400 850
P 2 1 0 0 -100 950 200 950
P 2 1 0 0 100 750 200 750
P 2 1 0 0 -100 -850 0 -850
P 2 1 0 0 0 750 100 750
P 2 1 0 0 -600 450 -500 450
X AGC 18 -800 -1000 100 R 40 40 1 1 P 
X ANALN 9 -800 -700 100 R 40 40 1 1 I 
X AUD/AUX 17 400 -700 100 L 40 40 1 1 O 
X ERASE 25 -800 700 100 R 40 40 1 1 I I
X FT 22 -800 400 100 R 40 40 1 1 I I
X FWD 26 -800 600 100 R 40 40 1 1 I I
X INT/RDY 27 400 -900 100 L 40 40 1 1 B 
X LED 2 400 700 100 L 40 40 1 1 I I
X MIC+ 10 -800 -400 100 R 40 40 1 1 I 
X MIC- 11 -800 -500 100 R 40 40 1 1 I 
X MISO 4 -800 -200 100 R 40 40 1 1 I 
X MOSI 5 -800 -100 100 R 40 40 1 1 I 
X PLAY 23 -800 800 100 R 40 40 1 1 I I
X REC 24 -800 900 100 R 40 40 1 1 I I
X RESET 3 400 900 100 L 40 40 1 1 I I
X R_OSC 20 -800 -900 100 R 40 40 1 1 P 
X SCLK 6 -800 0 100 R 40 40 1 1 I C
X SP+ 15 400 -400 100 L 40 40 1 1 O 
X SP- 13 400 -500 100 L 40 40 1 1 O 
X SS 7 -800 100 100 R 40 40 1 1 I I
X VCCA 21 400 200 100 L 40 40 1 1 W 
X VCCD 1 400 500 100 L 40 40 1 1 W 
X VCCP 14 400 0 100 L 40 40 1 1 W 
X VOL 19 -800 500 100 R 40 40 1 1 I I
X VSSA 8 400 100 100 L 40 40 1 1 W 
X VSSD 28 400 400 100 L 40 40 1 1 W 
X VSSP1 16 400 -100 100 L 40 40 1 1 W 
X VSSP2 12 400 -200 100 L 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2532E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2532E IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2532E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 15 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 8 -500 800 100 R 40 40 2 1 I 
X A1 9 -500 700 100 R 40 40 2 1 I 
X A2 10 -500 600 100 R 40 40 2 1 I 
X A3 11 -500 500 100 R 40 40 2 1 I 
X A4 12 -500 400 100 R 40 40 2 1 I 
X A5 13 -500 300 100 R 40 40 2 1 I 
X A6 14 -500 200 100 R 40 40 2 1 I 
X A7 16 -500 100 100 R 40 40 2 1 I 
X A8 17 -500 0 100 R 40 40 2 1 I 
X AGC 26 500 -900 100 L 40 40 2 1 P 
X ANA_IN 27 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 28 500 -400 100 L 40 40 2 1 O 
X AUX_IN 18 500 0 100 L 40 40 2 1 I 
X CE 2 -500 -400 100 R 40 40 2 1 I I
X EOM 4 -500 -700 100 R 40 40 2 1 O I
X MIC 24 500 -700 100 L 40 40 2 1 I 
X MIC_REF 25 500 -600 100 L 40 40 2 1 I 
X OVF 1 -500 -800 100 R 40 40 2 1 O I
X P/R 6 -500 -600 100 R 40 40 2 1 I 
X PD 3 -500 -500 100 R 40 40 2 1 I 
X SP+ 21 500 200 100 L 40 40 2 1 O 
X SP- 22 500 100 100 L 40 40 2 1 O 
X VCCA 23 500 700 100 L 40 40 2 1 W 
X VCCD 7 500 800 100 L 40 40 2 1 W 
X VSSA 20 500 400 100 L 40 40 2 1 W 
X VSSD 19 500 500 100 L 40 40 2 1 W 
X XCLK 5 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2532P
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2532P IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2532P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2532S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2532S IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2532S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2540E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2540E IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2540E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 15 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 8 -500 800 100 R 40 40 2 1 I 
X A1 9 -500 700 100 R 40 40 2 1 I 
X A2 10 -500 600 100 R 40 40 2 1 I 
X A3 11 -500 500 100 R 40 40 2 1 I 
X A4 12 -500 400 100 R 40 40 2 1 I 
X A5 13 -500 300 100 R 40 40 2 1 I 
X A6 14 -500 200 100 R 40 40 2 1 I 
X A7 16 -500 100 100 R 40 40 2 1 I 
X A8 17 -500 0 100 R 40 40 2 1 I 
X AGC 26 500 -900 100 L 40 40 2 1 P 
X ANA_IN 27 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 28 500 -400 100 L 40 40 2 1 O 
X AUX_IN 18 500 0 100 L 40 40 2 1 I 
X CE 2 -500 -400 100 R 40 40 2 1 I I
X EOM 4 -500 -700 100 R 40 40 2 1 O I
X MIC 24 500 -700 100 L 40 40 2 1 I 
X MIC_REF 25 500 -600 100 L 40 40 2 1 I 
X OVF 1 -500 -800 100 R 40 40 2 1 O I
X P/R 6 -500 -600 100 R 40 40 2 1 I 
X PD 3 -500 -500 100 R 40 40 2 1 I 
X SP+ 21 500 200 100 L 40 40 2 1 O 
X SP- 22 500 100 100 L 40 40 2 1 O 
X VCCA 23 500 700 100 L 40 40 2 1 W 
X VCCD 7 500 800 100 L 40 40 2 1 W 
X VSSA 20 500 400 100 L 40 40 2 1 W 
X VSSD 19 500 500 100 L 40 40 2 1 W 
X XCLK 5 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2540P
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2540P IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2540P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2540S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2540S IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2540S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2548E
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2548E IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2548E" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 15 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 8 -500 800 100 R 40 40 2 1 I 
X A1 9 -500 700 100 R 40 40 2 1 I 
X A2 10 -500 600 100 R 40 40 2 1 I 
X A3 11 -500 500 100 R 40 40 2 1 I 
X A4 12 -500 400 100 R 40 40 2 1 I 
X A5 13 -500 300 100 R 40 40 2 1 I 
X A6 14 -500 200 100 R 40 40 2 1 I 
X A7 16 -500 100 100 R 40 40 2 1 I 
X A8 17 -500 0 100 R 40 40 2 1 I 
X AGC 26 500 -900 100 L 40 40 2 1 P 
X ANA_IN 27 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 28 500 -400 100 L 40 40 2 1 O 
X AUX_IN 18 500 0 100 L 40 40 2 1 I 
X CE 2 -500 -400 100 R 40 40 2 1 I I
X EOM 4 -500 -700 100 R 40 40 2 1 O I
X MIC 24 500 -700 100 L 40 40 2 1 I 
X MIC_REF 25 500 -600 100 L 40 40 2 1 I 
X OVF 1 -500 -800 100 R 40 40 2 1 O I
X P/R 6 -500 -600 100 R 40 40 2 1 I 
X PD 3 -500 -500 100 R 40 40 2 1 I 
X SP+ 21 500 200 100 L 40 40 2 1 O 
X SP- 22 500 100 100 L 40 40 2 1 O 
X VCCA 23 500 700 100 L 40 40 2 1 W 
X VCCD 7 500 800 100 L 40 40 2 1 W 
X VSSA 20 500 400 100 L 40 40 2 1 W 
X VSSD 19 500 500 100 L 40 40 2 1 W 
X XCLK 5 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2548P
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2548P IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2548P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2548S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2548S IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2548S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2560E
# Package Name: TSOP
# Dev Tech: 60
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2560E IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2560E" -350 -1100 50 H V L B
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 8 -500 800 100 R 40 40 1 1 I 
X A1 9 -500 700 100 R 40 40 1 1 I 
X A2 10 -500 600 100 R 40 40 1 1 I 
X A3 11 -500 500 100 R 40 40 1 1 I 
X A4 12 -500 400 100 R 40 40 1 1 I 
X A5 13 -500 300 100 R 40 40 1 1 I 
X A6 14 -500 200 100 R 40 40 1 1 I 
X A7 15 -500 100 100 R 40 40 1 1 I 
X A8 16 -500 0 100 R 40 40 1 1 I 
X A9 17 -500 -100 100 R 40 40 1 1 I 
X AGC 26 500 -900 100 L 40 40 1 1 P 
X ANA_IN 27 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 28 500 -400 100 L 40 40 1 1 O 
X AUX_IN 18 500 0 100 L 40 40 1 1 I 
X CE 2 -500 -400 100 R 40 40 1 1 I I
X EOM 4 -500 -700 100 R 40 40 1 1 O I
X MIC 24 500 -700 100 L 40 40 1 1 I 
X MIC_REF 25 500 -600 100 L 40 40 1 1 I 
X OVF 1 -500 -800 100 R 40 40 1 1 O I
X P/R 6 -500 -600 100 R 40 40 1 1 I 
X PD 3 -500 -500 100 R 40 40 1 1 I 
X SP+ 21 500 200 100 L 40 40 1 1 O 
X SP- 22 500 100 100 L 40 40 1 1 O 
X VCCA 23 500 700 100 L 40 40 1 1 W 
X VCCD 7 500 800 100 L 40 40 1 1 W 
X VSSA 20 500 400 100 L 40 40 1 1 W 
X VSSD 19 500 500 100 L 40 40 1 1 W 
X XCLK 5 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2560P
# Package Name: DIL28-6
# Dev Tech: 60
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2560P IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2560P" -350 -1100 50 H V L B
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2560S
# Package Name: SO28W
# Dev Tech: 60
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2560S IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2560S" -350 -1100 50 H V L B
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2564E
# Package Name: TSOP
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2564E IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2564E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 15 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 8 -500 800 100 R 40 40 2 1 I 
X A1 9 -500 700 100 R 40 40 2 1 I 
X A2 10 -500 600 100 R 40 40 2 1 I 
X A3 11 -500 500 100 R 40 40 2 1 I 
X A4 12 -500 400 100 R 40 40 2 1 I 
X A5 13 -500 300 100 R 40 40 2 1 I 
X A6 14 -500 200 100 R 40 40 2 1 I 
X A7 16 -500 100 100 R 40 40 2 1 I 
X A8 17 -500 0 100 R 40 40 2 1 I 
X AGC 26 500 -900 100 L 40 40 2 1 P 
X ANA_IN 27 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 28 500 -400 100 L 40 40 2 1 O 
X AUX_IN 18 500 0 100 L 40 40 2 1 I 
X CE 2 -500 -400 100 R 40 40 2 1 I I
X EOM 4 -500 -700 100 R 40 40 2 1 O I
X MIC 24 500 -700 100 L 40 40 2 1 I 
X MIC_REF 25 500 -600 100 L 40 40 2 1 I 
X OVF 1 -500 -800 100 R 40 40 2 1 O I
X P/R 6 -500 -600 100 R 40 40 2 1 I 
X PD 3 -500 -500 100 R 40 40 2 1 I 
X SP+ 21 500 200 100 L 40 40 2 1 O 
X SP- 22 500 100 100 L 40 40 2 1 O 
X VCCA 23 500 700 100 L 40 40 2 1 W 
X VCCD 7 500 800 100 L 40 40 2 1 W 
X VSSA 20 500 400 100 L 40 40 2 1 W 
X VSSD 19 500 500 100 L 40 40 2 1 W 
X XCLK 5 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2564P
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2564P IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2564P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2564S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD2564S IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD2564S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 8 -100 0 100 R 40 40 1 1 U 
# Gate Name: IC
# Symbol Name: ISD2532
P 2 2 0 0 -400 900 -400 -1000
P 2 2 0 0 -400 -1000 400 -1000
P 2 2 0 0 400 -1000 400 900
P 2 2 0 0 400 900 -400 900
P 2 2 0 0 -300 -650 -130 -650
P 2 2 0 0 -220 -550 -180 -550
P 2 2 0 0 -305 -750 -140 -750
P 2 2 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 2 1 I 
X A1 2 -500 700 100 R 40 40 2 1 I 
X A2 3 -500 600 100 R 40 40 2 1 I 
X A3 4 -500 500 100 R 40 40 2 1 I 
X A4 5 -500 400 100 R 40 40 2 1 I 
X A5 6 -500 300 100 R 40 40 2 1 I 
X A6 7 -500 200 100 R 40 40 2 1 I 
X A7 9 -500 100 100 R 40 40 2 1 I 
X A8 10 -500 0 100 R 40 40 2 1 I 
X AGC 19 500 -900 100 L 40 40 2 1 P 
X ANA_IN 20 500 -100 100 L 40 40 2 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 2 1 O 
X AUX_IN 11 500 0 100 L 40 40 2 1 I 
X CE 23 -500 -400 100 R 40 40 2 1 I I
X EOM 25 -500 -700 100 R 40 40 2 1 O I
X MIC 17 500 -700 100 L 40 40 2 1 I 
X MIC_REF 18 500 -600 100 L 40 40 2 1 I 
X OVF 22 -500 -800 100 R 40 40 2 1 O I
X P/R 27 -500 -600 100 R 40 40 2 1 I 
X PD 24 -500 -500 100 R 40 40 2 1 I 
X SP+ 14 500 200 100 L 40 40 2 1 O 
X SP- 15 500 100 100 L 40 40 2 1 O 
X VCCA 16 500 700 100 L 40 40 2 1 W 
X VCCD 28 500 800 100 L 40 40 2 1 W 
X VSSA 13 500 400 100 L 40 40 2 1 W 
X VSSD 12 500 500 100 L 40 40 2 1 W 
X XCLK 26 -500 -900 100 R 40 40 2 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2575E
# Package Name: TSOP
# Dev Tech: 75
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2575E IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2575E" -350 -1100 50 H V L B
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 8 -500 800 100 R 40 40 1 1 I 
X A1 9 -500 700 100 R 40 40 1 1 I 
X A2 10 -500 600 100 R 40 40 1 1 I 
X A3 11 -500 500 100 R 40 40 1 1 I 
X A4 12 -500 400 100 R 40 40 1 1 I 
X A5 13 -500 300 100 R 40 40 1 1 I 
X A6 14 -500 200 100 R 40 40 1 1 I 
X A7 15 -500 100 100 R 40 40 1 1 I 
X A8 16 -500 0 100 R 40 40 1 1 I 
X A9 17 -500 -100 100 R 40 40 1 1 I 
X AGC 26 500 -900 100 L 40 40 1 1 P 
X ANA_IN 27 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 28 500 -400 100 L 40 40 1 1 O 
X AUX_IN 18 500 0 100 L 40 40 1 1 I 
X CE 2 -500 -400 100 R 40 40 1 1 I I
X EOM 4 -500 -700 100 R 40 40 1 1 O I
X MIC 24 500 -700 100 L 40 40 1 1 I 
X MIC_REF 25 500 -600 100 L 40 40 1 1 I 
X OVF 1 -500 -800 100 R 40 40 1 1 O I
X P/R 6 -500 -600 100 R 40 40 1 1 I 
X PD 3 -500 -500 100 R 40 40 1 1 I 
X SP+ 21 500 200 100 L 40 40 1 1 O 
X SP- 22 500 100 100 L 40 40 1 1 O 
X VCCA 23 500 700 100 L 40 40 1 1 W 
X VCCD 7 500 800 100 L 40 40 1 1 W 
X VSSA 20 500 400 100 L 40 40 1 1 W 
X VSSD 19 500 500 100 L 40 40 1 1 W 
X XCLK 5 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2575P
# Package Name: DIL28-6
# Dev Tech: 75
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2575P IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2575P" -350 -1100 50 H V L B
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2575S
# Package Name: SO28W
# Dev Tech: 75
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2575S IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2575S" -350 -1100 50 H V L B
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2590E
# Package Name: TSOP
# Dev Tech: 90
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2590E IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2590E" -350 -1100 50 H V L B
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 8 -500 800 100 R 40 40 1 1 I 
X A1 9 -500 700 100 R 40 40 1 1 I 
X A2 10 -500 600 100 R 40 40 1 1 I 
X A3 11 -500 500 100 R 40 40 1 1 I 
X A4 12 -500 400 100 R 40 40 1 1 I 
X A5 13 -500 300 100 R 40 40 1 1 I 
X A6 14 -500 200 100 R 40 40 1 1 I 
X A7 15 -500 100 100 R 40 40 1 1 I 
X A8 16 -500 0 100 R 40 40 1 1 I 
X A9 17 -500 -100 100 R 40 40 1 1 I 
X AGC 26 500 -900 100 L 40 40 1 1 P 
X ANA_IN 27 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 28 500 -400 100 L 40 40 1 1 O 
X AUX_IN 18 500 0 100 L 40 40 1 1 I 
X CE 2 -500 -400 100 R 40 40 1 1 I I
X EOM 4 -500 -700 100 R 40 40 1 1 O I
X MIC 24 500 -700 100 L 40 40 1 1 I 
X MIC_REF 25 500 -600 100 L 40 40 1 1 I 
X OVF 1 -500 -800 100 R 40 40 1 1 O I
X P/R 6 -500 -600 100 R 40 40 1 1 I 
X PD 3 -500 -500 100 R 40 40 1 1 I 
X SP+ 21 500 200 100 L 40 40 1 1 O 
X SP- 22 500 100 100 L 40 40 1 1 O 
X VCCA 23 500 700 100 L 40 40 1 1 W 
X VCCD 7 500 800 100 L 40 40 1 1 W 
X VSSA 20 500 400 100 L 40 40 1 1 W 
X VSSD 19 500 500 100 L 40 40 1 1 W 
X XCLK 5 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2590P
# Package Name: DIL28-6
# Dev Tech: 90
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2590P IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2590P" -350 -1100 50 H V L B
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD2590S
# Package Name: SO28W
# Dev Tech: 90
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD2590S IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD2590S" -350 -1100 50 H V L B
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-SI
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-SI IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-SI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-120E
# Package Name: TSOP
# Dev Tech: 120
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-120E IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-120E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-120ED
# Package Name: TSOP
# Dev Tech: 120
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-120ED IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-120ED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-120EI
# Package Name: TSOP
# Dev Tech: 120
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-120EI IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-120EI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-120P
# Package Name: DIL28-6
# Dev Tech: 120
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-120P IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-120P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-120S
# Package Name: SO28W
# Dev Tech: 120
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-120S IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-120S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-150E
# Package Name: TSOP
# Dev Tech: 150
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-150E IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-150E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-150ED
# Package Name: TSOP
# Dev Tech: 150
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-150ED IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-150ED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-150EI
# Package Name: TSOP
# Dev Tech: 150
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-150EI IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-150EI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-150P
# Package Name: DIL28-6
# Dev Tech: 150
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-150P IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-150P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-150S
# Package Name: SO28W
# Dev Tech: 150
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-150S IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-150S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-180E
# Package Name: TSOP
# Dev Tech: 180
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-180E IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-180E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-180ED
# Package Name: TSOP
# Dev Tech: 180
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-180ED IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-180ED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-180EI
# Package Name: TSOP
# Dev Tech: 180
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-180EI IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-180EI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-180P
# Package Name: DIL28-6
# Dev Tech: 180
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-180P IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-180P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-180S
# Package Name: SO28W
# Dev Tech: 180
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-180S IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-180S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-240E
# Package Name: TSOP
# Dev Tech: 240
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-240E IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-240E" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-240ED
# Package Name: TSOP
# Dev Tech: 240
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-240ED IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-240ED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-240EI
# Package Name: TSOP
# Dev Tech: 240
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-240EI IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-240EI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-240P
# Package Name: DIL28-6
# Dev Tech: 240
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-240P IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-240P" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002-240S
# Package Name: SO28W
# Dev Tech: 240
# Dev Prefix: IC1
# Gate count = 12
#
DEF ISD4002-240S IC1 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC1" 0 0 50 H V C C
F1 "ISD4002-240S" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-04ME
# Package Name: TSOP
# Dev Tech: 04
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-04ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-04ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-04MED
# Package Name: TSOP
# Dev Tech: 04
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-04MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-04MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-04MEI
# Package Name: TSOP
# Dev Tech: 04
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-04MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-04MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-04MP
# Package Name: DIL28-6
# Dev Tech: 04
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-04MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-04MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-04MS
# Package Name: SO28W
# Dev Tech: 04
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-04MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-04MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-04MSI
# Package Name: SO28W
# Dev Tech: 04
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-04MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-04MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-05ME
# Package Name: TSOP
# Dev Tech: 05
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-05ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-05ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-05MED
# Package Name: TSOP
# Dev Tech: 05
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-05MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-05MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-05MEI
# Package Name: TSOP
# Dev Tech: 05
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-05MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-05MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-05MP
# Package Name: DIL28-6
# Dev Tech: 05
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-05MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-05MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-05MS
# Package Name: SO28W
# Dev Tech: 05
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-05MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-05MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-05MSI
# Package Name: SO28W
# Dev Tech: 05
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-05MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-05MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-06ME
# Package Name: TSOP
# Dev Tech: 06
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-06ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-06ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-06MED
# Package Name: TSOP
# Dev Tech: 06
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-06MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-06MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-06MEI
# Package Name: TSOP
# Dev Tech: 06
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-06MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-06MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-06MP
# Package Name: DIL28-6
# Dev Tech: 06
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-06MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-06MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-06MS
# Package Name: SO28W
# Dev Tech: 06
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-06MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-06MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-06MSI
# Package Name: SO28W
# Dev Tech: 06
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-06MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-06MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-08ME
# Package Name: TSOP
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-08ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-08ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-08MED
# Package Name: TSOP
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-08MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-08MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-08MEI
# Package Name: TSOP
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-08MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-08MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-08MP
# Package Name: DIL28-6
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-08MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-08MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-08MS
# Package Name: SO28W
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-08MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-08MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4003-08MSI
# Package Name: SO28W
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4003-08MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4003-08MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-08ME
# Package Name: TSOP
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-08ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-08ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-08MED
# Package Name: TSOP
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-08MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-08MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-08MEI
# Package Name: TSOP
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-08MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-08MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-08MP
# Package Name: DIL28-6
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-08MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-08MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-08MS
# Package Name: SO28W
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-08MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-08MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-08MSI
# Package Name: SO28W
# Dev Tech: 08
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-08MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-08MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-10ME
# Package Name: TSOP
# Dev Tech: 10
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-10ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-10ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-10MED
# Package Name: TSOP
# Dev Tech: 10
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-10MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-10MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-10MEI
# Package Name: TSOP
# Dev Tech: 10
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-10MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-10MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-10MP
# Package Name: DIL28-6
# Dev Tech: 10
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-10MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-10MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-10MS
# Package Name: SO28W
# Dev Tech: 10
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-10MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-10MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-10MSI
# Package Name: SO28W
# Dev Tech: 10
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-10MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-10MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-12ME
# Package Name: TSOP
# Dev Tech: 12
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-12ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-12ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-12MED
# Package Name: TSOP
# Dev Tech: 12
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-12MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-12MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-12MEI
# Package Name: TSOP
# Dev Tech: 12
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-12MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-12MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-12MP
# Package Name: DIL28-6
# Dev Tech: 12
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-12MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-12MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-12MS
# Package Name: SO28W
# Dev Tech: 12
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-12MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-12MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-12MSI
# Package Name: SO28W
# Dev Tech: 12
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-12MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-12MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-16ME
# Package Name: TSOP
# Dev Tech: 16
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-16ME IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-16ME" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-16MED
# Package Name: TSOP
# Dev Tech: 16
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-16MED IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-16MED" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-16MEI
# Package Name: TSOP
# Dev Tech: 16
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-16MEI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-16MEI" 0 0 50 H V C C
F2 "isd-new-1-TSOP" 0 150 50 H I C C
DRAW
X NC 3 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 4 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 13 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 14 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 15 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 16 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 23 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 27 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 28 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 22 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 25 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 24 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 20 600 -200 100 L 40 40 12 1 I 
X INT 5 -600 -1000 100 R 40 40 12 1 O I
X MISO 11 -600 800 100 R 40 40 12 1 O 
X MOSI 10 -600 700 100 R 40 40 12 1 I 
X RAC 2 -600 -900 100 R 40 40 12 1 O 
X SCLK 8 -600 600 100 R 40 40 12 1 I 
X SS 9 -600 500 100 R 40 40 12 1 I I
X VCCA 26 600 400 100 L 40 40 12 1 W 
X VCCD 7 600 800 100 L 40 40 12 1 W 
X VSSA@1 1 600 100 100 L 40 40 12 1 W 
X VSSA@2 17 600 200 100 L 40 40 12 1 W 
X VSSA@3 18 600 300 100 L 40 40 12 1 W 
X VSSD 12 600 700 100 L 40 40 12 1 W 
X XCLK 6 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-16MP
# Package Name: DIL28-6
# Dev Tech: 16
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-16MP IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-16MP" 0 0 50 H V C C
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-16MS
# Package Name: SO28W
# Dev Tech: 16
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-16MS IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-16MS" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4004-16MSI
# Package Name: SO28W
# Dev Tech: 16
# Dev Prefix: IC
# Gate count = 12
#
DEF ISD4004-16MSI IC 0 40 Y Y 12 L N
# Gate Name: G$1
# Symbol Name: NC-LEFT
F0 "IC" 0 0 50 H V C C
F1 "ISD4004-16MSI" 0 0 50 H V C C
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
X NC 5 -100 0 100 R 40 40 1 1 U 
# Gate Name: G$2
# Symbol Name: NC-LEFT
X NC 6 -100 0 100 R 40 40 2 1 U 
# Gate Name: G$3
# Symbol Name: NC-LEFT
X NC 7 -100 0 100 R 40 40 3 1 U 
# Gate Name: G$4
# Symbol Name: NC-LEFT
X NC 8 -100 0 100 R 40 40 4 1 U 
# Gate Name: G$5
# Symbol Name: NC-LEFT
X NC 9 -100 0 100 R 40 40 5 1 U 
# Gate Name: G$6
# Symbol Name: NC-LEFT
X NC 10 -100 0 100 R 40 40 6 1 U 
# Gate Name: G$7
# Symbol Name: NC-RIGHT
X NC 19 100 0 100 L 40 40 7 1 U 
# Gate Name: G$8
# Symbol Name: NC-RIGHT
X NC 20 100 0 100 L 40 40 8 1 U 
# Gate Name: G$9
# Symbol Name: NC-RIGHT
X NC 21 100 0 100 L 40 40 9 1 U 
# Gate Name: G$10
# Symbol Name: NC-RIGHT
X NC 22 100 0 100 L 40 40 10 1 U 
# Gate Name: G$11
# Symbol Name: NC-RIGHT
X NC 15 100 0 100 L 40 40 11 1 U 
# Gate Name: IC1
# Symbol Name: ISD4000
P 2 12 0 0 -500 900 -500 -1200
P 2 12 0 0 -500 -1200 500 -1200
P 2 12 0 0 500 -1200 500 900
P 2 12 0 0 500 900 -500 900
P 2 12 0 0 -400 550 -300 550
P 2 12 0 0 -400 -950 -280 -950
X AM_CAP 14 600 -1000 100 L 40 40 12 1 I 
X ANA_IN+ 17 -600 -500 100 R 40 40 12 1 I 
X ANA_IN- 16 -600 -200 100 R 40 40 12 1 I 
X AUD_OUT 13 600 -200 100 L 40 40 12 1 I 
X INT 25 -600 -1000 100 R 40 40 12 1 O I
X MISO 3 -600 800 100 R 40 40 12 1 O 
X MOSI 2 -600 700 100 R 40 40 12 1 I 
X RAC 24 -600 -900 100 R 40 40 12 1 O 
X SCLK 28 -600 600 100 R 40 40 12 1 I 
X SS 1 -600 500 100 R 40 40 12 1 I I
X VCCA 18 600 400 100 L 40 40 12 1 W 
X VCCD 27 600 800 100 L 40 40 12 1 W 
X VSSA@1 11 600 100 100 L 40 40 12 1 W 
X VSSA@2 12 600 200 100 L 40 40 12 1 W 
X VSSA@3 23 600 300 100 L 40 40 12 1 W 
X VSSD 4 600 700 100 L 40 40 12 1 W 
X XCLK 26 -600 -1100 100 R 40 40 12 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD25120P
# Package Name: DIL28-6
# Dev Tech: 120
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD25120P IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD25120P" -350 -1100 50 H V L B
F2 "isd-new-1-DIL28-6" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD25120S
# Package Name: SO28W
# Dev Tech: 120
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD25120S IC 0 40 Y Y 1 L N
# Gate Name: IC1
# Symbol Name: ISD2560
F0 "IC" -350 950 50 H V L B
F1 "ISD25120S" -350 -1100 50 H V L B
F2 "isd-new-1-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -400 900 -400 -1000
P 2 1 0 0 -400 -1000 400 -1000
P 2 1 0 0 400 -1000 400 900
P 2 1 0 0 400 900 -400 900
P 2 1 0 0 -300 -650 -130 -650
P 2 1 0 0 -220 -550 -180 -550
P 2 1 0 0 -305 -750 -140 -750
P 2 1 0 0 -300 -350 -200 -350
X A0 1 -500 800 100 R 40 40 1 1 I 
X A1 2 -500 700 100 R 40 40 1 1 I 
X A2 3 -500 600 100 R 40 40 1 1 I 
X A3 4 -500 500 100 R 40 40 1 1 I 
X A4 5 -500 400 100 R 40 40 1 1 I 
X A5 6 -500 300 100 R 40 40 1 1 I 
X A6 7 -500 200 100 R 40 40 1 1 I 
X A7 8 -500 100 100 R 40 40 1 1 I 
X A8 9 -500 0 100 R 40 40 1 1 I 
X A9 10 -500 -100 100 R 40 40 1 1 I 
X AGC 19 500 -900 100 L 40 40 1 1 P 
X ANA_IN 20 500 -100 100 L 40 40 1 1 I 
X ANA_OUT 21 500 -400 100 L 40 40 1 1 O 
X AUX_IN 11 500 0 100 L 40 40 1 1 I 
X CE 23 -500 -400 100 R 40 40 1 1 I I
X EOM 25 -500 -700 100 R 40 40 1 1 O I
X MIC 17 500 -700 100 L 40 40 1 1 I 
X MIC_REF 18 500 -600 100 L 40 40 1 1 I 
X OVF 22 -500 -800 100 R 40 40 1 1 O I
X P/R 27 -500 -600 100 R 40 40 1 1 I 
X PD 24 -500 -500 100 R 40 40 1 1 I 
X SP+ 14 500 200 100 L 40 40 1 1 O 
X SP- 15 500 100 100 L 40 40 1 1 O 
X VCCA 16 500 700 100 L 40 40 1 1 W 
X VCCD 28 500 800 100 L 40 40 1 1 W 
X VSSA 13 500 400 100 L 40 40 1 1 W 
X VSSD 12 500 500 100 L 40 40 1 1 W 
X XCLK 26 -500 -900 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#End Library