EESchema-LIBRARY Version 2.3  29/04/2008-12:22:25
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 4
#
# Dev Name: ISD25XXP
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD25XXP IC 0 40 Y Y 2 L N
# Gate Name: A
# Symbol Name: ISD25XX
F0 "IC" -500 950 50 H V L B
F1 "ISD25XXP" -500 -1025 50 H V L B
F2 "isd-DIL28-6" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 900 500 900
P 2 1 0 0 500 900 500 -900
P 2 1 0 0 500 -900 -500 -900
P 2 1 0 0 -500 -900 -500 900
P 2 1 0 0 -410 -660 -250 -660
P 2 1 0 0 -410 -560 -250 -560
P 2 1 0 0 -410 -260 -300 -260
P 2 1 0 0 -297 -460 -250 -460
X A0/M0 1 -700 800 200 R 40 40 1 1 I 
X A1/M1 2 -700 700 200 R 40 40 1 1 I 
X A2/M2 3 -700 600 200 R 40 40 1 1 I 
X A3/M3 4 -700 500 200 R 40 40 1 1 I 
X A4/M4 5 -700 400 200 R 40 40 1 1 I 
X A5/M5 6 -700 300 200 R 40 40 1 1 I 
X A6/M6 7 -700 200 200 R 40 40 1 1 I 
X A7 8 -700 100 200 R 40 40 1 1 I 
X A8 9 -700 0 200 R 40 40 1 1 I 
X A9 10 -700 -100 200 R 40 40 1 1 I 
X AGC 19 700 -600 200 L 40 40 1 1 P 
X ANA_IN 20 700 -100 200 L 40 40 1 1 I 
X ANA_OUT 21 700 -400 200 L 40 40 1 1 O 
X AUX_IN 11 700 600 200 L 40 40 1 1 I 
X CE 23 -700 -300 200 R 40 40 1 1 I 
X EOM 25 -700 -600 200 R 40 40 1 1 O 
X MIC 17 700 800 200 L 40 40 1 1 I 
X MIC_REF 18 700 -800 200 L 40 40 1 1 I 
X OVF 22 -700 -700 200 R 40 40 1 1 O 
X P/R 27 -700 -500 200 R 40 40 1 1 I 
X PD 24 -700 -400 200 R 40 40 1 1 I 
X SP+ 14 700 200 200 L 40 40 1 1 O 
X SP- 15 700 400 200 L 40 40 1 1 O 
X XCLK 26 -700 -800 200 R 40 40 1 1 I 
# Gate Name: P
# Symbol Name: VCC2VSS2
T 1 -50 300 50 0 2 0 VCCA
T 1 150 300 50 0 2 0 VCCD
T 1 -50 -200 50 0 2 0 VSSA
T 1 150 -200 50 0 2 0 VSSD
X VCCA 16 -100 300 200 D 40 40 2 1 W 
X VCCD 28 100 300 200 D 40 40 2 1 W 
X VSSA 13 -100 -300 200 U 40 40 2 1 W 
X VSSD 12 100 -300 200 U 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISD25XXS
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF ISD25XXS IC 0 40 Y Y 2 L N
# Gate Name: A
# Symbol Name: ISD25XX
F0 "IC" -500 950 50 H V L B
F1 "ISD25XXS" -500 -1025 50 H V L B
F2 "isd-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 900 500 900
P 2 1 0 0 500 900 500 -900
P 2 1 0 0 500 -900 -500 -900
P 2 1 0 0 -500 -900 -500 900
P 2 1 0 0 -410 -660 -250 -660
P 2 1 0 0 -410 -560 -250 -560
P 2 1 0 0 -410 -260 -300 -260
P 2 1 0 0 -297 -460 -250 -460
X A0/M0 1 -700 800 200 R 40 40 1 1 I 
X A1/M1 2 -700 700 200 R 40 40 1 1 I 
X A2/M2 3 -700 600 200 R 40 40 1 1 I 
X A3/M3 4 -700 500 200 R 40 40 1 1 I 
X A4/M4 5 -700 400 200 R 40 40 1 1 I 
X A5/M5 6 -700 300 200 R 40 40 1 1 I 
X A6/M6 7 -700 200 200 R 40 40 1 1 I 
X A7 8 -700 100 200 R 40 40 1 1 I 
X A8 9 -700 0 200 R 40 40 1 1 I 
X A9 10 -700 -100 200 R 40 40 1 1 I 
X AGC 19 700 -600 200 L 40 40 1 1 P 
X ANA_IN 20 700 -100 200 L 40 40 1 1 I 
X ANA_OUT 21 700 -400 200 L 40 40 1 1 O 
X AUX_IN 11 700 600 200 L 40 40 1 1 I 
X CE 23 -700 -300 200 R 40 40 1 1 I 
X EOM 25 -700 -600 200 R 40 40 1 1 O 
X MIC 17 700 800 200 L 40 40 1 1 I 
X MIC_REF 18 700 -800 200 L 40 40 1 1 I 
X OVF 22 -700 -700 200 R 40 40 1 1 O 
X P/R 27 -700 -500 200 R 40 40 1 1 I 
X PD 24 -700 -400 200 R 40 40 1 1 I 
X SP+ 14 700 200 200 L 40 40 1 1 O 
X SP- 15 700 400 200 L 40 40 1 1 O 
X XCLK 26 -700 -800 200 R 40 40 1 1 I 
# Gate Name: P
# Symbol Name: VCC2VSS2
T 1 -50 300 50 0 2 0 VCCA
T 1 150 300 50 0 2 0 VCCD
T 1 -50 -200 50 0 2 0 VSSA
T 1 150 -200 50 0 2 0 VSSD
X VCCA 16 -100 300 200 D 40 40 2 1 W 
X VCCD 28 100 300 200 D 40 40 2 1 W 
X VSSA 13 -100 -300 200 U 40 40 2 1 W 
X VSSD 12 100 -300 200 U 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002P
# Package Name: DIL28-6
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD4002P IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ISD4002
F0 "IC" -500 950 50 H V L B
F1 "ISD4002P" -500 -1025 50 H V L B
F2 "isd-DIL28-6" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 900 500 900
P 2 1 0 0 500 900 500 -900
P 2 1 0 0 500 -900 -500 -900
P 2 1 0 0 -500 -900 -500 900
P 2 1 0 0 -410 340 -275 340
P 2 1 0 0 -410 540 -312 540
X AM_CAP 14 -700 -200 200 R 40 40 1 1 O 
X ANA_IN+ 17 700 800 200 L 40 40 1 1 I 
X ANA_IN- 16 700 600 200 L 40 40 1 1 I 
X AUD_OUT 13 700 300 200 L 40 40 1 1 O 
X INT 25 -700 300 200 R 40 40 1 1 O 
X MISO 3 -700 800 200 R 40 40 1 1 B 
X MOSI 2 -700 700 200 R 40 40 1 1 B 
X RAC 24 -700 100 200 R 40 40 1 1 O 
X SCLK 28 -700 600 200 R 40 40 1 1 B 
X SS 1 -700 500 200 R 40 40 1 1 I 
X VCCA 18 700 -400 200 L 40 40 1 1 W 
X VCCD 27 700 0 200 L 40 40 1 1 W 
X VSSA 11 700 -600 200 L 40 40 1 1 W 
X VSSA@1 12 700 -700 200 L 40 40 1 1 W 
X VSSA@2 23 700 -800 200 L 40 40 1 1 W 
X VSSD 4 700 -200 200 L 40 40 1 1 W 
X XCLK 26 -700 -600 200 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ISD4002S
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ISD4002S IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ISD4002
F0 "IC" -500 950 50 H V L B
F1 "ISD4002S" -500 -1025 50 H V L B
F2 "isd-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 900 500 900
P 2 1 0 0 500 900 500 -900
P 2 1 0 0 500 -900 -500 -900
P 2 1 0 0 -500 -900 -500 900
P 2 1 0 0 -410 340 -275 340
P 2 1 0 0 -410 540 -312 540
X AM_CAP 14 -700 -200 200 R 40 40 1 1 O 
X ANA_IN+ 17 700 800 200 L 40 40 1 1 I 
X ANA_IN- 16 700 600 200 L 40 40 1 1 I 
X AUD_OUT 13 700 300 200 L 40 40 1 1 O 
X INT 25 -700 300 200 R 40 40 1 1 O 
X MISO 3 -700 800 200 R 40 40 1 1 B 
X MOSI 2 -700 700 200 R 40 40 1 1 B 
X RAC 24 -700 100 200 R 40 40 1 1 O 
X SCLK 28 -700 600 200 R 40 40 1 1 B 
X SS 1 -700 500 200 R 40 40 1 1 I 
X VCCA 18 700 -400 200 L 40 40 1 1 W 
X VCCD 27 700 0 200 L 40 40 1 1 W 
X VSSA 11 700 -600 200 L 40 40 1 1 W 
X VSSA@1 12 700 -700 200 L 40 40 1 1 W 
X VSSA@2 23 700 -800 200 L 40 40 1 1 W 
X VSSD 4 700 -200 200 L 40 40 1 1 W 
X XCLK 26 -700 -600 200 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#End Library