EESchema-LIBRARY Version 2.3  29/04/2008-12:22:28
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 5
#
# Dev Name: ISP2032
# Package Name: PLCC-44
# Dev Tech: ''
# Dev Prefix: U
# Gate count = 2
#
DEF ISP2032 U 0 40 Y Y 2 L N
# Gate Name: A
# Symbol Name: ISP2032
F0 "U" 0 2500 50 H V L B
F1 "ISP2032" 0 -200 50 H V L B
F2 "lattice-PLCC-44" 0 150 50 H I C C
DRAW
P 2 1 0 0 0 0 0 2400
P 2 1 0 0 0 2400 700 2400
P 2 1 0 0 700 2400 700 0
P 2 1 0 0 700 0 0 0
X CLK 11 -300 1700 300 R 40 40 1 1 I C
X IO0 15 -300 100 300 R 40 40 1 1 B 
X IO1 16 -300 200 300 R 40 40 1 1 B 
X IO2 17 -300 300 300 R 40 40 1 1 B 
X IO3 18 -300 400 300 R 40 40 1 1 B 
X IO4 19 -300 500 300 R 40 40 1 1 B 
X IO5 20 -300 600 300 R 40 40 1 1 B 
X IO6 21 -300 700 300 R 40 40 1 1 B 
X IO7 22 -300 800 300 R 40 40 1 1 B 
X IO8 25 -300 900 300 R 40 40 1 1 B 
X IO9 26 -300 1000 300 R 40 40 1 1 B 
X IO10 27 -300 1100 300 R 40 40 1 1 B 
X IO11 28 -300 1200 300 R 40 40 1 1 B 
X IO12 29 -300 1300 300 R 40 40 1 1 B 
X IO13 30 -300 1400 300 R 40 40 1 1 B 
X IO14 31 -300 1500 300 R 40 40 1 1 B 
X IO15 32 -300 1600 300 R 40 40 1 1 B 
X IO16 37 1000 100 300 L 40 40 1 1 B 
X IO17 38 1000 200 300 L 40 40 1 1 B 
X IO18 39 1000 300 300 L 40 40 1 1 B 
X IO19 40 1000 400 300 L 40 40 1 1 B 
X IO20 41 1000 500 300 L 40 40 1 1 B 
X IO21 42 1000 600 300 L 40 40 1 1 B 
X IO22 43 1000 700 300 L 40 40 1 1 B 
X IO23 44 1000 800 300 L 40 40 1 1 B 
X IO24 3 1000 900 300 L 40 40 1 1 B 
X IO25 4 1000 1000 300 L 40 40 1 1 B 
X IO26 5 1000 1100 300 L 40 40 1 1 B 
X IO27 6 1000 1200 300 L 40 40 1 1 B 
X IO28 7 1000 1300 300 L 40 40 1 1 B 
X IO29 8 1000 1400 300 L 40 40 1 1 B 
X IO30 9 1000 1500 300 L 40 40 1 1 B 
X IO31 10 1000 1600 300 L 40 40 1 1 B 
X ISPEN/ 13 -300 2300 300 R 40 40 1 1 I I
X MODE 36 -300 2200 300 R 40 40 1 1 I 
X OE 2 -300 1900 300 R 40 40 1 1 I 
X RESET/ 35 -300 1800 300 R 40 40 1 1 I I
X SCLK 33 -300 2000 300 R 40 40 1 1 I C
X SDI 14 -300 2100 300 R 40 40 1 1 I 
X SDO 24 1000 2100 300 L 40 40 1 1 O 
# Gate Name: P
# Symbol Name: 2PWR2GND
T 1 -50 250 50 0 2 0 VCC
T 1 150 250 50 0 2 0 VCC
T 1 -50 -225 50 0 2 0 GND
T 1 150 -225 50 0 2 0 GND
X GND@1 1 -100 -400 300 U 40 40 2 1 W 
X GND@2 23 100 -400 300 U 40 40 2 1 W 
X VCC@1 12 -100 400 300 D 40 40 2 1 W 
X VCC@2 34 100 400 300 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISP2064
# Package Name: PLCC-84
# Dev Tech: ''
# Dev Prefix: U
# Gate count = 2
#
DEF ISP2064 U 0 40 Y Y 2 L N
# Gate Name: A
# Symbol Name: ISP2064
F0 "U" 0 4100 50 H V L B
F1 "ISP2064" 0 -200 50 H V L B
F2 "lattice-PLCC-84" 0 150 50 H I C C
DRAW
P 2 1 0 0 0 0 0 4000
P 2 1 0 0 0 4000 700 4000
P 2 1 0 0 700 4000 700 0
P 2 1 0 0 700 0 0 0
X CLK 20 -300 3300 300 R 40 40 1 1 I C
X IO0 26 -300 100 300 R 40 40 1 1 B 
X IO1 27 -300 200 300 R 40 40 1 1 B 
X IO2 28 -300 300 300 R 40 40 1 1 B 
X IO3 29 -300 400 300 R 40 40 1 1 B 
X IO4 30 -300 500 300 R 40 40 1 1 B 
X IO5 31 -300 600 300 R 40 40 1 1 B 
X IO6 32 -300 700 300 R 40 40 1 1 B 
X IO7 33 -300 800 300 R 40 40 1 1 B 
X IO8 34 -300 900 300 R 40 40 1 1 B 
X IO9 35 -300 1000 300 R 40 40 1 1 B 
X IO10 36 -300 1100 300 R 40 40 1 1 B 
X IO11 37 -300 1200 300 R 40 40 1 1 B 
X IO12 38 -300 1300 300 R 40 40 1 1 B 
X IO13 39 -300 1400 300 R 40 40 1 1 B 
X IO14 40 -300 1500 300 R 40 40 1 1 B 
X IO15 41 -300 1600 300 R 40 40 1 1 B 
X IO16 45 -300 1700 300 R 40 40 1 1 B 
X IO17 46 -300 1800 300 R 40 40 1 1 B 
X IO18 47 -300 1900 300 R 40 40 1 1 B 
X IO19 48 -300 2000 300 R 40 40 1 1 B 
X IO20 49 -300 2100 300 R 40 40 1 1 B 
X IO21 50 -300 2200 300 R 40 40 1 1 B 
X IO22 51 -300 2300 300 R 40 40 1 1 B 
X IO23 52 -300 2400 300 R 40 40 1 1 B 
X IO24 53 -300 2500 300 R 40 40 1 1 B 
X IO25 54 -300 2600 300 R 40 40 1 1 B 
X IO26 55 -300 2700 300 R 40 40 1 1 B 
X IO27 56 -300 2800 300 R 40 40 1 1 B 
X IO28 57 -300 2900 300 R 40 40 1 1 B 
X IO29 58 -300 3000 300 R 40 40 1 1 B 
X IO30 59 -300 3100 300 R 40 40 1 1 B 
X IO31 60 -300 3200 300 R 40 40 1 1 B 
X IO32 68 1000 100 300 L 40 40 1 1 B 
X IO33 69 1000 200 300 L 40 40 1 1 B 
X IO34 70 1000 300 300 L 40 40 1 1 B 
X IO35 71 1000 400 300 L 40 40 1 1 B 
X IO36 72 1000 500 300 L 40 40 1 1 B 
X IO37 73 1000 600 300 L 40 40 1 1 B 
X IO38 74 1000 700 300 L 40 40 1 1 B 
X IO39 75 1000 800 300 L 40 40 1 1 B 
X IO40 76 1000 900 300 L 40 40 1 1 B 
X IO41 77 1000 1000 300 L 40 40 1 1 B 
X IO42 78 1000 1100 300 L 40 40 1 1 B 
X IO43 79 1000 1200 300 L 40 40 1 1 B 
X IO44 80 1000 1300 300 L 40 40 1 1 B 
X IO45 81 1000 1400 300 L 40 40 1 1 B 
X IO46 82 1000 1500 300 L 40 40 1 1 B 
X IO47 83 1000 1600 300 L 40 40 1 1 B 
X IO48 3 1000 1700 300 L 40 40 1 1 B 
X IO49 4 1000 1800 300 L 40 40 1 1 B 
X IO50 5 1000 1900 300 L 40 40 1 1 B 
X IO51 6 1000 2000 300 L 40 40 1 1 B 
X IO52 7 1000 2100 300 L 40 40 1 1 B 
X IO53 8 1000 2200 300 L 40 40 1 1 B 
X IO54 9 1000 2300 300 L 40 40 1 1 B 
X IO55 10 1000 2400 300 L 40 40 1 1 B 
X IO56 11 1000 2500 300 L 40 40 1 1 B 
X IO57 12 1000 2600 300 L 40 40 1 1 B 
X IO58 13 1000 2700 300 L 40 40 1 1 B 
X IO59 14 1000 2800 300 L 40 40 1 1 B 
X IO60 15 1000 2900 300 L 40 40 1 1 B 
X IO61 16 1000 3000 300 L 40 40 1 1 B 
X IO62 17 1000 3100 300 L 40 40 1 1 B 
X IO63 18 1000 3200 300 L 40 40 1 1 B 
X ISPEN/ 23 -300 3900 300 R 40 40 1 1 I I
X MODE 42 -300 3800 300 R 40 40 1 1 I 
X OE 67 -300 3500 300 R 40 40 1 1 I 
X RESET/ 24 -300 3400 300 R 40 40 1 1 I I
X SCLK 61 -300 3600 300 R 40 40 1 1 I C
X SDI 25 -300 3700 300 R 40 40 1 1 I 
X SDO 44 1000 3700 300 L 40 40 1 1 O 
# Gate Name: P
# Symbol Name: 2PWR4GND
T 1 -150 250 50 0 2 0 VCC
T 1 50 250 50 0 2 0 VCC
T 1 -350 -225 50 0 2 0 GND
T 1 -150 -225 50 0 2 0 GND
T 1 50 -225 50 0 2 0 GND
T 1 250 -225 50 0 2 0 GND
X GND@1 1 -400 -400 300 U 40 40 2 1 W 
X GND@2 22 -200 -400 300 U 40 40 2 1 W 
X GND@3 43 0 -400 300 U 40 40 2 1 W 
X GND@4 64 200 -400 300 U 40 40 2 1 W 
X VCC@1 21 -200 400 300 D 40 40 2 1 W 
X VCC@2 65 0 400 300 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISPGAL
# Package Name: PLCC-28
# Dev Tech: ''
# Dev Prefix: U
# Gate count = 2
#
DEF ISPGAL U 0 40 Y Y 2 L N
# Gate Name: A
# Symbol Name: ISPGAL
F0 "U" 0 1800 50 H V L B
F1 "ISPGAL" 0 -200 50 H V L B
F2 "lattice-PLCC-28" 0 150 50 H I C C
DRAW
P 2 1 0 0 0 0 0 1700
P 2 1 0 0 0 1700 700 1700
P 2 1 0 0 700 1700 700 0
P 2 1 0 0 700 0 0 0
X I0 3 -300 100 300 R 40 40 1 1 I 
X I1 4 -300 200 300 R 40 40 1 1 I 
X I2 5 -300 300 300 R 40 40 1 1 I 
X I3 6 -300 400 300 R 40 40 1 1 I 
X I4 7 -300 500 300 R 40 40 1 1 I 
X I5 9 -300 600 300 R 40 40 1 1 I 
X I6 10 -300 700 300 R 40 40 1 1 I 
X I7 11 -300 800 300 R 40 40 1 1 I 
X I8 12 -300 900 300 R 40 40 1 1 I 
X I9 13 -300 1000 300 R 40 40 1 1 I 
X I10 16 -300 1100 300 R 40 40 1 1 I 
X I11/CLK 2 -300 1200 300 R 40 40 1 1 I C
X IO0 17 1000 100 300 L 40 40 1 1 B 
X IO1 18 1000 200 300 L 40 40 1 1 B 
X IO2 19 1000 300 300 L 40 40 1 1 B 
X IO3 20 1000 400 300 L 40 40 1 1 B 
X IO4 21 1000 500 300 L 40 40 1 1 B 
X IO5 23 1000 600 300 L 40 40 1 1 B 
X IO6 24 1000 700 300 L 40 40 1 1 B 
X IO7 25 1000 800 300 L 40 40 1 1 B 
X IO8 26 1000 900 300 L 40 40 1 1 B 
X IO9 27 1000 1000 300 L 40 40 1 1 B 
X MODE 8 -300 1600 300 R 40 40 1 1 I 
X SCLK 1 -300 1400 300 R 40 40 1 1 I C
X SDI 15 -300 1500 300 R 40 40 1 1 I 
X SDO 22 1000 1500 300 L 40 40 1 1 O 
# Gate Name: P
# Symbol Name: PWRGND
T 1 -50 250 50 0 2 0 VCC
T 1 -50 -225 50 0 2 0 GND
X GND 14 -100 -400 300 U 40 40 2 1 W 
X VCC 28 -100 400 300 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: ISPHDR
# Package Name: 1X08
# Dev Tech: ''
# Dev Prefix: J
# Gate count = 1
#
DEF ISPHDR J 0 40 Y Y 1 L N
# Gate Name: A1
# Symbol Name: ISPHDR
F0 "J" -250 525 50 H V L B
F1 "ISPHDR" -250 -500 50 H V L B
F2 "lattice-1X08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -250 -400 50 -400
P 2 1 0 0 50 -400 50 500
P 2 1 0 0 50 500 -250 500
P 2 1 0 0 -250 500 -250 -400
T 0 175 425 50 0 1 0 Vcc
T 0 175 325 50 0 1 0 SDO
T 0 175 225 50 0 1 0 SDI
T 0 250 125 50 0 1 0 ispEN/
T 0 200 -75 50 0 1 0 MODE
T 0 175 -175 50 0 1 0 GND
T 0 200 -275 50 0 1 0 SCLK
X GND 2 -100 -200 100 R 40 40 1 1 W I
X ISPEN/ 5 -100 100 100 R 40 40 1 1 O I
X MODE 3 -100 -100 100 R 40 40 1 1 O I
X N/C 4 -100 0 100 R 40 40 1 1 U I
X SCLK 1 -100 -300 100 R 40 40 1 1 O I
X SDI 6 -100 200 100 R 40 40 1 1 O I
X SDO 7 -100 300 100 R 40 40 1 1 I I
X VCC 8 -100 400 100 R 40 40 1 1 W I
ENDDRAW
ENDDEF

#
# Dev Name: ISPRJ45
# Package Name: RJ45-90
# Dev Tech: ''
# Dev Prefix: J
# Gate count = 1
#
DEF ISPRJ45 J 0 40 Y Y 1 L N
# Gate Name: A1
# Symbol Name: ISPHDR
F0 "J" -250 525 50 H V L B
F1 "ISPRJ45" -250 -500 50 H V L B
F2 "lattice-RJ45-90" 0 150 50 H I C C
DRAW
P 2 1 0 0 -250 -400 50 -400
P 2 1 0 0 50 -400 50 500
P 2 1 0 0 50 500 -250 500
P 2 1 0 0 -250 500 -250 -400
T 0 175 425 50 0 1 0 Vcc
T 0 175 325 50 0 1 0 SDO
T 0 175 225 50 0 1 0 SDI
T 0 250 125 50 0 1 0 ispEN/
T 0 200 -75 50 0 1 0 MODE
T 0 175 -175 50 0 1 0 GND
T 0 200 -275 50 0 1 0 SCLK
X GND 7 -100 -200 100 R 40 40 1 1 W I
X ISPEN/ 4 -100 100 100 R 40 40 1 1 O I
X MODE 6 -100 -100 100 R 40 40 1 1 O I
X N/C 5 -100 0 100 R 40 40 1 1 U I
X SCLK 8 -100 -300 100 R 40 40 1 1 O I
X SDI 3 -100 200 100 R 40 40 1 1 O I
X SDO 2 -100 300 100 R 40 40 1 1 I I
X VCC 1 -100 400 100 R 40 40 1 1 W I
ENDDRAW
ENDDEF

#End Library