EESchema-LIBRARY Version 2.3  29/04/2008-12:22:54
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 2
#
# Dev Name: MC9S12NE64
# Package Name: LQFP-112
# Dev Tech: ''
# Dev Prefix: IC$1
# Gate count = 1
#
DEF MC9S12NE64 IC$1 0 40 Y Y 1 L N
# Gate Name: MC9S12
# Symbol Name: MC9S12NE64
F0 "IC$1" -300 300 50 H V L B
F1 "MC9S12NE64" -300 -400 50 H V L B
F2 "mc9s12ne64-lqfp112-LQFP-112" 0 150 50 H I C C
DRAW
P 2 1 0 0 2200 2200 -2000 2200
P 2 1 0 0 -2000 2200 -2200 2000
P 2 1 0 0 -2200 2000 -2200 -2200
P 2 1 0 0 -2200 -2200 2200 -2200
P 2 1 0 0 2200 -2200 2200 2200
C -1900 1900 100 1 1 0 N
X /IRQ_PE1 55 1300 -2400 200 U 40 40 1 1 B 
X /LSTRB_/TAGLO_PE3 53 1100 -2400 200 U 40 40 1 1 B 
X /RESET 44 200 -2400 200 U 40 40 1 1 B 
X /XIRQ_PE0 56 1400 -2400 200 U 40 40 1 1 B 
X ADDR0_DATA0_PB0 10 -2400 400 200 R 40 40 1 1 B 
X ADDR1_DATA1_PB1 11 -2400 300 200 R 40 40 1 1 B 
X ADDR2_DATA2_PB2 12 -2400 200 200 R 40 40 1 1 B 
X ADDR3_DATA3_PB3 13 -2400 100 200 R 40 40 1 1 B 
X ADDR4_DATA4_PB4 16 -2400 -200 200 R 40 40 1 1 B 
X ADDR5_DATA5_PB5 17 -2400 -300 200 R 40 40 1 1 B 
X ADDR6_DATA6_PB6 18 -2400 -400 200 R 40 40 1 1 B 
X ADDR7_DATA7_PB7 19 -2400 -500 200 R 40 40 1 1 B 
X BKGD_MODC_/TAGHI 57 2400 -1300 200 L 40 40 1 1 B 
X ECLK_PE4 41 -100 -2400 200 U 40 40 1 1 B 
X EXTAL 48 600 -2400 200 U 40 40 1 1 B 
X KWG7_PG7 29 -1300 -2400 200 U 40 40 1 1 B 
X MII-COL_KWJ3_PJ3 21 -2400 -700 200 R 40 40 1 1 B 
X MII-CRS_KWJ2_PJ2 20 -2400 -600 200 R 40 40 1 1 B 
X MII-MDC_KWJ0_PJ0 8 -2400 600 200 R 40 40 1 1 B 
X MII-MDIO_KWJ1_PJ1 9 -2400 500 200 R 40 40 1 1 B 
X MII-RXCLK_KWG4_PG4 26 -2400 -1200 200 R 40 40 1 1 B 
X MII-RXD0_KWG0_PG0 22 -2400 -800 200 R 40 40 1 1 B 
X MII-RXD1_KWG1_PG1 23 -2400 -900 200 R 40 40 1 1 B 
X MII-RXD2_KWG2_PG2 24 -2400 -1000 200 R 40 40 1 1 B 
X MII-RXD3_KWG3_PG3 25 -2400 -1100 200 R 40 40 1 1 B 
X MII-RXDV_KWG5_PG5 27 -2400 -1300 200 R 40 40 1 1 B 
X MII-RXER_KWG6_PG6 28 -2400 -1400 200 R 40 40 1 1 B 
X MII-TXCLK_KWH4_PH4 3 -2400 1100 200 R 40 40 1 1 B 
X MII-TXD0_KWH0_PH0 7 -2400 700 200 R 40 40 1 1 B 
X MII-TXD1_KWH1_PH1 6 -2400 800 200 R 40 40 1 1 B 
X MII-TXD2_KWH2_PH2 5 -2400 900 200 R 40 40 1 1 B 
X MII-TXD3_KWH3_PH3 4 -2400 1000 200 R 40 40 1 1 B 
X MII-TXEN_KWH5_PH5 2 -2400 1200 200 R 40 40 1 1 B 
X MII-TXER_KWH6_PH6 1 -2400 1300 200 R 40 40 1 1 B 
X MODA_IPIPE0_PE5 40 -200 -2400 200 U 40 40 1 1 B 
X MODB_IPIPE1_PE6 39 -300 -2400 200 U 40 40 1 1 B 
X NOACC_PE7 38 -400 -2400 200 U 40 40 1 1 B 
X PA0_ADDR8_DATA8 60 2400 -1000 200 L 40 40 1 1 B 
X PA1_ADDR9_DATA9 61 2400 -900 200 L 40 40 1 1 B 
X PA2_ADDR10_DATA10 62 2400 -800 200 L 40 40 1 1 B 
X PA3_ADDR11_DATA11 63 2400 -700 200 L 40 40 1 1 B 
X PA4_ADDR12_DATA12 77 2400 700 200 L 40 40 1 1 B 
X PA5_ADDR13_DATA13 78 2400 800 200 L 40 40 1 1 B 
X PA6_ADDR14_DATA14 79 2400 900 200 L 40 40 1 1 B 
X PA7_ADDR15_DATA15 80 2400 1000 200 L 40 40 1 1 B 
X PAD0_AN0 85 1400 2400 200 D 40 40 1 1 B 
X PAD1_AN1 86 1300 2400 200 D 40 40 1 1 B 
X PAD2_AN2 87 1200 2400 200 D 40 40 1 1 B 
X PAD3_AN3 88 1100 2400 200 D 40 40 1 1 B 
X PAD4_AN4 89 1000 2400 200 D 40 40 1 1 B 
X PAD5_AN5 90 900 2400 200 D 40 40 1 1 B 
X PAD6_AN6 91 800 2400 200 D 40 40 1 1 B 
X PAD7_AN7 92 700 2400 200 D 40 40 1 1 B 
X PHY_RBIAS 66 2400 -400 200 L 40 40 1 1 B 
X PHY_RXN 74 2400 400 200 L 40 40 1 1 B 
X PHY_RXP 73 2400 300 200 L 40 40 1 1 B 
X PHY_TXN 71 2400 100 200 L 40 40 1 1 B 
X PHY_TXP 70 2400 0 200 L 40 40 1 1 B 
X PHY_VDDA 68 2400 -200 200 L 40 40 1 1 W 
X PHY_VDDRX 75 2400 500 200 L 40 40 1 1 W 
X PHY_VDDTX 69 2400 -100 200 L 40 40 1 1 W 
X PHY_VSSA 67 2400 -300 200 L 40 40 1 1 W 
X PHY_VSSRX 76 2400 600 200 L 40 40 1 1 W 
X PHY_VSSTX 72 2400 200 200 L 40 40 1 1 W 
X PJ6_KWJ6_IIC-SDA 112 -1300 2400 200 D 40 40 1 1 B 
X PJ7_KWJ7_IIC-SCL 111 -1200 2400 200 D 40 40 1 1 B 
X PK0_XADDR14 97 200 2400 200 D 40 40 1 1 B 
X PK1_XADDR15 98 100 2400 200 D 40 40 1 1 B 
X PK2_XADDR16 99 0 2400 200 D 40 40 1 1 B 
X PK3_XADDR17 100 -100 2400 200 D 40 40 1 1 B 
X PK4_XADDR18 103 -400 2400 200 D 40 40 1 1 B 
X PK5_XADDR19 104 -500 2400 200 D 40 40 1 1 B 
X PK6_/XCS 105 -600 2400 200 D 40 40 1 1 B 
X PK7_/ECS_ROMCTL 106 -700 2400 200 D 40 40 1 1 B 
X PL0_ACTLED 84 2400 1400 200 L 40 40 1 1 B 
X PL1_LNKLED 83 2400 1300 200 L 40 40 1 1 B 
X PL2_SPDLED 81 2400 1100 200 L 40 40 1 1 B 
X PL3_DUPLED 59 2400 -1100 200 L 40 40 1 1 B 
X PL4_COLLED 58 2400 -1200 200 L 40 40 1 1 B 
X PL5 52 1000 -2400 200 U 40 40 1 1 B 
X PL6 51 900 -2400 200 U 40 40 1 1 B 
X PT4_TIM-IOC4 110 -1100 2400 200 D 40 40 1 1 B 
X PT5_TIM-IOC5 109 -1000 2400 200 D 40 40 1 1 B 
X PT6_TIM-IOC6 108 -900 2400 200 D 40 40 1 1 B 
X PT7_TIM-IOC7 107 -800 2400 200 D 40 40 1 1 B 
X R_/W/PE2 54 1200 -2400 200 U 40 40 1 1 B 
X SCI0-RXD_PS0 30 -1200 -2400 200 U 40 40 1 1 B 
X SCI0-TXD_PS1 31 -1100 -2400 200 U 40 40 1 1 B 
X SCI1-RXD_PS2 32 -1000 -2400 200 U 40 40 1 1 B 
X SCI1-TXD_PS3 33 -900 -2400 200 U 40 40 1 1 B 
X SPI-/SS_PS7 37 -500 -2400 200 U 40 40 1 1 B 
X SPI-MISO_PS4 34 -800 -2400 200 U 40 40 1 1 B 
X SPI-MOSI_PS5 35 -700 -2400 200 U 40 40 1 1 B 
X SPI-SCK_PS6 36 -600 -2400 200 U 40 40 1 1 B 
X TEST 50 800 -2400 200 U 40 40 1 1 B 
X VDD1 102 -300 2400 200 D 40 40 1 1 W 
X VDD2 65 2400 -500 200 L 40 40 1 1 W 
X VDDA 93 600 2400 200 D 40 40 1 1 W 
X VDDPLL 45 300 -2400 200 U 40 40 1 1 W 
X VDDR 82 2400 1200 200 L 40 40 1 1 W 
X VDDX1 14 -2400 0 200 R 40 40 1 1 W 
X VDDX2 43 100 -2400 200 U 40 40 1 1 W 
X VRH 94 500 2400 200 D 40 40 1 1 W 
X VRL 95 400 2400 200 D 40 40 1 1 W 
X VSS1 101 -200 2400 200 D 40 40 1 1 W 
X VSS2 64 2400 -600 200 L 40 40 1 1 W 
X VSSA 96 300 2400 200 D 40 40 1 1 W 
X VSSPLL 47 500 -2400 200 U 40 40 1 1 W 
X VSSX1 15 -2400 -100 200 R 40 40 1 1 W 
X VSSX2 42 0 -2400 200 U 40 40 1 1 W 
X XFC 46 400 -2400 200 U 40 40 1 1 B 
X XTAL 49 700 -2400 200 U 40 40 1 1 B 
ENDDRAW
ENDDEF

#
# Dev Name: MC9S12NE64-SEGREG.
# Package Name: LQFP-112
# Dev Tech: ''
# Dev Prefix: IC$1
# Gate count = 1
#
DEF MC9S12NE64-SEGREG. IC$1 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MC9S12NE64-SEGREG.
F0 "IC$1" -300 400 50 H V L B
F1 "MC9S12NE64-SEGREG." -300 -700 50 H V L B
F2 "mc9s12ne64-lqfp112-LQFP-112" 0 150 50 H I C C
DRAW
P 2 1 0 0 1400 4000 -1500 4000
P 2 1 0 0 -1500 4000 -1500 -4400
P 2 1 0 0 -1500 -4400 1400 -4400
P 2 1 0 0 1400 -4400 1400 4000
X /IRQ_PE1 55 1600 1900 200 L 40 40 1 1 B 
X /LSTRB_/TAGLO_PE3 53 1600 1700 200 L 40 40 1 1 B 
X /RESET 44 -1700 3200 200 R 40 40 1 1 B 
X /XIRQ_PE0 56 1600 2000 200 L 40 40 1 1 B 
X ADDR0_DATA0_PB0 10 1600 2900 200 L 40 40 1 1 B 
X ADDR1_DATA1_PB1 11 1600 2800 200 L 40 40 1 1 B 
X ADDR2_DATA2_PB2 12 1600 2700 200 L 40 40 1 1 B 
X ADDR3_DATA3_PB3 13 1600 2600 200 L 40 40 1 1 B 
X ADDR4_DATA4_PB4 16 1600 2500 200 L 40 40 1 1 B 
X ADDR5_DATA5_PB5 17 1600 2400 200 L 40 40 1 1 B 
X ADDR6_DATA6_PB6 18 1600 2300 200 L 40 40 1 1 B 
X ADDR7_DATA7_PB7 19 1600 2200 200 L 40 40 1 1 B 
X BKGD_MODC_/TAGHI 57 -1700 -1900 200 R 40 40 1 1 B 
X ECLK_PE4 41 1600 1600 200 L 40 40 1 1 B 
X EXTAL 48 -1700 2500 200 R 40 40 1 1 B 
X KWG7_PG7 29 1600 400 200 L 40 40 1 1 B 
X MII-COL_KWJ3_PJ3 21 1600 -900 200 L 40 40 1 1 B 
X MII-CRS_KWJ2_PJ2 20 1600 -800 200 L 40 40 1 1 B 
X MII-MDC_KWJ0_PJ0 8 1600 -600 200 L 40 40 1 1 B 
X MII-MDIO_KWJ1_PJ1 9 1600 -700 200 L 40 40 1 1 B 
X MII-RXCLK_KWG4_PG4 26 1600 700 200 L 40 40 1 1 B 
X MII-RXD0_KWG0_PG0 22 1600 1100 200 L 40 40 1 1 B 
X MII-RXD1_KWG1_PG1 23 1600 1000 200 L 40 40 1 1 B 
X MII-RXD2_KWG2_PG2 24 1600 900 200 L 40 40 1 1 B 
X MII-RXD3_KWG3_PG3 25 1600 800 200 L 40 40 1 1 B 
X MII-RXDV_KWG5_PG5 27 1600 600 200 L 40 40 1 1 B 
X MII-RXER_KWG6_PG6 28 1600 500 200 L 40 40 1 1 B 
X MII-TXCLK_KWH4_PH4 3 1600 -200 200 L 40 40 1 1 B 
X MII-TXD0_KWH0_PH0 7 1600 200 200 L 40 40 1 1 B 
X MII-TXD1_KWH1_PH1 6 1600 100 200 L 40 40 1 1 B 
X MII-TXD2_KWH2_PH2 5 1600 0 200 L 40 40 1 1 B 
X MII-TXD3_KWH3_PH3 4 1600 -100 200 L 40 40 1 1 B 
X MII-TXEN_KWH5_PH5 2 1600 -300 200 L 40 40 1 1 B 
X MII-TXER_KWH6_PH6 1 1600 -400 200 L 40 40 1 1 B 
X MODA_IPIPE0_PE5 40 1600 1500 200 L 40 40 1 1 B 
X MODB_IPIPE1_PE6 39 1600 1400 200 L 40 40 1 1 B 
X NOACC_PE7 38 1600 1300 200 L 40 40 1 1 B 
X PA0_ADDR8_DATA8 60 1600 3800 200 L 40 40 1 1 B 
X PA1_ADDR9_DATA9 61 1600 3700 200 L 40 40 1 1 B 
X PA2_ADDR10_DATA10 62 1600 3600 200 L 40 40 1 1 B 
X PA3_ADDR11_DATA11 63 1600 3500 200 L 40 40 1 1 B 
X PA4_ADDR12_DATA12 77 1600 3400 200 L 40 40 1 1 B 
X PA5_ADDR13_DATA13 78 1600 3300 200 L 40 40 1 1 B 
X PA6_ADDR14_DATA14 79 1600 3200 200 L 40 40 1 1 B 
X PA7_ADDR15_DATA15 80 1600 3100 200 L 40 40 1 1 B 
X PAD0_AN0 85 -1700 1900 200 R 40 40 1 1 B 
X PAD1_AN1 86 -1700 1800 200 R 40 40 1 1 B 
X PAD2_AN2 87 -1700 1700 200 R 40 40 1 1 B 
X PAD3_AN3 88 -1700 1600 200 R 40 40 1 1 B 
X PAD4_AN4 89 -1700 1500 200 R 40 40 1 1 B 
X PAD5_AN5 90 -1700 1400 200 R 40 40 1 1 B 
X PAD6_AN6 91 -1700 1300 200 R 40 40 1 1 B 
X PAD7_AN7 92 -1700 1200 200 R 40 40 1 1 B 
X PHY_RBIAS 66 -1700 0 200 R 40 40 1 1 B 
X PHY_RXN 74 -1700 -1100 200 R 40 40 1 1 B 
X PHY_RXP 73 -1700 -500 200 R 40 40 1 1 B 
X PHY_TXN 71 -1700 -1300 200 R 40 40 1 1 B 
X PHY_TXP 70 -1700 -700 200 R 40 40 1 1 B 
X PHY_VDDA 68 -1200 4200 200 D 40 40 1 1 W 
X PHY_VDDRX 75 -1000 4200 200 D 40 40 1 1 W 
X PHY_VDDTX 69 -800 4200 200 D 40 40 1 1 W 
X PHY_VSSA 67 -1200 -4600 200 U 40 40 1 1 W 
X PHY_VSSRX 76 -1000 -4600 200 U 40 40 1 1 W 
X PHY_VSSTX 72 -800 -4600 200 U 40 40 1 1 W 
X PJ6_KWJ6_IIC-SDA 112 1600 -1000 200 L 40 40 1 1 B 
X PJ7_KWJ7_IIC-SCL 111 1600 -1100 200 L 40 40 1 1 B 
X PK0_XADDR14 97 1600 -1300 200 L 40 40 1 1 B 
X PK1_XADDR15 98 1600 -1400 200 L 40 40 1 1 B 
X PK2_XADDR16 99 1600 -1500 200 L 40 40 1 1 B 
X PK3_XADDR17 100 1600 -1600 200 L 40 40 1 1 B 
X PK4_XADDR18 103 1600 -1700 200 L 40 40 1 1 B 
X PK5_XADDR19 104 1600 -1800 200 L 40 40 1 1 B 
X PK6_/XCS 105 1600 -1900 200 L 40 40 1 1 B 
X PK7_/ECS_ROMCTL 106 1600 -2000 200 L 40 40 1 1 B 
X PL0_ACTLED 84 1600 -3100 200 L 40 40 1 1 B 
X PL1_LNKLED 83 1600 -3200 200 L 40 40 1 1 B 
X PL2_SPDLED 81 1600 -3300 200 L 40 40 1 1 B 
X PL3_DUPLED 59 1600 -3400 200 L 40 40 1 1 B 
X PL4_COLLED 58 1600 -3500 200 L 40 40 1 1 B 
X PL5 52 1600 -3600 200 L 40 40 1 1 B 
X PL6 51 1600 -3700 200 L 40 40 1 1 B 
X PT4_TIM-IOC4 110 1600 -3900 200 L 40 40 1 1 B 
X PT5_TIM-IOC5 109 1600 -4000 200 L 40 40 1 1 B 
X PT6_TIM-IOC6 108 1600 -4100 200 L 40 40 1 1 B 
X PT7_TIM-IOC7 107 1600 -4200 200 L 40 40 1 1 B 
X R_/W/PE2 54 1600 1800 200 L 40 40 1 1 B 
X SCI0-RXD_PS0 30 1600 -2200 200 L 40 40 1 1 B 
X SCI0-TXD_PS1 31 1600 -2300 200 L 40 40 1 1 B 
X SCI1-RXD_PS2 32 1600 -2400 200 L 40 40 1 1 B 
X SCI1-TXD_PS3 33 1600 -2500 200 L 40 40 1 1 B 
X SPI-/SS_PS7 37 1600 -2900 200 L 40 40 1 1 B 
X SPI-MISO_PS4 34 1600 -2600 200 L 40 40 1 1 B 
X SPI-MOSI_PS5 35 1600 -2700 200 L 40 40 1 1 B 
X SPI-SCK_PS6 36 1600 -2800 200 L 40 40 1 1 B 
X TEST 50 -1700 -2800 200 R 40 40 1 1 B 
X VDD1 102 -400 4200 200 D 40 40 1 1 W 
X VDD2 65 -200 4200 200 D 40 40 1 1 W 
X VDDA 93 0 4200 200 D 40 40 1 1 W 
X VDDPLL 45 600 4200 200 D 40 40 1 1 W 
X VDDR 82 800 4200 200 D 40 40 1 1 W 
X VDDX1 14 200 4200 200 D 40 40 1 1 W 
X VDDX2 43 400 4200 200 D 40 40 1 1 W 
X VRH 94 -1700 800 200 R 40 40 1 1 W 
X VRL 95 -1700 600 200 R 40 40 1 1 W 
X VSS1 101 -400 -4600 200 U 40 40 1 1 W 
X VSS2 64 -200 -4600 200 U 40 40 1 1 W 
X VSSA 96 0 -4600 200 U 40 40 1 1 W 
X VSSPLL 47 600 -4600 200 U 40 40 1 1 W 
X VSSX1 15 200 -4600 200 U 40 40 1 1 W 
X VSSX2 42 400 -4600 200 U 40 40 1 1 W 
X XFC 46 -1700 -2400 200 R 40 40 1 1 B 
X XTAL 49 -1700 2800 200 R 40 40 1 1 B 
ENDDRAW
ENDDEF

#End Library