EESchema-LIBRARY Version 2.3 29/04/2008-12:23:06 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 15 # # Dev Name: MCP42XXXP # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: IC # Gate count = 3 # DEF MCP42XXXP IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: MCP42XX F0 "IC" -400 750 50 H V L B F1 "MCP42XXXP" -400 -900 50 H V L B F2 "micro-pic18xxx-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 180 600 0 600 P 2 1 0 0 0 600 0 510 P 2 1 0 0 0 300 0 200 P 2 1 0 0 0 200 190 200 P 2 1 0 0 0 510 -50 490 P 2 1 0 0 -50 490 50 460 P 2 1 0 0 50 460 -50 420 P 2 1 0 0 -50 420 50 390 P 2 1 0 0 50 390 -50 350 P 2 1 0 0 -50 350 50 320 P 2 1 0 0 50 320 0 300 P 2 1 0 0 190 400 80 400 P 2 1 0 0 80 400 50 400 P 2 1 0 0 50 400 120 420 P 2 1 0 0 120 420 120 380 P 2 1 0 0 120 380 50 400 P 2 1 0 0 110 410 80 400 P 2 1 0 0 80 400 110 390 P 2 1 0 0 110 390 110 410 P 2 1 0 0 -400 700 -400 -800 P 2 1 0 0 -400 -800 400 -800 P 2 1 0 0 400 -800 400 700 P 2 1 0 0 400 700 -400 700 P 2 1 0 0 180 -200 0 -200 P 2 1 0 0 0 -200 0 -290 P 2 1 0 0 0 -500 0 -600 P 2 1 0 0 0 -600 190 -600 P 2 1 0 0 0 -290 -50 -310 P 2 1 0 0 -50 -310 50 -340 P 2 1 0 0 50 -340 -50 -380 P 2 1 0 0 -50 -380 50 -410 P 2 1 0 0 50 -410 -50 -450 P 2 1 0 0 -50 -450 50 -480 P 2 1 0 0 50 -480 0 -500 P 2 1 0 0 190 -400 80 -400 P 2 1 0 0 80 -400 50 -400 P 2 1 0 0 50 -400 120 -380 P 2 1 0 0 120 -380 120 -420 P 2 1 0 0 120 -420 50 -400 P 2 1 0 0 110 -390 80 -400 P 2 1 0 0 80 -400 110 -410 P 2 1 0 0 110 -410 110 -390 P 2 1 0 0 -305 -555 -110 -555 P 2 1 0 0 -305 645 -210 645 P 2 1 0 0 -305 -155 -210 -155 X A0 8 500 600 100 L 40 40 1 1 P X A1 7 500 -200 100 L 40 40 1 1 P X B0 10 500 200 100 L 40 40 1 1 P X B1 5 500 -600 100 L 40 40 1 1 P X CS 1 -500 -200 100 R 40 40 1 1 I I X RS 11 -500 600 100 R 40 40 1 1 I I X SCK 2 -500 200 100 R 40 40 1 1 I X SHDN 12 -500 -600 100 R 40 40 1 1 I I X SI 3 -500 0 100 R 40 40 1 1 I X SO 13 500 0 100 L 40 40 1 1 O X W0 9 500 400 100 L 40 40 1 1 P X W1 6 500 -400 100 L 40 40 1 1 P # Gate Name: GND # Symbol Name: VSS X GND 4 0 -100 100 U 40 40 2 1 W # Gate Name: VCC # Symbol Name: VDD X VCC 14 0 100 100 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C242SO # Package Name: SO-28W # Dev Tech: 4 # Dev Prefix: IC # Gate count = 4 # DEF PIC18C242SO IC 0 40 Y Y 4 L N # Gate Name: G$1 # Symbol Name: ABC F0 "IC" -800 1150 50 H V L B F1 "PIC18C242SO" 100 -1000 50 H V L B F2 "micro-pic18xxx-SO-28W" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -900 P 2 1 0 0 700 -900 -800 -900 P 2 1 0 0 -800 -900 -800 1100 X CCP1/RC2 13 800 -200 100 L 40 40 1 1 B X INT/RB0 21 800 900 100 L 40 40 1 1 B X MCLR#/VPP 1 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 9 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -200 100 R 40 40 1 1 O X PGC/RB6 27 800 300 100 L 40 40 1 1 B X PGD/RB7 28 800 200 100 L 40 40 1 1 B X PGM/RB3 24 800 600 100 L 40 40 1 1 B X RA0/AN0 2 -900 700 100 R 40 40 1 1 B X RA1/AN1 3 -900 600 100 R 40 40 1 1 B X RA2/AN2 4 -900 500 100 R 40 40 1 1 B X RA3/AN3 5 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -900 300 100 R 40 40 1 1 B X RA5/AN4 7 -900 200 100 R 40 40 1 1 B X RB1 22 800 800 100 L 40 40 1 1 B X RB2 23 800 700 100 L 40 40 1 1 B X RB4 25 800 500 100 L 40 40 1 1 B X RB5 26 800 400 100 L 40 40 1 1 B X RX/RC7 18 800 -700 100 L 40 40 1 1 B X SCK/RC3 14 800 -300 100 L 40 40 1 1 B X SDI/RC4 15 800 -400 100 L 40 40 1 1 B X SDO/RC5 16 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 12 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 11 800 0 100 L 40 40 1 1 B X TX/RC6 17 800 -600 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: VDD X VCC 20 0 100 100 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VSS X GND 8 0 -100 100 U 40 40 3 1 W # Gate Name: G$4 # Symbol Name: VSS X GND 19 0 -100 100 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C242SP # Package Name: DIL28-3 # Dev Tech: 4 # Dev Prefix: IC # Gate count = 4 # DEF PIC18C242SP IC 0 40 Y Y 4 L N # Gate Name: G$1 # Symbol Name: ABC F0 "IC" -800 1150 50 H V L B F1 "PIC18C242SP" 100 -1000 50 H V L B F2 "micro-pic18xxx-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -900 P 2 1 0 0 700 -900 -800 -900 P 2 1 0 0 -800 -900 -800 1100 X CCP1/RC2 13 800 -200 100 L 40 40 1 1 B X INT/RB0 21 800 900 100 L 40 40 1 1 B X MCLR#/VPP 1 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 9 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -200 100 R 40 40 1 1 O X PGC/RB6 27 800 300 100 L 40 40 1 1 B X PGD/RB7 28 800 200 100 L 40 40 1 1 B X PGM/RB3 24 800 600 100 L 40 40 1 1 B X RA0/AN0 2 -900 700 100 R 40 40 1 1 B X RA1/AN1 3 -900 600 100 R 40 40 1 1 B X RA2/AN2 4 -900 500 100 R 40 40 1 1 B X RA3/AN3 5 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -900 300 100 R 40 40 1 1 B X RA5/AN4 7 -900 200 100 R 40 40 1 1 B X RB1 22 800 800 100 L 40 40 1 1 B X RB2 23 800 700 100 L 40 40 1 1 B X RB4 25 800 500 100 L 40 40 1 1 B X RB5 26 800 400 100 L 40 40 1 1 B X RX/RC7 18 800 -700 100 L 40 40 1 1 B X SCK/RC3 14 800 -300 100 L 40 40 1 1 B X SDI/RC4 15 800 -400 100 L 40 40 1 1 B X SDO/RC5 16 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 12 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 11 800 0 100 L 40 40 1 1 B X TX/RC6 17 800 -600 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: VDD X VCC 20 0 100 100 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VSS X GND 8 0 -100 100 U 40 40 3 1 W # Gate Name: G$4 # Symbol Name: VSS X GND 19 0 -100 100 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C252SO # Package Name: SO-28W # Dev Tech: 5 # Dev Prefix: IC # Gate count = 4 # DEF PIC18C252SO IC 0 40 Y Y 4 L N # Gate Name: G$1 # Symbol Name: ABC F0 "IC" -800 1150 50 H V L B F1 "PIC18C252SO" 100 -1000 50 H V L B F2 "micro-pic18xxx-SO-28W" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -900 P 2 1 0 0 700 -900 -800 -900 P 2 1 0 0 -800 -900 -800 1100 X CCP1/RC2 13 800 -200 100 L 40 40 1 1 B X INT/RB0 21 800 900 100 L 40 40 1 1 B X MCLR#/VPP 1 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 9 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -200 100 R 40 40 1 1 O X PGC/RB6 27 800 300 100 L 40 40 1 1 B X PGD/RB7 28 800 200 100 L 40 40 1 1 B X PGM/RB3 24 800 600 100 L 40 40 1 1 B X RA0/AN0 2 -900 700 100 R 40 40 1 1 B X RA1/AN1 3 -900 600 100 R 40 40 1 1 B X RA2/AN2 4 -900 500 100 R 40 40 1 1 B X RA3/AN3 5 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -900 300 100 R 40 40 1 1 B X RA5/AN4 7 -900 200 100 R 40 40 1 1 B X RB1 22 800 800 100 L 40 40 1 1 B X RB2 23 800 700 100 L 40 40 1 1 B X RB4 25 800 500 100 L 40 40 1 1 B X RB5 26 800 400 100 L 40 40 1 1 B X RX/RC7 18 800 -700 100 L 40 40 1 1 B X SCK/RC3 14 800 -300 100 L 40 40 1 1 B X SDI/RC4 15 800 -400 100 L 40 40 1 1 B X SDO/RC5 16 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 12 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 11 800 0 100 L 40 40 1 1 B X TX/RC6 17 800 -600 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: VDD X VCC 20 0 100 100 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VSS X GND 8 0 -100 100 U 40 40 3 1 W # Gate Name: G$4 # Symbol Name: VSS X GND 19 0 -100 100 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C252SP # Package Name: DIL28-3 # Dev Tech: 5 # Dev Prefix: IC # Gate count = 4 # DEF PIC18C252SP IC 0 40 Y Y 4 L N # Gate Name: G$1 # Symbol Name: ABC F0 "IC" -800 1150 50 H V L B F1 "PIC18C252SP" 100 -1000 50 H V L B F2 "micro-pic18xxx-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -900 P 2 1 0 0 700 -900 -800 -900 P 2 1 0 0 -800 -900 -800 1100 X CCP1/RC2 13 800 -200 100 L 40 40 1 1 B X INT/RB0 21 800 900 100 L 40 40 1 1 B X MCLR#/VPP 1 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 9 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -200 100 R 40 40 1 1 O X PGC/RB6 27 800 300 100 L 40 40 1 1 B X PGD/RB7 28 800 200 100 L 40 40 1 1 B X PGM/RB3 24 800 600 100 L 40 40 1 1 B X RA0/AN0 2 -900 700 100 R 40 40 1 1 B X RA1/AN1 3 -900 600 100 R 40 40 1 1 B X RA2/AN2 4 -900 500 100 R 40 40 1 1 B X RA3/AN3 5 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -900 300 100 R 40 40 1 1 B X RA5/AN4 7 -900 200 100 R 40 40 1 1 B X RB1 22 800 800 100 L 40 40 1 1 B X RB2 23 800 700 100 L 40 40 1 1 B X RB4 25 800 500 100 L 40 40 1 1 B X RB5 26 800 400 100 L 40 40 1 1 B X RX/RC7 18 800 -700 100 L 40 40 1 1 B X SCK/RC3 14 800 -300 100 L 40 40 1 1 B X SDI/RC4 15 800 -400 100 L 40 40 1 1 B X SDO/RC5 16 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 12 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 11 800 0 100 L 40 40 1 1 B X TX/RC6 17 800 -600 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: VDD X VCC 20 0 100 100 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: VSS X GND 8 0 -100 100 U 40 40 3 1 W # Gate Name: G$4 # Symbol Name: VSS X GND 19 0 -100 100 U 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C442L # Package Name: PLCC-44 # Dev Tech: 4 # Dev Prefix: IC # Gate count = 3 # DEF PIC18C442L IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: ABCDE F0 "IC" -800 1150 50 H V L B F1 "PIC18C442L" 100 -1400 50 H V L B F2 "micro-pic18xxx-PLCC-44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -1300 P 2 1 0 0 700 -1300 -800 -1300 P 2 1 0 0 -800 -1300 -800 1100 P 2 1 0 0 -705 945 -510 945 X CCP1/RC2 19 800 -200 100 L 40 40 1 1 B X CS#/AN7/RE2 11 800 -1100 100 L 40 40 1 1 B X INT/RB0 36 800 900 100 L 40 40 1 1 B X MCLR#/VPP 2 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 14 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 15 -900 -200 100 R 40 40 1 1 O X PGC/RB6 43 800 300 100 L 40 40 1 1 B X PGD/RB7 44 800 200 100 L 40 40 1 1 B X PGM/RB3 39 800 600 100 L 40 40 1 1 B X RA0/AN0 3 -900 700 100 R 40 40 1 1 B X RA1/AN1 4 -900 600 100 R 40 40 1 1 B X RA2/AN2 5 -900 500 100 R 40 40 1 1 B X RA3/AN3 6 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 7 -900 300 100 R 40 40 1 1 B X RA5/AN4 8 -900 200 100 R 40 40 1 1 B X RB1 37 800 800 100 L 40 40 1 1 B X RB2 38 800 700 100 L 40 40 1 1 B X RB4 41 800 500 100 L 40 40 1 1 B X RB5 42 800 400 100 L 40 40 1 1 B X RD#/AN5/RE0 9 800 -900 100 L 40 40 1 1 B X RD0/PSP0 21 -900 -400 100 R 40 40 1 1 B X RD1/PSP1 22 -900 -500 100 R 40 40 1 1 B X RD2/PSP2 23 -900 -600 100 R 40 40 1 1 B X RD3/PSP3 24 -900 -700 100 R 40 40 1 1 B X RD4/PSP4 30 -900 -800 100 R 40 40 1 1 B X RD5/PSP5 31 -900 -900 100 R 40 40 1 1 B X RD6/PSP6 32 -900 -1000 100 R 40 40 1 1 B X RD7/PSP7 33 -900 -1100 100 R 40 40 1 1 B X RX/RC7 29 800 -700 100 L 40 40 1 1 B X SCK/RC3 20 800 -300 100 L 40 40 1 1 B X SDI/RC4 25 800 -400 100 L 40 40 1 1 B X SDO/RC5 26 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 18 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 16 800 0 100 L 40 40 1 1 B X TX/RC6 27 800 -600 100 L 40 40 1 1 B X WR#/AN6/RE1 10 800 -1000 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: GNDVCC T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 13 0 -300 200 U 40 40 2 1 W X VCC 12 0 300 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: GNDVCC T 1 50 -155 50 0 3 0 GND T 1 50 175 50 0 3 0 VCC X GND 34 0 -300 200 U 40 40 3 1 W X VCC 35 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C442P # Package Name: DIL40 # Dev Tech: 4 # Dev Prefix: IC # Gate count = 3 # DEF PIC18C442P IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: ABCDE F0 "IC" -800 1150 50 H V L B F1 "PIC18C442P" 100 -1400 50 H V L B F2 "micro-pic18xxx-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -1300 P 2 1 0 0 700 -1300 -800 -1300 P 2 1 0 0 -800 -1300 -800 1100 P 2 1 0 0 -705 945 -510 945 X CCP1/RC2 17 800 -200 100 L 40 40 1 1 B X CS#/AN7/RE2 10 800 -1100 100 L 40 40 1 1 B X INT/RB0 33 800 900 100 L 40 40 1 1 B X MCLR#/VPP 1 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 13 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 14 -900 -200 100 R 40 40 1 1 O X PGC/RB6 39 800 300 100 L 40 40 1 1 B X PGD/RB7 40 800 200 100 L 40 40 1 1 B X PGM/RB3 36 800 600 100 L 40 40 1 1 B X RA0/AN0 2 -900 700 100 R 40 40 1 1 B X RA1/AN1 3 -900 600 100 R 40 40 1 1 B X RA2/AN2 4 -900 500 100 R 40 40 1 1 B X RA3/AN3 5 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -900 300 100 R 40 40 1 1 B X RA5/AN4 7 -900 200 100 R 40 40 1 1 B X RB1 34 800 800 100 L 40 40 1 1 B X RB2 35 800 700 100 L 40 40 1 1 B X RB4 37 800 500 100 L 40 40 1 1 B X RB5 38 800 400 100 L 40 40 1 1 B X RD#/AN5/RE0 8 800 -900 100 L 40 40 1 1 B X RD0/PSP0 19 -900 -400 100 R 40 40 1 1 B X RD1/PSP1 20 -900 -500 100 R 40 40 1 1 B X RD2/PSP2 21 -900 -600 100 R 40 40 1 1 B X RD3/PSP3 22 -900 -700 100 R 40 40 1 1 B X RD4/PSP4 27 -900 -800 100 R 40 40 1 1 B X RD5/PSP5 28 -900 -900 100 R 40 40 1 1 B X RD6/PSP6 29 -900 -1000 100 R 40 40 1 1 B X RD7/PSP7 30 -900 -1100 100 R 40 40 1 1 B X RX/RC7 26 800 -700 100 L 40 40 1 1 B X SCK/RC3 18 800 -300 100 L 40 40 1 1 B X SDI/RC4 23 800 -400 100 L 40 40 1 1 B X SDO/RC5 24 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 16 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 15 800 0 100 L 40 40 1 1 B X TX/RC6 25 800 -600 100 L 40 40 1 1 B X WR#/AN6/RE1 9 800 -1000 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: GNDVCC T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 12 0 -300 200 U 40 40 2 1 W X VCC 11 0 300 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: GNDVCC T 1 50 -155 50 0 3 0 GND T 1 50 175 50 0 3 0 VCC X GND 31 0 -300 200 U 40 40 3 1 W X VCC 32 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C442PT # Package Name: TQFP44 # Dev Tech: 4 # Dev Prefix: IC # Gate count = 3 # DEF PIC18C442PT IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: ABCDE F0 "IC" -800 1150 50 H V L B F1 "PIC18C442PT" 100 -1400 50 H V L B F2 "micro-pic18xxx-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -1300 P 2 1 0 0 700 -1300 -800 -1300 P 2 1 0 0 -800 -1300 -800 1100 P 2 1 0 0 -705 945 -510 945 X CCP1/RC2 36 800 -200 100 L 40 40 1 1 B X CS#/AN7/RE2 27 800 -1100 100 L 40 40 1 1 B X INT/RB0 8 800 900 100 L 40 40 1 1 B X MCLR#/VPP 18 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 30 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 31 -900 -200 100 R 40 40 1 1 O X PGC/RB6 16 800 300 100 L 40 40 1 1 B X PGD/RB7 17 800 200 100 L 40 40 1 1 B X PGM/RB3 11 800 600 100 L 40 40 1 1 B X RA0/AN0 19 -900 700 100 R 40 40 1 1 B X RA1/AN1 20 -900 600 100 R 40 40 1 1 B X RA2/AN2 21 -900 500 100 R 40 40 1 1 B X RA3/AN3 22 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 23 -900 300 100 R 40 40 1 1 B X RA5/AN4 24 -900 200 100 R 40 40 1 1 B X RB1 9 800 800 100 L 40 40 1 1 B X RB2 10 800 700 100 L 40 40 1 1 B X RB4 14 800 500 100 L 40 40 1 1 B X RB5 15 800 400 100 L 40 40 1 1 B X RD#/AN5/RE0 25 800 -900 100 L 40 40 1 1 B X RD0/PSP0 38 -900 -400 100 R 40 40 1 1 B X RD1/PSP1 39 -900 -500 100 R 40 40 1 1 B X RD2/PSP2 40 -900 -600 100 R 40 40 1 1 B X RD3/PSP3 41 -900 -700 100 R 40 40 1 1 B X RD4/PSP4 2 -900 -800 100 R 40 40 1 1 B X RD5/PSP5 3 -900 -900 100 R 40 40 1 1 B X RD6/PSP6 4 -900 -1000 100 R 40 40 1 1 B X RD7/PSP7 5 -900 -1100 100 R 40 40 1 1 B X RX/RC7 1 800 -700 100 L 40 40 1 1 B X SCK/RC3 37 800 -300 100 L 40 40 1 1 B X SDI/RC4 42 800 -400 100 L 40 40 1 1 B X SDO/RC5 43 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 35 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 32 800 0 100 L 40 40 1 1 B X TX/RC6 44 800 -600 100 L 40 40 1 1 B X WR#/AN6/RE1 26 800 -1000 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: GNDVCC T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 6 0 -300 200 U 40 40 2 1 W X VCC 7 0 300 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: GNDVCC T 1 50 -155 50 0 3 0 GND T 1 50 175 50 0 3 0 VCC X GND 29 0 -300 200 U 40 40 3 1 W X VCC 28 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C452L # Package Name: PLCC-44 # Dev Tech: 5 # Dev Prefix: IC # Gate count = 3 # DEF PIC18C452L IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: ABCDE F0 "IC" -800 1150 50 H V L B F1 "PIC18C452L" 100 -1400 50 H V L B F2 "micro-pic18xxx-PLCC-44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -1300 P 2 1 0 0 700 -1300 -800 -1300 P 2 1 0 0 -800 -1300 -800 1100 P 2 1 0 0 -705 945 -510 945 X CCP1/RC2 19 800 -200 100 L 40 40 1 1 B X CS#/AN7/RE2 11 800 -1100 100 L 40 40 1 1 B X INT/RB0 36 800 900 100 L 40 40 1 1 B X MCLR#/VPP 2 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 14 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 15 -900 -200 100 R 40 40 1 1 O X PGC/RB6 43 800 300 100 L 40 40 1 1 B X PGD/RB7 44 800 200 100 L 40 40 1 1 B X PGM/RB3 39 800 600 100 L 40 40 1 1 B X RA0/AN0 3 -900 700 100 R 40 40 1 1 B X RA1/AN1 4 -900 600 100 R 40 40 1 1 B X RA2/AN2 5 -900 500 100 R 40 40 1 1 B X RA3/AN3 6 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 7 -900 300 100 R 40 40 1 1 B X RA5/AN4 8 -900 200 100 R 40 40 1 1 B X RB1 37 800 800 100 L 40 40 1 1 B X RB2 38 800 700 100 L 40 40 1 1 B X RB4 41 800 500 100 L 40 40 1 1 B X RB5 42 800 400 100 L 40 40 1 1 B X RD#/AN5/RE0 9 800 -900 100 L 40 40 1 1 B X RD0/PSP0 21 -900 -400 100 R 40 40 1 1 B X RD1/PSP1 22 -900 -500 100 R 40 40 1 1 B X RD2/PSP2 23 -900 -600 100 R 40 40 1 1 B X RD3/PSP3 24 -900 -700 100 R 40 40 1 1 B X RD4/PSP4 30 -900 -800 100 R 40 40 1 1 B X RD5/PSP5 31 -900 -900 100 R 40 40 1 1 B X RD6/PSP6 32 -900 -1000 100 R 40 40 1 1 B X RD7/PSP7 33 -900 -1100 100 R 40 40 1 1 B X RX/RC7 29 800 -700 100 L 40 40 1 1 B X SCK/RC3 20 800 -300 100 L 40 40 1 1 B X SDI/RC4 25 800 -400 100 L 40 40 1 1 B X SDO/RC5 26 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 18 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 16 800 0 100 L 40 40 1 1 B X TX/RC6 27 800 -600 100 L 40 40 1 1 B X WR#/AN6/RE1 10 800 -1000 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: GNDVCC T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 13 0 -300 200 U 40 40 2 1 W X VCC 12 0 300 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: GNDVCC T 1 50 -155 50 0 3 0 GND T 1 50 175 50 0 3 0 VCC X GND 34 0 -300 200 U 40 40 3 1 W X VCC 35 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C452P # Package Name: DIL40 # Dev Tech: 5 # Dev Prefix: IC # Gate count = 3 # DEF PIC18C452P IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: ABCDE F0 "IC" -800 1150 50 H V L B F1 "PIC18C452P" 100 -1400 50 H V L B F2 "micro-pic18xxx-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -1300 P 2 1 0 0 700 -1300 -800 -1300 P 2 1 0 0 -800 -1300 -800 1100 P 2 1 0 0 -705 945 -510 945 X CCP1/RC2 17 800 -200 100 L 40 40 1 1 B X CS#/AN7/RE2 10 800 -1100 100 L 40 40 1 1 B X INT/RB0 33 800 900 100 L 40 40 1 1 B X MCLR#/VPP 1 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 13 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 14 -900 -200 100 R 40 40 1 1 O X PGC/RB6 39 800 300 100 L 40 40 1 1 B X PGD/RB7 40 800 200 100 L 40 40 1 1 B X PGM/RB3 36 800 600 100 L 40 40 1 1 B X RA0/AN0 2 -900 700 100 R 40 40 1 1 B X RA1/AN1 3 -900 600 100 R 40 40 1 1 B X RA2/AN2 4 -900 500 100 R 40 40 1 1 B X RA3/AN3 5 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -900 300 100 R 40 40 1 1 B X RA5/AN4 7 -900 200 100 R 40 40 1 1 B X RB1 34 800 800 100 L 40 40 1 1 B X RB2 35 800 700 100 L 40 40 1 1 B X RB4 37 800 500 100 L 40 40 1 1 B X RB5 38 800 400 100 L 40 40 1 1 B X RD#/AN5/RE0 8 800 -900 100 L 40 40 1 1 B X RD0/PSP0 19 -900 -400 100 R 40 40 1 1 B X RD1/PSP1 20 -900 -500 100 R 40 40 1 1 B X RD2/PSP2 21 -900 -600 100 R 40 40 1 1 B X RD3/PSP3 22 -900 -700 100 R 40 40 1 1 B X RD4/PSP4 27 -900 -800 100 R 40 40 1 1 B X RD5/PSP5 28 -900 -900 100 R 40 40 1 1 B X RD6/PSP6 29 -900 -1000 100 R 40 40 1 1 B X RD7/PSP7 30 -900 -1100 100 R 40 40 1 1 B X RX/RC7 26 800 -700 100 L 40 40 1 1 B X SCK/RC3 18 800 -300 100 L 40 40 1 1 B X SDI/RC4 23 800 -400 100 L 40 40 1 1 B X SDO/RC5 24 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 16 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 15 800 0 100 L 40 40 1 1 B X TX/RC6 25 800 -600 100 L 40 40 1 1 B X WR#/AN6/RE1 9 800 -1000 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: GNDVCC T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 12 0 -300 200 U 40 40 2 1 W X VCC 11 0 300 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: GNDVCC T 1 50 -155 50 0 3 0 GND T 1 50 175 50 0 3 0 VCC X GND 31 0 -300 200 U 40 40 3 1 W X VCC 32 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: PIC18C452PT # Package Name: TQFP44 # Dev Tech: 5 # Dev Prefix: IC # Gate count = 3 # DEF PIC18C452PT IC 0 40 Y Y 3 L N # Gate Name: G$1 # Symbol Name: ABCDE F0 "IC" -800 1150 50 H V L B F1 "PIC18C452PT" 100 -1400 50 H V L B F2 "micro-pic18xxx-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1100 700 1100 P 2 1 0 0 700 1100 700 -1300 P 2 1 0 0 700 -1300 -800 -1300 P 2 1 0 0 -800 -1300 -800 1100 P 2 1 0 0 -705 945 -510 945 X CCP1/RC2 36 800 -200 100 L 40 40 1 1 B X CS#/AN7/RE2 27 800 -1100 100 L 40 40 1 1 B X INT/RB0 8 800 900 100 L 40 40 1 1 B X MCLR#/VPP 18 -900 900 100 R 40 40 1 1 I X OSC1/CLKIN 30 -900 0 100 R 40 40 1 1 I X OSC2/CLKOUT 31 -900 -200 100 R 40 40 1 1 O X PGC/RB6 16 800 300 100 L 40 40 1 1 B X PGD/RB7 17 800 200 100 L 40 40 1 1 B X PGM/RB3 11 800 600 100 L 40 40 1 1 B X RA0/AN0 19 -900 700 100 R 40 40 1 1 B X RA1/AN1 20 -900 600 100 R 40 40 1 1 B X RA2/AN2 21 -900 500 100 R 40 40 1 1 B X RA3/AN3 22 -900 400 100 R 40 40 1 1 B X RA4/T0CKI 23 -900 300 100 R 40 40 1 1 B X RA5/AN4 24 -900 200 100 R 40 40 1 1 B X RB1 9 800 800 100 L 40 40 1 1 B X RB2 10 800 700 100 L 40 40 1 1 B X RB4 14 800 500 100 L 40 40 1 1 B X RB5 15 800 400 100 L 40 40 1 1 B X RD#/AN5/RE0 25 800 -900 100 L 40 40 1 1 B X RD0/PSP0 38 -900 -400 100 R 40 40 1 1 B X RD1/PSP1 39 -900 -500 100 R 40 40 1 1 B X RD2/PSP2 40 -900 -600 100 R 40 40 1 1 B X RD3/PSP3 41 -900 -700 100 R 40 40 1 1 B X RD4/PSP4 2 -900 -800 100 R 40 40 1 1 B X RD5/PSP5 3 -900 -900 100 R 40 40 1 1 B X RD6/PSP6 4 -900 -1000 100 R 40 40 1 1 B X RD7/PSP7 5 -900 -1100 100 R 40 40 1 1 B X RX/RC7 1 800 -700 100 L 40 40 1 1 B X SCK/RC3 37 800 -300 100 L 40 40 1 1 B X SDI/RC4 42 800 -400 100 L 40 40 1 1 B X SDO/RC5 43 800 -500 100 L 40 40 1 1 B X T1OSI/RC1 35 800 -100 100 L 40 40 1 1 B X T1OSO/RC0 32 800 0 100 L 40 40 1 1 B X TX/RC6 44 800 -600 100 L 40 40 1 1 B X WR#/AN6/RE1 26 800 -1000 100 L 40 40 1 1 B # Gate Name: G$2 # Symbol Name: GNDVCC T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 6 0 -300 200 U 40 40 2 1 W X VCC 7 0 300 200 D 40 40 2 1 W # Gate Name: G$3 # Symbol Name: GNDVCC T 1 50 -155 50 0 3 0 GND T 1 50 175 50 0 3 0 VCC X GND 29 0 -300 200 U 40 40 3 1 W X VCC 28 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: PIC18F010P # Package Name: DIL8 # Dev Tech: 1 # Dev Prefix: IC # Gate count = 1 # DEF PIC18F010P IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC180X0 F0 "IC" -400 450 50 H V L B F1 "PIC18F010P" -400 -500 50 H V L B F2 "micro-pic18xxx-DIL8" 0 150 50 H I C C DRAW P 2 1 0 0 -400 400 400 400 P 2 1 0 0 400 400 400 -400 P 2 1 0 0 400 -400 -400 -400 P 2 1 0 0 -400 -400 -400 400 T 0 65 335 70 0 1 0 VDD T 0 75 -335 70 0 1 0 VSS X RB0 7 500 200 100 L 40 40 1 1 I X RB1 6 500 0 100 L 40 40 1 1 O X RB2 5 500 -200 100 L 40 40 1 1 T X RB3 4 -500 -200 100 R 40 40 1 1 I X RB4 3 -500 0 100 R 40 40 1 1 I X RB5 2 -500 200 100 R 40 40 1 1 I X VDD 1 100 500 100 D 40 40 1 1 W X VSS 8 100 -500 100 U 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC18F010SN # Package Name: SO-08 # Dev Tech: 1 # Dev Prefix: IC # Gate count = 1 # DEF PIC18F010SN IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC180X0 F0 "IC" -400 450 50 H V L B F1 "PIC18F010SN" -400 -500 50 H V L B F2 "micro-pic18xxx-SO-08" 0 150 50 H I C C DRAW P 2 1 0 0 -400 400 400 400 P 2 1 0 0 400 400 400 -400 P 2 1 0 0 400 -400 -400 -400 P 2 1 0 0 -400 -400 -400 400 T 0 65 335 70 0 1 0 VDD T 0 75 -335 70 0 1 0 VSS X RB0 7 500 200 100 L 40 40 1 1 I X RB1 6 500 0 100 L 40 40 1 1 O X RB2 5 500 -200 100 L 40 40 1 1 T X RB3 4 -500 -200 100 R 40 40 1 1 I X RB4 3 -500 0 100 R 40 40 1 1 I X RB5 2 -500 200 100 R 40 40 1 1 I X VDD 1 100 500 100 D 40 40 1 1 W X VSS 8 100 -500 100 U 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC18F020P # Package Name: DIL8 # Dev Tech: 2 # Dev Prefix: IC # Gate count = 1 # DEF PIC18F020P IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC180X0 F0 "IC" -400 450 50 H V L B F1 "PIC18F020P" -400 -500 50 H V L B F2 "micro-pic18xxx-DIL8" 0 150 50 H I C C DRAW P 2 1 0 0 -400 400 400 400 P 2 1 0 0 400 400 400 -400 P 2 1 0 0 400 -400 -400 -400 P 2 1 0 0 -400 -400 -400 400 T 0 65 335 70 0 1 0 VDD T 0 75 -335 70 0 1 0 VSS X RB0 7 500 200 100 L 40 40 1 1 I X RB1 6 500 0 100 L 40 40 1 1 O X RB2 5 500 -200 100 L 40 40 1 1 T X RB3 4 -500 -200 100 R 40 40 1 1 I X RB4 3 -500 0 100 R 40 40 1 1 I X RB5 2 -500 200 100 R 40 40 1 1 I X VDD 1 100 500 100 D 40 40 1 1 W X VSS 8 100 -500 100 U 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC18F020SN # Package Name: SO-08 # Dev Tech: 2 # Dev Prefix: IC # Gate count = 1 # DEF PIC18F020SN IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC180X0 F0 "IC" -400 450 50 H V L B F1 "PIC18F020SN" -400 -500 50 H V L B F2 "micro-pic18xxx-SO-08" 0 150 50 H I C C DRAW P 2 1 0 0 -400 400 400 400 P 2 1 0 0 400 400 400 -400 P 2 1 0 0 400 -400 -400 -400 P 2 1 0 0 -400 -400 -400 400 T 0 65 335 70 0 1 0 VDD T 0 75 -335 70 0 1 0 VSS X RB0 7 500 200 100 L 40 40 1 1 I X RB1 6 500 0 100 L 40 40 1 1 O X RB2 5 500 -200 100 L 40 40 1 1 T X RB3 4 -500 -200 100 R 40 40 1 1 I X RB4 3 -500 0 100 R 40 40 1 1 I X RB5 2 -500 200 100 R 40 40 1 1 I X VDD 1 100 500 100 D 40 40 1 1 W X VSS 8 100 -500 100 U 40 40 1 1 W ENDDRAW ENDDEF #End Library