EESchema-LIBRARY Version 2.3 29/04/2008-12:22:55 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 7 # # Dev Name: PIC16C745JW # Package Name: DIL28-3 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF PIC16C745JW IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16C745 F0 "IC" -700 950 50 H V L B F1 "PIC16C745JW" 0 -1000 50 H V L B F2 "microchip16c7xx-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 800 900 P 2 1 0 0 800 900 800 -900 P 2 1 0 0 800 -900 -700 -900 P 2 1 0 0 -700 -900 -700 900 T 0 40 830 60 0 1 0 VDD T 0 -160 -820 60 0 1 0 VSS X CK/TX/RC6 17 900 -300 100 L 40 40 1 1 B X D+ 16 900 -600 100 L 40 40 1 1 B X D- 15 900 -700 100 L 40 40 1 1 B X DT/RX/RC7 18 900 -200 100 L 40 40 1 1 B X INT/RB0 21 900 0 100 L 40 40 1 1 B X MCLR#/VPP 1 -800 700 100 R 40 40 1 1 I X OSC1/CLKIN 9 -800 -200 100 R 40 40 1 1 I X OSC2/CLKOUT 10 -800 -300 100 R 40 40 1 1 O X RA0/AN0 2 -800 500 100 R 40 40 1 1 B X RA1/AN1 3 -800 400 100 R 40 40 1 1 B X RA2/AN2 4 -800 300 100 R 40 40 1 1 B X RA3/AN3/VREF 5 -800 200 100 R 40 40 1 1 B X RA4/T0CKI 6 -800 100 100 R 40 40 1 1 B X RA5/AN4 7 -800 0 100 R 40 40 1 1 B X RB1 22 900 100 100 L 40 40 1 1 B X RB2 23 900 200 100 L 40 40 1 1 B X RB3 24 900 300 100 L 40 40 1 1 B X RB4 25 900 400 100 L 40 40 1 1 B X RB5 26 900 500 100 L 40 40 1 1 B X RB6 27 900 600 100 L 40 40 1 1 B X RB7 28 900 700 100 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 -800 -400 100 R 40 40 1 1 B X RC1/T1OSI/CCP2 12 -800 -500 100 R 40 40 1 1 B X RC2/CCP1 13 -800 -600 100 R 40 40 1 1 B X VDD 20 0 1000 100 D 40 40 1 1 W X VSS 8 -100 -1000 100 U 40 40 1 1 W X VSS@1 19 -200 -1000 100 U 40 40 1 1 W X VUSB 14 900 -500 100 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: PIC16C745SO # Package Name: SO28-W # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF PIC16C745SO IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16C745 F0 "IC" -700 950 50 H V L B F1 "PIC16C745SO" 0 -1000 50 H V L B F2 "microchip16c7xx-SO28-W" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 800 900 P 2 1 0 0 800 900 800 -900 P 2 1 0 0 800 -900 -700 -900 P 2 1 0 0 -700 -900 -700 900 T 0 40 830 60 0 1 0 VDD T 0 -160 -820 60 0 1 0 VSS X CK/TX/RC6 17 900 -300 100 L 40 40 1 1 B X D+ 16 900 -600 100 L 40 40 1 1 B X D- 15 900 -700 100 L 40 40 1 1 B X DT/RX/RC7 18 900 -200 100 L 40 40 1 1 B X INT/RB0 21 900 0 100 L 40 40 1 1 B X MCLR#/VPP 1 -800 700 100 R 40 40 1 1 I X OSC1/CLKIN 9 -800 -200 100 R 40 40 1 1 I X OSC2/CLKOUT 10 -800 -300 100 R 40 40 1 1 O X RA0/AN0 2 -800 500 100 R 40 40 1 1 B X RA1/AN1 3 -800 400 100 R 40 40 1 1 B X RA2/AN2 4 -800 300 100 R 40 40 1 1 B X RA3/AN3/VREF 5 -800 200 100 R 40 40 1 1 B X RA4/T0CKI 6 -800 100 100 R 40 40 1 1 B X RA5/AN4 7 -800 0 100 R 40 40 1 1 B X RB1 22 900 100 100 L 40 40 1 1 B X RB2 23 900 200 100 L 40 40 1 1 B X RB3 24 900 300 100 L 40 40 1 1 B X RB4 25 900 400 100 L 40 40 1 1 B X RB5 26 900 500 100 L 40 40 1 1 B X RB6 27 900 600 100 L 40 40 1 1 B X RB7 28 900 700 100 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 -800 -400 100 R 40 40 1 1 B X RC1/T1OSI/CCP2 12 -800 -500 100 R 40 40 1 1 B X RC2/CCP1 13 -800 -600 100 R 40 40 1 1 B X VDD 20 0 1000 100 D 40 40 1 1 W X VSS 8 -100 -1000 100 U 40 40 1 1 W X VSS@1 19 -200 -1000 100 U 40 40 1 1 W X VUSB 14 900 -500 100 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: PIC16C745SP # Package Name: DIL28-3 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF PIC16C745SP IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16C745 F0 "IC" -700 950 50 H V L B F1 "PIC16C745SP" 0 -1000 50 H V L B F2 "microchip16c7xx-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 800 900 P 2 1 0 0 800 900 800 -900 P 2 1 0 0 800 -900 -700 -900 P 2 1 0 0 -700 -900 -700 900 T 0 40 830 60 0 1 0 VDD T 0 -160 -820 60 0 1 0 VSS X CK/TX/RC6 17 900 -300 100 L 40 40 1 1 B X D+ 16 900 -600 100 L 40 40 1 1 B X D- 15 900 -700 100 L 40 40 1 1 B X DT/RX/RC7 18 900 -200 100 L 40 40 1 1 B X INT/RB0 21 900 0 100 L 40 40 1 1 B X MCLR#/VPP 1 -800 700 100 R 40 40 1 1 I X OSC1/CLKIN 9 -800 -200 100 R 40 40 1 1 I X OSC2/CLKOUT 10 -800 -300 100 R 40 40 1 1 O X RA0/AN0 2 -800 500 100 R 40 40 1 1 B X RA1/AN1 3 -800 400 100 R 40 40 1 1 B X RA2/AN2 4 -800 300 100 R 40 40 1 1 B X RA3/AN3/VREF 5 -800 200 100 R 40 40 1 1 B X RA4/T0CKI 6 -800 100 100 R 40 40 1 1 B X RA5/AN4 7 -800 0 100 R 40 40 1 1 B X RB1 22 900 100 100 L 40 40 1 1 B X RB2 23 900 200 100 L 40 40 1 1 B X RB3 24 900 300 100 L 40 40 1 1 B X RB4 25 900 400 100 L 40 40 1 1 B X RB5 26 900 500 100 L 40 40 1 1 B X RB6 27 900 600 100 L 40 40 1 1 B X RB7 28 900 700 100 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 -800 -400 100 R 40 40 1 1 B X RC1/T1OSI/CCP2 12 -800 -500 100 R 40 40 1 1 B X RC2/CCP1 13 -800 -600 100 R 40 40 1 1 B X VDD 20 0 1000 100 D 40 40 1 1 W X VSS 8 -100 -1000 100 U 40 40 1 1 W X VSS@1 19 -200 -1000 100 U 40 40 1 1 W X VUSB 14 900 -500 100 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: PIC16C765JW # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF PIC16C765JW IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16C765 F0 "IC" -700 1150 50 H V L B F1 "PIC16C765JW" -100 -1400 50 H V L B F2 "microchip16c7xx-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1100 800 1100 P 2 1 0 0 800 1100 800 -1300 P 2 1 0 0 800 -1300 -700 -1300 P 2 1 0 0 -700 -1300 -700 1100 T 0 40 1030 60 0 1 0 VDD T 0 -260 -1220 60 0 1 0 VSS X D+ 24 900 -1000 100 L 40 40 1 1 B X D- 23 900 -1100 100 L 40 40 1 1 B X INT/RB0 33 900 200 100 L 40 40 1 1 B X MCLR#/VPP 1 -800 900 100 R 40 40 1 1 I X OSC1/CLKIN 13 -800 -300 100 R 40 40 1 1 I X OSC2/CLKOUT 14 -800 -400 100 R 40 40 1 1 O X PSP0/RD0 19 900 -700 100 L 40 40 1 1 B X PSP1/RD1 20 900 -600 100 L 40 40 1 1 B X PSP2/RD2 21 900 -500 100 L 40 40 1 1 B X PSP3/RD3 22 900 -400 100 L 40 40 1 1 B X PSP4/RD4 27 900 -300 100 L 40 40 1 1 B X PSP5/RD5 28 900 -200 100 L 40 40 1 1 B X PSP6/RD6 29 900 -100 100 L 40 40 1 1 B X PSP7/RD7 30 900 0 100 L 40 40 1 1 B X RA0/AN0 2 -800 700 100 R 40 40 1 1 B X RA1/AN1 3 -800 600 100 R 40 40 1 1 B X RA2/AN2 4 -800 500 100 R 40 40 1 1 B X RA3/AN3/VREF 5 -800 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -800 300 100 R 40 40 1 1 B X RA5/AN4 7 -800 200 100 R 40 40 1 1 B X RB1 34 900 300 100 L 40 40 1 1 B X RB2 35 900 400 100 L 40 40 1 1 B X RB3 36 900 500 100 L 40 40 1 1 B X RB4 37 900 600 100 L 40 40 1 1 B X RB5 38 900 700 100 L 40 40 1 1 B X RB6 39 900 800 100 L 40 40 1 1 B X RB7 40 900 900 100 L 40 40 1 1 B X RC0/T1OSO/T1CKI 15 -800 -600 100 R 40 40 1 1 B X RC1/T1OSI/CCP2 16 -800 -700 100 R 40 40 1 1 B X RC2/CCP1 17 -800 -800 100 R 40 40 1 1 B X RC6/TX/CK 25 -800 -900 100 R 40 40 1 1 B X RC7/RX/DT 26 -800 -1000 100 R 40 40 1 1 B X RE0/RD#/AN5 8 -800 100 100 R 40 40 1 1 B X RE1/WR#/AN6 9 -800 0 100 R 40 40 1 1 B X RE2/CS#/AN7 10 -800 -100 100 R 40 40 1 1 B X VDD 11 100 1200 100 D 40 40 1 1 W X VDD@1 32 0 1200 100 D 40 40 1 1 W X VSS 12 -200 -1400 100 U 40 40 1 1 W X VSS@1 31 -300 -1400 100 U 40 40 1 1 W X VUSB 18 900 -900 100 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: PIC16C765L # Package Name: PLCC-44 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF PIC16C765L IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16C765 F0 "IC" -700 1150 50 H V L B F1 "PIC16C765L" -100 -1400 50 H V L B F2 "microchip16c7xx-PLCC-44" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1100 800 1100 P 2 1 0 0 800 1100 800 -1300 P 2 1 0 0 800 -1300 -700 -1300 P 2 1 0 0 -700 -1300 -700 1100 T 0 40 1030 60 0 1 0 VDD T 0 -260 -1220 60 0 1 0 VSS X D+ 26 900 -1000 100 L 40 40 1 1 B X D- 25 900 -1100 100 L 40 40 1 1 B X INT/RB0 36 900 200 100 L 40 40 1 1 B X MCLR#/VPP 2 -800 900 100 R 40 40 1 1 I X OSC1/CLKIN 14 -800 -300 100 R 40 40 1 1 I X OSC2/CLKOUT 15 -800 -400 100 R 40 40 1 1 O X PSP0/RD0 21 900 -700 100 L 40 40 1 1 B X PSP1/RD1 22 900 -600 100 L 40 40 1 1 B X PSP2/RD2 23 900 -500 100 L 40 40 1 1 B X PSP3/RD3 24 900 -400 100 L 40 40 1 1 B X PSP4/RD4 30 900 -300 100 L 40 40 1 1 B X PSP5/RD5 31 900 -200 100 L 40 40 1 1 B X PSP6/RD6 32 900 -100 100 L 40 40 1 1 B X PSP7/RD7 33 900 0 100 L 40 40 1 1 B X RA0/AN0 3 -800 700 100 R 40 40 1 1 B X RA1/AN1 4 -800 600 100 R 40 40 1 1 B X RA2/AN2 5 -800 500 100 R 40 40 1 1 B X RA3/AN3/VREF 6 -800 400 100 R 40 40 1 1 B X RA4/T0CKI 7 -800 300 100 R 40 40 1 1 B X RA5/AN4 8 -800 200 100 R 40 40 1 1 B X RB1 37 900 300 100 L 40 40 1 1 B X RB2 38 900 400 100 L 40 40 1 1 B X RB3 39 900 500 100 L 40 40 1 1 B X RB4 41 900 600 100 L 40 40 1 1 B X RB5 42 900 700 100 L 40 40 1 1 B X RB6 43 900 800 100 L 40 40 1 1 B X RB7 44 900 900 100 L 40 40 1 1 B X RC0/T1OSO/T1CKI 16 -800 -600 100 R 40 40 1 1 B X RC1/T1OSI/CCP2 18 -800 -700 100 R 40 40 1 1 B X RC2/CCP1 19 -800 -800 100 R 40 40 1 1 B X RC6/TX/CK 27 -800 -900 100 R 40 40 1 1 B X RC7/RX/DT 29 -800 -1000 100 R 40 40 1 1 B X RE0/RD#/AN5 9 -800 100 100 R 40 40 1 1 B X RE1/WR#/AN6 10 -800 0 100 R 40 40 1 1 B X RE2/CS#/AN7 11 -800 -100 100 R 40 40 1 1 B X VDD 12 100 1200 100 D 40 40 1 1 W X VDD@1 35 0 1200 100 D 40 40 1 1 W X VSS 13 -200 -1400 100 U 40 40 1 1 W X VSS@1 34 -300 -1400 100 U 40 40 1 1 W X VUSB 20 900 -900 100 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: PIC16C765P # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF PIC16C765P IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16C765 F0 "IC" -700 1150 50 H V L B F1 "PIC16C765P" -100 -1400 50 H V L B F2 "microchip16c7xx-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1100 800 1100 P 2 1 0 0 800 1100 800 -1300 P 2 1 0 0 800 -1300 -700 -1300 P 2 1 0 0 -700 -1300 -700 1100 T 0 40 1030 60 0 1 0 VDD T 0 -260 -1220 60 0 1 0 VSS X D+ 24 900 -1000 100 L 40 40 1 1 B X D- 23 900 -1100 100 L 40 40 1 1 B X INT/RB0 33 900 200 100 L 40 40 1 1 B X MCLR#/VPP 1 -800 900 100 R 40 40 1 1 I X OSC1/CLKIN 13 -800 -300 100 R 40 40 1 1 I X OSC2/CLKOUT 14 -800 -400 100 R 40 40 1 1 O X PSP0/RD0 19 900 -700 100 L 40 40 1 1 B X PSP1/RD1 20 900 -600 100 L 40 40 1 1 B X PSP2/RD2 21 900 -500 100 L 40 40 1 1 B X PSP3/RD3 22 900 -400 100 L 40 40 1 1 B X PSP4/RD4 27 900 -300 100 L 40 40 1 1 B X PSP5/RD5 28 900 -200 100 L 40 40 1 1 B X PSP6/RD6 29 900 -100 100 L 40 40 1 1 B X PSP7/RD7 30 900 0 100 L 40 40 1 1 B X RA0/AN0 2 -800 700 100 R 40 40 1 1 B X RA1/AN1 3 -800 600 100 R 40 40 1 1 B X RA2/AN2 4 -800 500 100 R 40 40 1 1 B X RA3/AN3/VREF 5 -800 400 100 R 40 40 1 1 B X RA4/T0CKI 6 -800 300 100 R 40 40 1 1 B X RA5/AN4 7 -800 200 100 R 40 40 1 1 B X RB1 34 900 300 100 L 40 40 1 1 B X RB2 35 900 400 100 L 40 40 1 1 B X RB3 36 900 500 100 L 40 40 1 1 B X RB4 37 900 600 100 L 40 40 1 1 B X RB5 38 900 700 100 L 40 40 1 1 B X RB6 39 900 800 100 L 40 40 1 1 B X RB7 40 900 900 100 L 40 40 1 1 B X RC0/T1OSO/T1CKI 15 -800 -600 100 R 40 40 1 1 B X RC1/T1OSI/CCP2 16 -800 -700 100 R 40 40 1 1 B X RC2/CCP1 17 -800 -800 100 R 40 40 1 1 B X RC6/TX/CK 25 -800 -900 100 R 40 40 1 1 B X RC7/RX/DT 26 -800 -1000 100 R 40 40 1 1 B X RE0/RD#/AN5 8 -800 100 100 R 40 40 1 1 B X RE1/WR#/AN6 9 -800 0 100 R 40 40 1 1 B X RE2/CS#/AN7 10 -800 -100 100 R 40 40 1 1 B X VDD 11 100 1200 100 D 40 40 1 1 W X VDD@1 32 0 1200 100 D 40 40 1 1 W X VSS 12 -200 -1400 100 U 40 40 1 1 W X VSS@1 31 -300 -1400 100 U 40 40 1 1 W X VUSB 18 900 -900 100 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: PIC16C765PT # Package Name: TQFP44 # Dev Tech: '' # Dev Prefix: IC # Gate count = 1 # DEF PIC16C765PT IC 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16C765 F0 "IC" -700 1150 50 H V L B F1 "PIC16C765PT" -100 -1400 50 H V L B F2 "microchip16c7xx-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1100 800 1100 P 2 1 0 0 800 1100 800 -1300 P 2 1 0 0 800 -1300 -700 -1300 P 2 1 0 0 -700 -1300 -700 1100 T 0 40 1030 60 0 1 0 VDD T 0 -260 -1220 60 0 1 0 VSS X D+ 43 900 -1000 100 L 40 40 1 1 B X D- 42 900 -1100 100 L 40 40 1 1 B X INT/RB0 8 900 200 100 L 40 40 1 1 B X MCLR#/VPP 18 -800 900 100 R 40 40 1 1 I X OSC1/CLKIN 30 -800 -300 100 R 40 40 1 1 I X OSC2/CLKOUT 31 -800 -400 100 R 40 40 1 1 O X PSP0/RD0 38 900 -700 100 L 40 40 1 1 B X PSP1/RD1 39 900 -600 100 L 40 40 1 1 B X PSP2/RD2 40 900 -500 100 L 40 40 1 1 B X PSP3/RD3 41 900 -400 100 L 40 40 1 1 B X PSP4/RD4 2 900 -300 100 L 40 40 1 1 B X PSP5/RD5 3 900 -200 100 L 40 40 1 1 B X PSP6/RD6 4 900 -100 100 L 40 40 1 1 B X PSP7/RD7 5 900 0 100 L 40 40 1 1 B X RA0/AN0 19 -800 700 100 R 40 40 1 1 B X RA1/AN1 20 -800 600 100 R 40 40 1 1 B X RA2/AN2 21 -800 500 100 R 40 40 1 1 B X RA3/AN3/VREF 22 -800 400 100 R 40 40 1 1 B X RA4/T0CKI 23 -800 300 100 R 40 40 1 1 B X RA5/AN4 24 -800 200 100 R 40 40 1 1 B X RB1 9 900 300 100 L 40 40 1 1 B X RB2 10 900 400 100 L 40 40 1 1 B X RB3 11 900 500 100 L 40 40 1 1 B X RB4 14 900 600 100 L 40 40 1 1 B X RB5 15 900 700 100 L 40 40 1 1 B X RB6 16 900 800 100 L 40 40 1 1 B X RB7 17 900 900 100 L 40 40 1 1 B X RC0/T1OSO/T1CKI 32 -800 -600 100 R 40 40 1 1 B X RC1/T1OSI/CCP2 35 -800 -700 100 R 40 40 1 1 B X RC2/CCP1 36 -800 -800 100 R 40 40 1 1 B X RC6/TX/CK 44 -800 -900 100 R 40 40 1 1 B X RC7/RX/DT 1 -800 -1000 100 R 40 40 1 1 B X RE0/RD#/AN5 25 -800 100 100 R 40 40 1 1 B X RE1/WR#/AN6 26 -800 0 100 R 40 40 1 1 B X RE2/CS#/AN7 27 -800 -100 100 R 40 40 1 1 B X VDD 7 100 1200 100 D 40 40 1 1 W X VDD@1 28 0 1200 100 D 40 40 1 1 W X VSS 6 -200 -1400 100 U 40 40 1 1 W X VSS@1 29 -300 -1400 100 U 40 40 1 1 W X VUSB 37 900 -900 100 L 40 40 1 1 O ENDDRAW ENDDEF #End Library