EESchema-LIBRARY Version 2.3 29/04/2008-12:23:02 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 12 # # Dev Name: MCP2510P # Package Name: DIL18 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP2510P U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP2510 F0 "U" -400 650 50 H V L B F1 "MCP2510P" -400 -1150 50 H V L B F2 "microchip_can-DIL18" 0 150 50 H I C C DRAW P 2 1 0 0 -400 600 500 600 P 2 1 0 0 500 600 500 -1000 P 2 1 0 0 500 -1000 -400 -1000 P 2 1 0 0 -400 -1000 -400 600 X CLKOUT 3 700 400 200 L 40 40 1 1 O X CS 16 -600 100 200 R 40 40 1 1 I I X INT 12 700 -400 200 L 40 40 1 1 O I X OSC1 8 -600 500 200 R 40 40 1 1 I X OSC2 7 -600 400 200 R 40 40 1 1 O X RESET 17 -600 -400 200 R 40 40 1 1 I I X RX0BF 11 700 -700 200 L 40 40 1 1 O I X RX1BF 10 700 -800 200 L 40 40 1 1 O I X RXCAN 2 700 200 200 L 40 40 1 1 I X SCK 13 -600 0 200 R 40 40 1 1 I X SI 14 -600 -100 200 R 40 40 1 1 I X SO 15 -600 -200 200 R 40 40 1 1 O X TX0RTS 4 -600 -700 200 R 40 40 1 1 I I X TX1RTS 5 -600 -800 200 R 40 40 1 1 I I X TX2RTS 6 -600 -900 200 R 40 40 1 1 I I X TXCAN 1 700 0 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 18 0 300 200 D 40 40 2 1 W X VSS 9 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP2510SO # Package Name: SO-18W # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP2510SO U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP2510 F0 "U" -400 650 50 H V L B F1 "MCP2510SO" -400 -1150 50 H V L B F2 "microchip_can-SO-18W" 0 150 50 H I C C DRAW P 2 1 0 0 -400 600 500 600 P 2 1 0 0 500 600 500 -1000 P 2 1 0 0 500 -1000 -400 -1000 P 2 1 0 0 -400 -1000 -400 600 X CLKOUT 3 700 400 200 L 40 40 1 1 O X CS 16 -600 100 200 R 40 40 1 1 I I X INT 12 700 -400 200 L 40 40 1 1 O I X OSC1 8 -600 500 200 R 40 40 1 1 I X OSC2 7 -600 400 200 R 40 40 1 1 O X RESET 17 -600 -400 200 R 40 40 1 1 I I X RX0BF 11 700 -700 200 L 40 40 1 1 O I X RX1BF 10 700 -800 200 L 40 40 1 1 O I X RXCAN 2 700 200 200 L 40 40 1 1 I X SCK 13 -600 0 200 R 40 40 1 1 I X SI 14 -600 -100 200 R 40 40 1 1 I X SO 15 -600 -200 200 R 40 40 1 1 O X TX0RTS 4 -600 -700 200 R 40 40 1 1 I I X TX1RTS 5 -600 -800 200 R 40 40 1 1 I I X TX2RTS 6 -600 -900 200 R 40 40 1 1 I I X TXCAN 1 700 0 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 18 0 300 200 D 40 40 2 1 W X VSS 9 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP2551P # Package Name: DIL8 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP2551P U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP2551 F0 "U" -400 450 50 H V L B F1 "MCP2551P" -400 -500 50 H V L B F2 "microchip_can-DIL8" 0 150 50 H I C C DRAW P 2 1 0 0 -400 400 -400 -400 P 2 1 0 0 -400 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -400 400 X CANH 7 500 200 200 L 40 40 1 1 B X CANL 6 500 0 200 L 40 40 1 1 B X RS 8 -600 -200 200 R 40 40 1 1 I X RXD 4 -600 0 200 R 40 40 1 1 O X TXD 1 -600 200 200 R 40 40 1 1 I X VREF 5 500 -300 200 L 40 40 1 1 W # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 3 0 300 200 D 40 40 2 1 W X VSS 2 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP2551SN # Package Name: SO-08 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP2551SN U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP2551 F0 "U" -400 450 50 H V L B F1 "MCP2551SN" -400 -500 50 H V L B F2 "microchip_can-SO-08" 0 150 50 H I C C DRAW P 2 1 0 0 -400 400 -400 -400 P 2 1 0 0 -400 -400 300 -400 P 2 1 0 0 300 -400 300 400 P 2 1 0 0 300 400 -400 400 X CANH 7 500 200 200 L 40 40 1 1 B X CANL 6 500 0 200 L 40 40 1 1 B X RS 8 -600 -200 200 R 40 40 1 1 I X RXD 4 -600 0 200 R 40 40 1 1 O X TXD 1 -600 200 200 R 40 40 1 1 I X VREF 5 500 -300 200 L 40 40 1 1 W # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 3 0 300 200 D 40 40 2 1 W X VSS 2 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25020P # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25020P U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25020 F0 "U" -400 600 50 H V L B F1 "MCP25020P" -400 -500 50 H V L B F2 "microchip_can-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 550 700 550 P 2 1 0 0 700 550 700 -400 P 2 1 0 0 700 -400 -400 -400 P 2 1 0 0 -400 -400 -400 550 X GP0 1 900 400 200 L 40 40 1 1 B X GP1 2 900 300 200 L 40 40 1 1 B X GP2/PWM1 3 900 200 200 L 40 40 1 1 B X GP3/PWM2 4 900 100 200 L 40 40 1 1 B X GP4 5 900 0 200 L 40 40 1 1 B X GP5 6 900 -100 200 L 40 40 1 1 B X GP6/CLKOUT 10 900 -200 200 L 40 40 1 1 B X GP7/NRST/VPP 11 900 -300 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 400 200 R 40 40 1 1 I X OSC2 9 -600 300 200 R 40 40 1 1 O X RXCAN 12 -600 -200 200 R 40 40 1 1 I X TXCAN 13 -600 0 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25020SL # Package Name: SO-14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25020SL U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25020 F0 "U" -400 600 50 H V L B F1 "MCP25020SL" -400 -500 50 H V L B F2 "microchip_can-SO-14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 550 700 550 P 2 1 0 0 700 550 700 -400 P 2 1 0 0 700 -400 -400 -400 P 2 1 0 0 -400 -400 -400 550 X GP0 1 900 400 200 L 40 40 1 1 B X GP1 2 900 300 200 L 40 40 1 1 B X GP2/PWM1 3 900 200 200 L 40 40 1 1 B X GP3/PWM2 4 900 100 200 L 40 40 1 1 B X GP4 5 900 0 200 L 40 40 1 1 B X GP5 6 900 -100 200 L 40 40 1 1 B X GP6/CLKOUT 10 900 -200 200 L 40 40 1 1 B X GP7/NRST/VPP 11 900 -300 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 400 200 R 40 40 1 1 I X OSC2 9 -600 300 200 R 40 40 1 1 O X RXCAN 12 -600 -200 200 R 40 40 1 1 I X TXCAN 13 -600 0 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25025P # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25025P U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25025 F0 "U" -400 750 50 H V L B F1 "MCP25025P" -400 -400 50 H V L B F2 "microchip_can-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 700 800 700 P 2 1 0 0 800 700 800 -300 P 2 1 0 0 800 -300 -400 -300 P 2 1 0 0 -400 -300 -400 700 X GP0 1 1000 500 200 L 40 40 1 1 B X GP1 2 1000 400 200 L 40 40 1 1 B X GP2/PWM1 3 1000 300 200 L 40 40 1 1 B X GP3/PWM2 4 1000 200 200 L 40 40 1 1 B X GP4 5 1000 100 200 L 40 40 1 1 B X GP5 6 1000 0 200 L 40 40 1 1 B X GP6/CLKOUT 10 1000 -100 200 L 40 40 1 1 B X GP7/NRST/VPP 11 1000 -200 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 100 200 R 40 40 1 1 I X OSC2 9 -600 0 200 R 40 40 1 1 O X RXCAN/NC 12 -600 400 200 R 40 40 1 1 I X TXCAN/TXRXCAN 13 -600 500 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25025SL # Package Name: SO-14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25025SL U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25025 F0 "U" -400 750 50 H V L B F1 "MCP25025SL" -400 -400 50 H V L B F2 "microchip_can-SO-14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 700 800 700 P 2 1 0 0 800 700 800 -300 P 2 1 0 0 800 -300 -400 -300 P 2 1 0 0 -400 -300 -400 700 X GP0 1 1000 500 200 L 40 40 1 1 B X GP1 2 1000 400 200 L 40 40 1 1 B X GP2/PWM1 3 1000 300 200 L 40 40 1 1 B X GP3/PWM2 4 1000 200 200 L 40 40 1 1 B X GP4 5 1000 100 200 L 40 40 1 1 B X GP5 6 1000 0 200 L 40 40 1 1 B X GP6/CLKOUT 10 1000 -100 200 L 40 40 1 1 B X GP7/NRST/VPP 11 1000 -200 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 100 200 R 40 40 1 1 I X OSC2 9 -600 0 200 R 40 40 1 1 O X RXCAN/NC 12 -600 400 200 R 40 40 1 1 I X TXCAN/TXRXCAN 13 -600 500 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25050P # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25050P U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25050 F0 "U" -400 650 50 H V L B F1 "MCP25050P" -400 -500 50 H V L B F2 "microchip_can-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 600 700 600 P 2 1 0 0 700 600 700 -400 P 2 1 0 0 700 -400 -400 -400 P 2 1 0 0 -400 -400 -400 600 X GP0/AN0 1 900 400 200 L 40 40 1 1 B X GP1/AN1 2 900 300 200 L 40 40 1 1 B X GP2/AN2/PWM1 3 900 200 200 L 40 40 1 1 B X GP3/AN3/PWM2 4 900 100 200 L 40 40 1 1 B X GP4/VREF- 5 900 0 200 L 40 40 1 1 B X GP5/VREF+ 6 900 -100 200 L 40 40 1 1 B X GP6/CLKOUT 10 900 -200 200 L 40 40 1 1 B X GP7/NRST/VPP 11 900 -300 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 400 200 R 40 40 1 1 I X OSC2 9 -600 300 200 R 40 40 1 1 O X RXCAN 12 -600 -100 200 R 40 40 1 1 I X TXCAN 13 -600 0 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25050SL # Package Name: SO-14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25050SL U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25050 F0 "U" -400 650 50 H V L B F1 "MCP25050SL" -400 -500 50 H V L B F2 "microchip_can-SO-14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 600 700 600 P 2 1 0 0 700 600 700 -400 P 2 1 0 0 700 -400 -400 -400 P 2 1 0 0 -400 -400 -400 600 X GP0/AN0 1 900 400 200 L 40 40 1 1 B X GP1/AN1 2 900 300 200 L 40 40 1 1 B X GP2/AN2/PWM1 3 900 200 200 L 40 40 1 1 B X GP3/AN3/PWM2 4 900 100 200 L 40 40 1 1 B X GP4/VREF- 5 900 0 200 L 40 40 1 1 B X GP5/VREF+ 6 900 -100 200 L 40 40 1 1 B X GP6/CLKOUT 10 900 -200 200 L 40 40 1 1 B X GP7/NRST/VPP 11 900 -300 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 400 200 R 40 40 1 1 I X OSC2 9 -600 300 200 R 40 40 1 1 O X RXCAN 12 -600 -100 200 R 40 40 1 1 I X TXCAN 13 -600 0 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25055P # Package Name: DIL14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25055P U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25055 F0 "U" -400 650 50 H V L B F1 "MCP25055P" -400 -500 50 H V L B F2 "microchip_can-DIL14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 600 900 600 P 2 1 0 0 900 600 900 -400 P 2 1 0 0 900 -400 -400 -400 P 2 1 0 0 -400 -400 -400 600 X GP0/AN0 1 1100 400 200 L 40 40 1 1 B X GP1/AN1 2 1100 300 200 L 40 40 1 1 B X GP2/AN2/PWM1 3 1100 200 200 L 40 40 1 1 B X GP3/AN3/PWM2 4 1100 100 200 L 40 40 1 1 B X GP4/VREF- 5 1100 0 200 L 40 40 1 1 B X GP5/VREF+ 6 1100 -100 200 L 40 40 1 1 B X GP6/CLKOUT 10 1100 -200 200 L 40 40 1 1 B X GP7/NRST/VPP 11 1100 -300 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 0 200 R 40 40 1 1 I X OSC2 9 -600 -100 200 R 40 40 1 1 O X RXCAN/NC 12 -600 300 200 R 40 40 1 1 I X TXCAN/TXRXCAN 13 -600 400 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: MCP25055SL # Package Name: SO-14 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF MCP25055SL U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: MCP25055 F0 "U" -400 650 50 H V L B F1 "MCP25055SL" -400 -500 50 H V L B F2 "microchip_can-SO-14" 0 150 50 H I C C DRAW P 2 1 0 0 -400 600 900 600 P 2 1 0 0 900 600 900 -400 P 2 1 0 0 900 -400 -400 -400 P 2 1 0 0 -400 -400 -400 600 X GP0/AN0 1 1100 400 200 L 40 40 1 1 B X GP1/AN1 2 1100 300 200 L 40 40 1 1 B X GP2/AN2/PWM1 3 1100 200 200 L 40 40 1 1 B X GP3/AN3/PWM2 4 1100 100 200 L 40 40 1 1 B X GP4/VREF- 5 1100 0 200 L 40 40 1 1 B X GP5/VREF+ 6 1100 -100 200 L 40 40 1 1 B X GP6/CLKOUT 10 1100 -200 200 L 40 40 1 1 B X GP7/NRST/VPP 11 1100 -300 200 L 40 40 1 1 B X OSC1/CLKIN 8 -600 0 200 R 40 40 1 1 I X OSC2 9 -600 -100 200 R 40 40 1 1 O X RXCAN/NC 12 -600 300 200 R 40 40 1 1 I X TXCAN/TXRXCAN 13 -600 400 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD T 1 72 -216 56 0 2 0 VSS T 1 72 184 56 0 2 0 VDD X VDD 14 0 300 200 D 40 40 2 1 W X VSS 7 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF #End Library