EESchema-LIBRARY Version 2.3  29/04/2008-12:23:02
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 6
#
# Dev Name: 18F6XJ6X
# Package Name: TQFP64-10X10
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF 18F6XJ6X IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: PIC18F6XJ6X
F0 "IC" -300 100 50 H V L B
F1 "18F6XJ6X" -200 -300 50 H V L B
F2 "microchip_enet-TQFP64-10X10" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1100 1900 1000 1900
P 2 1 0 0 1000 1900 1000 -2300
P 2 1 0 0 1000 -2300 -1100 -2300
P 2 1 0 0 -1100 -2300 -1100 1900
X AVDD 19 0 2000 100 D 40 40 1 1 W 
X AVSS 20 -600 -2400 100 U 40 40 1 1 W 
X ENVREG 18 -1200 -1900 100 R 40 40 1 1 I 
X OSC1/CLKI 39 1100 -600 100 L 40 40 1 1 I 
X OSC2/CLKO 40 1100 -800 100 L 40 40 1 1 O 
X RA0/LEDA/AN0 24 -1200 1200 100 R 40 40 1 1 B 
X RA1/LEDB/AN1 23 -1200 1100 100 R 40 40 1 1 B 
X RA2/AN2/VREF- 22 -1200 1000 100 R 40 40 1 1 B 
X RA3/AN3/VREF+ 21 -1200 900 100 R 40 40 1 1 B 
X RA4/T0CK 28 -1200 800 100 R 40 40 1 1 B 
X RA5/AN4 27 -1200 700 100 R 40 40 1 1 B 
X RB0/INT0/FLT0 3 -1200 400 100 R 40 40 1 1 B 
X RB1/INT1 4 -1200 300 100 R 40 40 1 1 B 
X RB2/INT2 5 -1200 200 100 R 40 40 1 1 B 
X RB3/INT3 6 -1200 100 100 R 40 40 1 1 B 
X RB4/KBI0 44 -1200 0 100 R 40 40 1 1 B 
X RB5/KBI1 43 -1200 -100 100 R 40 40 1 1 B 
X RB6/KBI2/PGC 42 -1200 -200 100 R 40 40 1 1 B 
X RB7/KBI3/PGD 37 -1200 -300 100 R 40 40 1 1 B 
X RBIAS 53 1100 -1800 100 L 40 40 1 1 I 
X RC0/T1OSO/T13CKI 30 -1200 -500 100 R 40 40 1 1 B 
X RC1/T1OSI/ECCP2/P2A 29 -1200 -600 100 R 40 40 1 1 B 
X RC2/ECCP1/P1A 33 -1200 -700 100 R 40 40 1 1 B 
X RC3/SCK1/SCL1 34 -1200 -800 100 R 40 40 1 1 B 
X RC4/SDI1/SDA1 35 -1200 -900 100 R 40 40 1 1 B 
X RC5/SDO1 36 -1200 -1000 100 R 40 40 1 1 B 
X RC6/TX1/CK1 31 -1200 -1100 100 R 40 40 1 1 B 
X RC7/RX1/DT1 32 -1200 -1200 100 R 40 40 1 1 B 
X RD0/P1B 60 -1200 -1500 100 R 40 40 1 1 B 
X RD1/ECCP3/P3A 59 -1200 -1600 100 R 40 40 1 1 B 
X RD2/CCP4/P3D 58 -1200 -1700 100 R 40 40 1 1 B 
X RE0/P2D 2 1100 -1000 100 L 40 40 1 1 B 
X RE1/P2C 1 1100 -1100 100 L 40 40 1 1 B 
X RE2/P2B 64 1100 -1200 100 L 40 40 1 1 B 
X RE3/P3C 63 1100 -1300 100 L 40 40 1 1 B 
X RE4/P3B 62 1100 -1400 100 L 40 40 1 1 B 
X RE5/P1C 61 1100 -1500 100 L 40 40 1 1 B 
X RF1/AN6/C2OUT 17 1100 300 100 L 40 40 1 1 B 
X RF2/AN7/C1OUT 16 1100 200 100 L 40 40 1 1 B 
X RF3/AN8 15 1100 100 100 L 40 40 1 1 B 
X RF4/AN9 14 1100 0 100 L 40 40 1 1 B 
X RF5/AN10/CVREF 13 1100 -100 100 L 40 40 1 1 B 
X RF6/AN11 12 1100 -200 100 L 40 40 1 1 B 
X RF7/\SS1 11 1100 -300 100 L 40 40 1 1 B 
X RG4/CCP5/P1D 8 1100 600 100 L 40 40 1 1 B 
X TPIN+ 47 1100 900 100 L 40 40 1 1 I 
X TPIN- 46 1100 800 100 L 40 40 1 1 I 
X TPOUT+ 51 1100 1200 100 L 40 40 1 1 O 
X TPOUT- 50 1100 1100 100 L 40 40 1 1 O 
X VDD 26 300 2000 100 D 40 40 1 1 W 
X VDD@1 38 400 2000 100 D 40 40 1 1 W 
X VDD@2 57 500 2000 100 D 40 40 1 1 W 
X VDDCORE/VCAP 10 -200 2000 100 D 40 40 1 1 W 
X VDDPLL 54 100 2000 100 D 40 40 1 1 W 
X VDDRX 48 700 2000 100 D 40 40 1 1 W 
X VDDTX 49 900 2000 100 D 40 40 1 1 W 
X VSS 9 -400 -2400 100 U 40 40 1 1 W 
X VSS@1 25 -300 -2400 100 U 40 40 1 1 W 
X VSS@2 41 -200 -2400 100 U 40 40 1 1 W 
X VSS@3 56 -100 -2400 100 U 40 40 1 1 W 
X VSSPLL 55 100 -2400 100 U 40 40 1 1 W 
X VSSRX 45 600 -2400 100 U 40 40 1 1 W 
X VSSTX 52 800 -2400 100 U 40 40 1 1 W 
X \MCLR 7 -1200 1700 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: 18F8XJ6X
# Package Name: TQFP80-12X12
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 0
#
DEF 18F8XJ6X IC 0 40 Y Y 0 L N
ENDDRAW
ENDDEF

#
# Dev Name: 18F9XJ6X
# Package Name: TQFP100-14X14
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF 18F9XJ6X IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: PIC18F9XJ6X
F0 "IC" -200 100 50 H V L B
F1 "18F9XJ6X" -300 -200 50 H V L B
F2 "microchip_enet-TQFP100-14X14" 0 150 50 H I C C
DRAW
P 2 1 0 0 -1200 2700 1100 2700
P 2 1 0 0 1100 2700 1100 -3300
P 2 1 0 0 1100 -3300 -1200 -3300
P 2 1 0 0 -1200 -3300 -1200 2700
X AVDD 30 -100 2800 100 D 40 40 1 1 W 
X AVSS 31 -600 -3400 100 U 40 40 1 1 W 
X ENVREG 29 -1300 -2800 100 R 40 40 1 1 I 
X N/C 9 -1300 -2600 100 R 40 40 1 1 U 
X OSC1/CLKI 63 1200 -2600 100 L 40 40 1 1 I 
X OSC2/CLKO 64 1200 -2800 100 L 40 40 1 1 O 
X RA0/LEDA/AN0 35 -1300 2200 100 R 40 40 1 1 B 
X RA1/LEDB/AN1 34 -1300 2100 100 R 40 40 1 1 B 
X RA2/AN2/VREF- 33 -1300 2000 100 R 40 40 1 1 B 
X RA3/AN3/VREF+ 32 -1300 1900 100 R 40 40 1 1 B 
X RA4/T0CK 42 -1300 1800 100 R 40 40 1 1 B 
X RA5/AN4 41 -1300 1700 100 R 40 40 1 1 B 
X RB0/INT0/FLT0 5 -1300 1400 100 R 40 40 1 1 B 
X RB1/INT1 6 -1300 1300 100 R 40 40 1 1 B 
X RB2/INT2 7 -1300 1200 100 R 40 40 1 1 B 
X RB3/INT3/ECCP2/P2A 8 -1300 1100 100 R 40 40 1 1 B 
X RB4/KBI0 69 -1300 1000 100 R 40 40 1 1 B 
X RB5/KBI1 68 -1300 900 100 R 40 40 1 1 B 
X RB6/KBI2/PGC 67 -1300 800 100 R 40 40 1 1 B 
X RB7/KBI3/PGD 57 -1300 700 100 R 40 40 1 1 B 
X RBIAS 80 1200 -3100 100 L 40 40 1 1 I 
X RC0/T1OSO/T13CKI 44 -1300 400 100 R 40 40 1 1 B 
X RC1/T1OSI/ECCP2/P2A 43 -1300 300 100 R 40 40 1 1 B 
X RC2/ECCP1/P1A 53 -1300 200 100 R 40 40 1 1 B 
X RC3/SCK1/SCL1 54 -1300 100 100 R 40 40 1 1 B 
X RC4/SDI1/SDA1 55 -1300 0 100 R 40 40 1 1 B 
X RC5/SDO1 56 -1300 -100 100 R 40 40 1 1 B 
X RC6/TX1/CK1 45 -1300 -200 100 R 40 40 1 1 B 
X RC7/RX1/DT1 46 -1300 -300 100 R 40 40 1 1 B 
X RD0/AD0/PSP0 92 -1300 -600 100 R 40 40 1 1 B 
X RD1/AD1/PSP1 91 -1300 -700 100 R 40 40 1 1 B 
X RD2/AD2/PSP2 90 -1300 -800 100 R 40 40 1 1 B 
X RD3/AD3/PSP3 89 -1300 -900 100 R 40 40 1 1 B 
X RD4/AD4/PSP4/SDO2 88 -1300 -1000 100 R 40 40 1 1 B 
X RD5/AD5/PSP5/SDI2/SDA2 87 -1300 -1100 100 R 40 40 1 1 B 
X RD6/AD6/PSP6/SCK2/SCL2 84 -1300 -1200 100 R 40 40 1 1 B 
X RD7/AD7/PSP7/SS2 83 -1300 -1300 100 R 40 40 1 1 B 
X RE0/AD8/RD/P2D 4 -1300 -1600 100 R 40 40 1 1 B 
X RE1/AD9/WR/P2C 3 -1300 -1700 100 R 40 40 1 1 B 
X RE2/AD10/CS/P2B 98 -1300 -1800 100 R 40 40 1 1 B 
X RE3/AD11/P3C 97 -1300 -1900 100 R 40 40 1 1 B 
X RE4/AD12/P3B 96 -1300 -2000 100 R 40 40 1 1 B 
X RE5/AD13/P1C 95 -1300 -2100 100 R 40 40 1 1 B 
X RE6/AD14/P1B 94 -1300 -2200 100 R 40 40 1 1 B 
X RE7/AD15/ECCP2/P2A 93 -1300 -2300 100 R 40 40 1 1 B 
X RF0/AN5 12 1200 -1600 100 L 40 40 1 1 B 
X RF1/AN6/C2OUT 28 1200 -1700 100 L 40 40 1 1 B 
X RF2/AN7/C1OUT 23 1200 -1800 100 L 40 40 1 1 B 
X RF3/AN8 22 1200 -1900 100 L 40 40 1 1 B 
X RF4/AN9 21 1200 -2000 100 L 40 40 1 1 B 
X RF5/AN10/CVREF 20 1200 -2100 100 L 40 40 1 1 B 
X RF6/AN11 19 1200 -2200 100 L 40 40 1 1 B 
X RF7/\SS1 18 1200 -2300 100 L 40 40 1 1 B 
X RG0/ECCP3/P3A 71 1200 -600 100 L 40 40 1 1 B 
X RG1/TX2/CK2 70 1200 -700 100 L 40 40 1 1 B 
X RG2/RX2/DT2 52 1200 -800 100 L 40 40 1 1 B 
X RG3/CCP4/P3D 51 1200 -900 100 L 40 40 1 1 B 
X RG4/CCP5/P1D 14 1200 -1000 100 L 40 40 1 1 B 
X RG5 11 1200 -1100 100 L 40 40 1 1 B 
X RG6 10 1200 -1200 100 L 40 40 1 1 B 
X RG7 38 1200 -1300 100 L 40 40 1 1 B 
X RH0/A16 99 1200 400 100 L 40 40 1 1 B 
X RH1/A17 100 1200 300 100 L 40 40 1 1 B 
X RH2/A18 1 1200 200 100 L 40 40 1 1 B 
X RH3/A19 2 1200 100 100 L 40 40 1 1 B 
X RH4/AN12/P3C 27 1200 0 100 L 40 40 1 1 B 
X RH5/AN13/P3B 26 1200 -100 100 L 40 40 1 1 B 
X RH6/AN14/P1C 25 1200 -200 100 L 40 40 1 1 B 
X RH7/AN15/P1B 24 1200 -300 100 L 40 40 1 1 B 
X RJ0/ALE 49 1200 1400 100 L 40 40 1 1 B 
X RJ1/OE 50 1200 1300 100 L 40 40 1 1 B 
X RJ2/WRL 66 1200 1200 100 L 40 40 1 1 B 
X RJ3/WRH 61 1200 1100 100 L 40 40 1 1 B 
X RJ4/BA0 47 1200 1000 100 L 40 40 1 1 B 
X RJ5/CE 48 1200 900 100 L 40 40 1 1 B 
X RJ6/LB 58 1200 800 100 L 40 40 1 1 B 
X RJ7/UB 39 1200 700 100 L 40 40 1 1 B 
X TPIN+ 74 1200 2000 100 L 40 40 1 1 I 
X TPIN- 73 1200 1900 100 L 40 40 1 1 I 
X TPOUT+ 78 1200 1700 100 L 40 40 1 1 O 
X TPOUT- 77 1200 1600 100 L 40 40 1 1 W 
X VDD@0 17 100 2800 100 D 40 40 1 1 W 
X VDD@1 37 200 2800 100 D 40 40 1 1 W 
X VDD@2 59 300 2800 100 D 40 40 1 1 W 
X VDD@3 62 400 2800 100 D 40 40 1 1 W 
X VDD@4 86 500 2800 100 D 40 40 1 1 W 
X VDDCORE/VCAP 16 -300 2800 100 D 40 40 1 1 W 
X VDDPLL 81 700 2800 100 D 40 40 1 1 W 
X VDDRX 75 1000 2800 100 D 40 40 1 1 W 
X VDDTX 76 900 2800 100 D 40 40 1 1 O 
X VSS@0 15 -400 -3400 100 U 40 40 1 1 W 
X VSS@1 36 -300 -3400 100 U 40 40 1 1 W 
X VSS@2 40 -200 -3400 100 U 40 40 1 1 W 
X VSS@3 60 -100 -3400 100 U 40 40 1 1 W 
X VSS@4 65 0 -3400 100 U 40 40 1 1 W 
X VSS@5 85 100 -3400 100 U 40 40 1 1 W 
X VSSPLL 82 -800 -3400 100 U 40 40 1 1 W 
X VSSRX 72 300 -3400 100 U 40 40 1 1 W 
X VSSTX 79 500 -3400 100 U 40 40 1 1 W 
X \MCLR 13 -1300 2500 100 R 40 40 1 1 I 
ENDDRAW
ENDDEF

#
# Dev Name: ENC28J60-DIL
# Package Name: DIL28-3
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ENC28J60-DIL IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ENC28J60
F0 "IC" -800 900 50 H V L B
F1 "ENC28J60-DIL" 200 -600 50 H V L B
F2 "microchip_enet-DIL28-3" 0 150 50 H I C C
DRAW
P 2 1 0 0 -800 800 -800 -500
P 2 1 0 0 -800 -500 600 -500
P 2 1 0 0 600 -500 600 800
P 2 1 0 0 600 800 -800 800
X CLKOUT 3 -1000 -200 200 R 40 40 1 1 O 
X CS 9 -1000 0 200 R 40 40 1 1 I I
X INT 4 -1000 700 200 R 40 40 1 1 O I
X LEDA 27 800 100 200 L 40 40 1 1 O 
X LEDB 26 800 0 200 L 40 40 1 1 O 
X OSC1 23 800 -300 200 L 40 40 1 1 I C
X OSC2 24 800 -400 200 L 40 40 1 1 O C
X RBIAS 14 -1000 -400 200 R 40 40 1 1 P 
X RESET 10 -1000 500 200 R 40 40 1 1 I I
X SCK 8 -1000 100 200 R 40 40 1 1 I C
X SI 7 -1000 200 200 R 40 40 1 1 I 
X SO 6 -1000 300 200 R 40 40 1 1 O 
X TPIN+ 13 800 400 200 L 40 40 1 1 I 
X TPIN- 12 800 300 200 L 40 40 1 1 I 
X TPOUT+ 17 800 700 200 L 40 40 1 1 O 
X TPOUT- 16 800 600 200 L 40 40 1 1 O 
X VCAP 1 -1000 -300 200 R 40 40 1 1 W 
X VDD 28 100 1000 200 D 40 40 1 1 W 
X VDDOSC 25 0 1000 200 D 40 40 1 1 W 
X VDDPLL 20 -200 1000 200 D 40 40 1 1 W 
X VDDRX 19 -300 1000 200 D 40 40 1 1 W 
X VDDTX 15 -100 1000 200 D 40 40 1 1 W 
X VSS 2 100 -700 200 U 40 40 1 1 W 
X VSSOSC 22 0 -700 200 U 40 40 1 1 W 
X VSSPLL 21 -200 -700 200 U 40 40 1 1 W 
X VSSRX 11 -300 -700 200 U 40 40 1 1 W 
X VSSTX 18 -100 -700 200 U 40 40 1 1 W 
X WOL 5 -1000 600 200 R 40 40 1 1 O I
ENDDRAW
ENDDEF

#
# Dev Name: ENC28J60-SO
# Package Name: SO28W
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ENC28J60-SO IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ENC28J60
F0 "IC" -800 900 50 H V L B
F1 "ENC28J60-SO" 200 -600 50 H V L B
F2 "microchip_enet-SO28W" 0 150 50 H I C C
DRAW
P 2 1 0 0 -800 800 -800 -500
P 2 1 0 0 -800 -500 600 -500
P 2 1 0 0 600 -500 600 800
P 2 1 0 0 600 800 -800 800
X CLKOUT 3 -1000 -200 200 R 40 40 1 1 O 
X CS 9 -1000 0 200 R 40 40 1 1 I I
X INT 4 -1000 700 200 R 40 40 1 1 O I
X LEDA 27 800 100 200 L 40 40 1 1 O 
X LEDB 26 800 0 200 L 40 40 1 1 O 
X OSC1 23 800 -300 200 L 40 40 1 1 I C
X OSC2 24 800 -400 200 L 40 40 1 1 O C
X RBIAS 14 -1000 -400 200 R 40 40 1 1 P 
X RESET 10 -1000 500 200 R 40 40 1 1 I I
X SCK 8 -1000 100 200 R 40 40 1 1 I C
X SI 7 -1000 200 200 R 40 40 1 1 I 
X SO 6 -1000 300 200 R 40 40 1 1 O 
X TPIN+ 13 800 400 200 L 40 40 1 1 I 
X TPIN- 12 800 300 200 L 40 40 1 1 I 
X TPOUT+ 17 800 700 200 L 40 40 1 1 O 
X TPOUT- 16 800 600 200 L 40 40 1 1 O 
X VCAP 1 -1000 -300 200 R 40 40 1 1 W 
X VDD 28 100 1000 200 D 40 40 1 1 W 
X VDDOSC 25 0 1000 200 D 40 40 1 1 W 
X VDDPLL 20 -200 1000 200 D 40 40 1 1 W 
X VDDRX 19 -300 1000 200 D 40 40 1 1 W 
X VDDTX 15 -100 1000 200 D 40 40 1 1 W 
X VSS 2 100 -700 200 U 40 40 1 1 W 
X VSSOSC 22 0 -700 200 U 40 40 1 1 W 
X VSSPLL 21 -200 -700 200 U 40 40 1 1 W 
X VSSRX 11 -300 -700 200 U 40 40 1 1 W 
X VSSTX 18 -100 -700 200 U 40 40 1 1 W 
X WOL 5 -1000 600 200 R 40 40 1 1 O I
ENDDRAW
ENDDEF

#
# Dev Name: ENC28J60-SSOP
# Package Name: SSOP28
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF ENC28J60-SSOP IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: ENC28J60
F0 "IC" -800 900 50 H V L B
F1 "ENC28J60-SSOP" 200 -600 50 H V L B
F2 "microchip_enet-SSOP28" 0 150 50 H I C C
DRAW
P 2 1 0 0 -800 800 -800 -500
P 2 1 0 0 -800 -500 600 -500
P 2 1 0 0 600 -500 600 800
P 2 1 0 0 600 800 -800 800
X CLKOUT 3 -1000 -200 200 R 40 40 1 1 O 
X CS 9 -1000 0 200 R 40 40 1 1 I I
X INT 4 -1000 700 200 R 40 40 1 1 O I
X LEDA 27 800 100 200 L 40 40 1 1 O 
X LEDB 26 800 0 200 L 40 40 1 1 O 
X OSC1 23 800 -300 200 L 40 40 1 1 I C
X OSC2 24 800 -400 200 L 40 40 1 1 O C
X RBIAS 14 -1000 -400 200 R 40 40 1 1 P 
X RESET 10 -1000 500 200 R 40 40 1 1 I I
X SCK 8 -1000 100 200 R 40 40 1 1 I C
X SI 7 -1000 200 200 R 40 40 1 1 I 
X SO 6 -1000 300 200 R 40 40 1 1 O 
X TPIN+ 13 800 400 200 L 40 40 1 1 I 
X TPIN- 12 800 300 200 L 40 40 1 1 I 
X TPOUT+ 17 800 700 200 L 40 40 1 1 O 
X TPOUT- 16 800 600 200 L 40 40 1 1 O 
X VCAP 1 -1000 -300 200 R 40 40 1 1 W 
X VDD 28 100 1000 200 D 40 40 1 1 W 
X VDDOSC 25 0 1000 200 D 40 40 1 1 W 
X VDDPLL 20 -200 1000 200 D 40 40 1 1 W 
X VDDRX 19 -300 1000 200 D 40 40 1 1 W 
X VDDTX 15 -100 1000 200 D 40 40 1 1 W 
X VSS 2 100 -700 200 U 40 40 1 1 W 
X VSSOSC 22 0 -700 200 U 40 40 1 1 W 
X VSSPLL 21 -200 -700 200 U 40 40 1 1 W 
X VSSRX 11 -300 -700 200 U 40 40 1 1 W 
X VSSTX 18 -100 -700 200 U 40 40 1 1 W 
X WOL 5 -1000 600 200 R 40 40 1 1 O I
ENDDRAW
ENDDEF

#End Library