EESchema-LIBRARY Version 2.3  29/04/2008-12:23:14
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 1
#
# Dev Name: MPC5200
# Package Name: TE-PBGA272
# Dev Tech: ''
# Dev Prefix: U
# Gate count = 3
#
DEF MPC5200 U 0 40 Y Y 3 L N
# Gate Name: G$1
# Symbol Name: MPC5200
F0 "U" -4000 -3100 50 H V L B
F1 "MPC5200" -4000 -3200 50 H V L B
F2 "mpc5200-TE-PBGA272" 0 150 50 H I C C
DRAW
P 2 1 0 0 -4200 3300 4200 3300
P 2 1 0 0 4200 3300 4200 -3400
P 2 1 0 0 4200 -3400 -4200 -3400
P 2 1 0 0 -4200 -3400 -4200 3300
X /ATA_DACK Y18 4400 -2000 200 L 40 40 1 1 B 
X /ATA_IOR Y17 4400 -1800 200 L 40 40 1 1 B 
X /ATA_IOW W17 4400 -1700 200 L 40 40 1 1 B 
X /HRESET B13 -2500 -3600 200 U 40 40 1 1 I 
X /LP_ALE V14 4400 -1200 200 L 40 40 1 1 B 
X /LP_CS0 W14 -4400 -2300 200 R 40 40 1 1 B 
X /LP_CS1 Y14 -4400 -2400 200 R 40 40 1 1 B 
X /LP_CS2 V15 -4400 -2500 200 R 40 40 1 1 B 
X /LP_CS3 W15 -4400 -2600 200 R 40 40 1 1 B 
X /LP_CS4 Y15 -4400 -2700 200 R 40 40 1 1 B 
X /LP_CS5 V16 -4400 -2800 200 R 40 40 1 1 B 
X /LP_OE D8 4400 -900 200 L 40 40 1 1 B 
X /LP_TS Y13 4400 -1000 200 L 40 40 1 1 B 
X /MEM_CAS B19 3300 3500 200 D 40 40 1 1 B 
X /MEM_CLK G20 3100 3500 200 D 40 40 1 1 B 
X /MEM_CS_0 B18 3500 3500 200 D 40 40 1 1 B 
X /MEM_RAS A18 3600 3500 200 D 40 40 1 1 B 
X /MEM_WE A19 3400 3500 200 D 40 40 1 1 B 
X /PCI_CBE_0 W10 -1700 -3600 200 U 40 40 1 1 B 
X /PCI_CBE_1 Y8 -1600 -3600 200 U 40 40 1 1 B 
X /PCI_CBE_2 W6 -1500 -3600 200 U 40 40 1 1 B 
X /PCI_CBE_3 Y2 -1400 -3600 200 U 40 40 1 1 B 
X /PCI_DEVSEL W7 -800 -3600 200 U 40 40 1 1 B 
X /PCI_FRAME V5 -1300 -3600 200 U 40 40 1 1 B 
X /PCI_GNT R4 -2200 -3600 200 U 40 40 1 1 B 
X /PCI_IRDY Y6 -1000 -3600 200 U 40 40 1 1 B 
X /PCI_PERR Y7 -700 -3600 200 U 40 40 1 1 B 
X /PCI_REQ U1 -1800 -3600 200 U 40 40 1 1 B 
X /PCI_RESET R2 -2100 -3600 200 U 40 40 1 1 B 
X /PCI_SERR W8 -600 -3600 200 U 40 40 1 1 B 
X /PCI_STOP V6 -1100 -3600 200 U 40 40 1 1 B 
X /PCI_TRDY W5 -1200 -3600 200 U 40 40 1 1 B 
X /PORRESET A13 -2600 -3600 200 U 40 40 1 1 I 
X /SRESET A14 -2700 -3600 200 U 40 40 1 1 I 
X ATA_DRQ V17 4400 -1600 200 L 40 40 1 1 B 
X ATA_INTRQ Y19 4400 -2100 200 L 40 40 1 1 B 
X ATA_IOCHRDY W18 4400 -1900 200 L 40 40 1 1 B 
X ATA_ISOLATION Y16 4400 -1500 200 L 40 40 1 1 B 
X ETH_0 K1 -4400 300 200 R 40 40 1 1 B 
X ETH_1 K2 -4400 200 200 R 40 40 1 1 B 
X ETH_2 K3 -4400 100 200 R 40 40 1 1 B 
X ETH_3 J1 -4400 0 200 R 40 40 1 1 B 
X ETH_4 J2 -4400 -100 200 R 40 40 1 1 B 
X ETH_5 L3 -4400 -200 200 R 40 40 1 1 B 
X ETH_6 N2 -4400 -300 200 R 40 40 1 1 B 
X ETH_7 N1 -4400 -400 200 R 40 40 1 1 B 
X ETH_8 M3 -4400 -500 200 R 40 40 1 1 B 
X ETH_9 L1 -4400 -600 200 R 40 40 1 1 B 
X ETH_10 J3 -4400 -700 200 R 40 40 1 1 B 
X ETH_11 L4 -4400 -800 200 R 40 40 1 1 B 
X ETH_12 M2 -4400 -900 200 R 40 40 1 1 B 
X ETH_13 M1 -4400 -1000 200 R 40 40 1 1 B 
X ETH_14 N4 -4400 -1100 200 R 40 40 1 1 B 
X ETH_15 N3 -4400 -1200 200 R 40 40 1 1 B 
X ETH_16 L2 -4400 -1300 200 R 40 40 1 1 B 
X ETH_17 J4 -4400 -1400 200 R 40 40 1 1 B 
X EXT_AD_0 V13 4400 2500 200 L 40 40 1 1 B 
X EXT_AD_1 W13 4400 2400 200 L 40 40 1 1 B 
X EXT_AD_2 V12 4400 2300 200 L 40 40 1 1 B 
X EXT_AD_3 Y12 4400 2200 200 L 40 40 1 1 B 
X EXT_AD_4 V11 4400 2100 200 L 40 40 1 1 B 
X EXT_AD_5 W12 4400 2000 200 L 40 40 1 1 B 
X EXT_AD_6 U11 4400 1900 200 L 40 40 1 1 B 
X EXT_AD_7 Y11 4400 1800 200 L 40 40 1 1 B 
X EXT_AD_8 W11 4400 1700 200 L 40 40 1 1 B 
X EXT_AD_9 V10 4400 1600 200 L 40 40 1 1 B 
X EXT_AD_10 Y10 4400 1500 200 L 40 40 1 1 B 
X EXT_AD_11 V9 4400 1400 200 L 40 40 1 1 B 
X EXT_AD_12 Y9 4400 1300 200 L 40 40 1 1 B 
X EXT_AD_13 V8 4400 1200 200 L 40 40 1 1 B 
X EXT_AD_14 W9 4400 1100 200 L 40 40 1 1 B 
X EXT_AD_15 U8 4400 1000 200 L 40 40 1 1 B 
X EXT_AD_16 W4 4400 900 200 L 40 40 1 1 B 
X EXT_AD_17 Y5 4400 800 200 L 40 40 1 1 B 
X EXT_AD_18 V4 4400 700 200 L 40 40 1 1 B 
X EXT_AD_19 Y4 4400 600 200 L 40 40 1 1 B 
X EXT_AD_20 V2 4400 500 200 L 40 40 1 1 B 
X EXT_AD_21 Y3 4400 400 200 L 40 40 1 1 B 
X EXT_AD_22 V3 4400 300 200 L 40 40 1 1 B 
X EXT_AD_23 W3 4400 200 200 L 40 40 1 1 B 
X EXT_AD_24 U3 4400 100 200 L 40 40 1 1 B 
X EXT_AD_25 W2 4400 0 200 L 40 40 1 1 B 
X EXT_AD_26 T2 4400 -100 200 L 40 40 1 1 B 
X EXT_AD_27 Y1 4400 -200 200 L 40 40 1 1 B 
X EXT_AD_28 T3 4400 -300 200 L 40 40 1 1 B 
X EXT_AD_29 W1 4400 -400 200 L 40 40 1 1 B 
X EXT_AD_30 R3 4400 -500 200 L 40 40 1 1 B 
X EXT_AD_31 V1 4400 -600 200 L 40 40 1 1 B 
X GPIO_WKUP_6 C15 2900 -3600 200 U 40 40 1 1 B 
X GPIO_WKUP_7 C12 3000 -3600 200 U 40 40 1 1 B 
X I2C_0 V19 4400 -2400 200 L 40 40 1 1 B 
X I2C_1 W19 4400 -2500 200 L 40 40 1 1 B 
X I2C_2 V20 4400 -2600 200 L 40 40 1 1 B 
X I2C_3 W20 4400 -2700 200 L 40 40 1 1 B 
X IRQ0 P3 -4400 -1700 200 R 40 40 1 1 B 
X IRQ1 P1 -4400 -1800 200 R 40 40 1 1 B 
X IRQ2 P2 -4400 -1900 200 R 40 40 1 1 B 
X IRQ3 R1 -4400 -2000 200 R 40 40 1 1 B 
X JTAG_TCK B4 -3000 -3600 200 U 40 40 1 1 I 
X JTAG_TDI A3 -3100 -3600 200 U 40 40 1 1 I 
X JTAG_TDO A2 -3200 -3600 200 U 40 40 1 1 I 
X JTAG_TMS A4 -3300 -3600 200 U 40 40 1 1 I 
X JTAG_TRST B3 -3400 -3600 200 U 40 40 1 1 I 
X LP_ACK U14 4400 -1100 200 L 40 40 1 1 B 
X LP_R/W W16 4400 -1300 200 L 40 40 1 1 B 
X MEM_CLK G19 3000 3500 200 D 40 40 1 1 B 
X MEM_CLK_EN F20 3200 3500 200 D 40 40 1 1 B 
X MEM_DQM_0 N19 0 3500 200 D 40 40 1 1 B 
X MEM_DQM_1 H19 -100 3500 200 D 40 40 1 1 B 
X MEM_DQM_2 A20 -200 3500 200 D 40 40 1 1 B 
X MEM_DQM_3 L17 -300 3500 200 D 40 40 1 1 B 
X MEM_MA_0 C17 2100 3500 200 D 40 40 1 1 B 
X MEM_MA_1 A16 2000 3500 200 D 40 40 1 1 B 
X MEM_MA_2 B16 1900 3500 200 D 40 40 1 1 B 
X MEM_MA_3 C16 1800 3500 200 D 40 40 1 1 B 
X MEM_MA_4 B20 1700 3500 200 D 40 40 1 1 B 
X MEM_MA_5 C19 1600 3500 200 D 40 40 1 1 B 
X MEM_MA_6 C20 1500 3500 200 D 40 40 1 1 B 
X MEM_MA_7 D19 1400 3500 200 D 40 40 1 1 B 
X MEM_MA_8 D20 1300 3500 200 D 40 40 1 1 B 
X MEM_MA_9 E19 1200 3500 200 D 40 40 1 1 B 
X MEM_MA_10 B17 1100 3500 200 D 40 40 1 1 B 
X MEM_MA_11 E20 1000 3500 200 D 40 40 1 1 B 
X MEM_MA_12 F19 900 3500 200 D 40 40 1 1 B 
X MEM_MBA_0 C18 2700 3500 200 D 40 40 1 1 B 
X MEM_MBA_1 A17 2600 3500 200 D 40 40 1 1 B 
X MEM_MDQS_0 N20 600 3500 200 D 40 40 1 1 B 
X MEM_MDQS_1 H20 500 3500 200 D 40 40 1 1 B 
X MEM_MDQS_2 D18 400 3500 200 D 40 40 1 1 B 
X MEM_MDQS_3 L18 300 3500 200 D 40 40 1 1 B 
X MEM_MDQ_0 U20 -600 3500 200 D 40 40 1 1 B 
X MEM_MDQ_1 U19 -700 3500 200 D 40 40 1 1 B 
X MEM_MDQ_2 T20 -800 3500 200 D 40 40 1 1 B 
X MEM_MDQ_3 T19 -900 3500 200 D 40 40 1 1 B 
X MEM_MDQ_4 R20 -1000 3500 200 D 40 40 1 1 B 
X MEM_MDQ_5 R19 -1100 3500 200 D 40 40 1 1 B 
X MEM_MDQ_6 P20 -1200 3500 200 D 40 40 1 1 B 
X MEM_MDQ_7 P19 -1300 3500 200 D 40 40 1 1 B 
X MEM_MDQ_8 J19 -1400 3500 200 D 40 40 1 1 B 
X MEM_MDQ_9 J20 -1500 3500 200 D 40 40 1 1 B 
X MEM_MDQ_10 K19 -1600 3500 200 D 40 40 1 1 B 
X MEM_MDQ_11 K20 -1700 3500 200 D 40 40 1 1 B 
X MEM_MDQ_12 L19 -1800 3500 200 D 40 40 1 1 B 
X MEM_MDQ_13 L20 -1900 3500 200 D 40 40 1 1 B 
X MEM_MDQ_14 M19 -2000 3500 200 D 40 40 1 1 B 
X MEM_MDQ_15 M20 -2100 3500 200 D 40 40 1 1 B 
X MEM_MDQ_16 E18 -2200 3500 200 D 40 40 1 1 B 
X MEM_MDQ_17 F18 -2300 3500 200 D 40 40 1 1 B 
X MEM_MDQ_18 G17 -2400 3500 200 D 40 40 1 1 B 
X MEM_MDQ_19 G18 -2500 3500 200 D 40 40 1 1 B 
X MEM_MDQ_20 H18 -2600 3500 200 D 40 40 1 1 B 
X MEM_MDQ_21 J18 -2700 3500 200 D 40 40 1 1 B 
X MEM_MDQ_22 J17 -2800 3500 200 D 40 40 1 1 B 
X MEM_MDQ_23 K18 -2900 3500 200 D 40 40 1 1 B 
X MEM_MDQ_24 M18 -3000 3500 200 D 40 40 1 1 B 
X MEM_MDQ_25 N17 -3100 3500 200 D 40 40 1 1 B 
X MEM_MDQ_26 N18 -3200 3500 200 D 40 40 1 1 B 
X MEM_MDQ_27 P18 -3300 3500 200 D 40 40 1 1 B 
X MEM_MDQ_28 R17 -3400 3500 200 D 40 40 1 1 B 
X MEM_MDQ_29 R18 -3500 3500 200 D 40 40 1 1 B 
X MEM_MDQ_30 T18 -3600 3500 200 D 40 40 1 1 B 
X MEM_MDQ_31 U18 -3700 3500 200 D 40 40 1 1 B 
X PCI_CLOCK T1 -2000 -3600 200 U 40 40 1 1 B 
X PCI_IDSEL U2 -1900 -3600 200 U 40 40 1 1 B 
X PCI_PAR V7 -900 -3600 200 U 40 40 1 1 B 
X PSC1_0 B11 -300 -3600 200 U 40 40 1 1 B 
X PSC1_1 A11 -200 -3600 200 U 40 40 1 1 B 
X PSC1_2 C10 -100 -3600 200 U 40 40 1 1 B 
X PSC1_3 B10 0 -3600 200 U 40 40 1 1 B 
X PSC1_4 A10 100 -3600 200 U 40 40 1 1 B 
X PSC2_0 C9 400 -3600 200 U 40 40 1 1 B 
X PSC2_1 B9 500 -3600 200 U 40 40 1 1 B 
X PSC2_2 A9 600 -3600 200 U 40 40 1 1 B 
X PSC2_3 B8 700 -3600 200 U 40 40 1 1 B 
X PSC2_4 A8 800 -3600 200 U 40 40 1 1 B 
X PSC3_0 C7 1100 -3600 200 U 40 40 1 1 B 
X PSC3_1 B7 1200 -3600 200 U 40 40 1 1 B 
X PSC3_2 A7 1300 -3600 200 U 40 40 1 1 B 
X PSC3_3 C6 1400 -3600 200 U 40 40 1 1 B 
X PSC3_4 B6 1500 -3600 200 U 40 40 1 1 B 
X PSC3_5 A6 1600 -3600 200 U 40 40 1 1 B 
X PSC3_6 C5 1700 -3600 200 U 40 40 1 1 B 
X PSC3_7 B5 1800 -3600 200 U 40 40 1 1 B 
X PSC3_8 A5 1900 -3600 200 U 40 40 1 1 B 
X PSC3_9 C4 2000 -3600 200 U 40 40 1 1 B 
X PSC6_0 B12 2300 -3600 200 U 40 40 1 1 B 
X PSC6_1 C11 2400 -3600 200 U 40 40 1 1 B 
X PSC6_2 A12 2500 -3600 200 U 40 40 1 1 B 
X PSC6_3 C13 2600 -3600 200 U 40 40 1 1 B 
X SYS_PLL_TPA B15 3700 -3600 200 U 40 40 1 1 I 
X TEST_MODE_0 B2 3400 -3600 200 U 40 40 1 1 B 
X TEST_MODE_1 A1 3300 -3600 200 U 40 40 1 1 B 
X TEST_SEL_0 B1 3600 -3600 200 U 40 40 1 1 B 
X TEST_SEL_1 C3 3500 -3600 200 U 40 40 1 1 B 
X TIMER_0 Y20 -4400 2500 200 R 40 40 1 1 B 
X TIMER_1 V18 -4400 2400 200 R 40 40 1 1 B 
X TIMER_2 D3 -4400 2300 200 R 40 40 1 1 B 
X TIMER_3 D2 -4400 2200 200 R 40 40 1 1 B 
X TIMER_4 D1 -4400 2100 200 R 40 40 1 1 B 
X TIMER_5 E3 -4400 2000 200 R 40 40 1 1 B 
X TIMER_6 E2 -4400 1900 200 R 40 40 1 1 B 
X TIMER_7 E1 -4400 1800 200 R 40 40 1 1 B 
X USB_0 H1 -4400 1500 200 R 40 40 1 1 B 
X USB_1 H2 -4400 1400 200 R 40 40 1 1 B 
X USB_2 H3 -4400 1300 200 R 40 40 1 1 B 
X USB_3 G1 -4400 1200 200 R 40 40 1 1 B 
X USB_4 G2 -4400 1100 200 R 40 40 1 1 B 
X USB_5 G3 -4400 1000 200 R 40 40 1 1 B 
X USB_6 G4 -4400 900 200 R 40 40 1 1 B 
X USB_7 F1 -4400 800 200 R 40 40 1 1 B 
X USB_8 F2 -4400 700 200 R 40 40 1 1 B 
X USB_9 F3 -4400 600 200 R 40 40 1 1 B 
# Gate Name: G$2
# Symbol Name: MPC5200CLK
P 2 2 0 0 -400 700 400 700
P 2 2 0 0 400 700 400 -800
P 2 2 0 0 400 -800 -400 -800
P 2 2 0 0 -400 -800 -400 700
X RTC_XTAL_IN C2 -600 600 200 R 40 40 2 1 I 
X RTC_XTAL_OUT C1 -600 100 200 R 40 40 2 1 I 
X SYS_XTAL_IN A15 -600 -200 200 R 40 40 2 1 I 
X SYS_XTAL_OUT D14 -600 -700 200 R 40 40 2 1 I 
# Gate Name: G$3
# Symbol Name: MPC5200PWR
P 2 3 0 0 -1000 1400 1000 1400
P 2 3 0 0 1000 1400 1000 -2600
P 2 3 0 0 1000 -2600 -1000 -2600
P 2 3 0 0 -1000 -2600 -1000 1400
X CORE_PLL_AVDD C8 -1200 1300 200 R 40 40 3 1 W 
X SYS_PLL_AVDD B14 -1200 1100 200 R 40 40 3 1 W 
X SYS_PLL_AVSS C14 1200 1100 200 L 40 40 3 1 W 
X VDD_CORE@D5 D5 -1200 900 200 R 40 40 3 1 W 
X VDD_CORE@D7 D7 -1200 800 200 R 40 40 3 1 W 
X VDD_CORE@D10 D10 -1200 700 200 R 40 40 3 1 W 
X VDD_CORE@D11 D11 -1200 600 200 R 40 40 3 1 W 
X VDD_CORE@K4 K4 -1200 500 200 R 40 40 3 1 W 
X VDD_CORE@M4 M4 -1200 400 200 R 40 40 3 1 W 
X VDD_CORE@P4 P4 -1200 300 200 R 40 40 3 1 W 
X VDD_CORE@U7 U7 -1200 200 200 R 40 40 3 1 W 
X VDD_CORE@U12 U12 -1200 100 200 R 40 40 3 1 W 
X VDD_CORE@U15 U15 -1200 0 200 R 40 40 3 1 W 
X VDD_IO@D6 D6 -1200 -200 200 R 40 40 3 1 W 
X VDD_IO@D9 D9 -1200 -300 200 R 40 40 3 1 W 
X VDD_IO@E4 E4 -1200 -400 200 R 40 40 3 1 W 
X VDD_IO@F4 F4 -1200 -500 200 R 40 40 3 1 W 
X VDD_IO@H4 H4 -1200 -600 200 R 40 40 3 1 W 
X VDD_IO@T4 T4 -1200 -700 200 R 40 40 3 1 W 
X VDD_IO@U5 U5 -1200 -800 200 R 40 40 3 1 W 
X VDD_IO@U6 U6 -1200 -900 200 R 40 40 3 1 W 
X VDD_IO@U9 U9 -1200 -1000 200 R 40 40 3 1 W 
X VDD_IO@U10 U10 -1200 -1100 200 R 40 40 3 1 W 
X VDD_IO@U13 U13 -1200 -1200 200 R 40 40 3 1 W 
X VDD_IO@U16 U16 -1200 -1300 200 R 40 40 3 1 W 
X VDD_MEM_IO@D12 D12 -1200 -1500 200 R 40 40 3 1 W 
X VDD_MEM_IO@D13 D13 -1200 -1600 200 R 40 40 3 1 W 
X VDD_MEM_IO@D15 D15 -1200 -1700 200 R 40 40 3 1 W 
X VDD_MEM_IO@D17 D17 -1200 -1800 200 R 40 40 3 1 W 
X VDD_MEM_IO@E17 E17 -1200 -1900 200 R 40 40 3 1 W 
X VDD_MEM_IO@F17 F17 -1200 -2000 200 R 40 40 3 1 W 
X VDD_MEM_IO@H17 H17 -1200 -2100 200 R 40 40 3 1 W 
X VDD_MEM_IO@K17 K17 -1200 -2200 200 R 40 40 3 1 W 
X VDD_MEM_IO@M17 M17 -1200 -2300 200 R 40 40 3 1 W 
X VDD_MEM_IO@P17 P17 -1200 -2400 200 R 40 40 3 1 W 
X VDD_MEM_IO@T17 T17 -1200 -2500 200 R 40 40 3 1 W 
X VSS_IO/CORE@D4 D4 1200 900 200 L 40 40 3 1 W 
X VSS_IO/CORE@D16 D16 1200 800 200 L 40 40 3 1 W 
X VSS_IO/CORE@J9 J9 1200 700 200 L 40 40 3 1 W 
X VSS_IO/CORE@J10 J10 1200 600 200 L 40 40 3 1 W 
X VSS_IO/CORE@J11 J11 1200 500 200 L 40 40 3 1 W 
X VSS_IO/CORE@J12 J12 1200 400 200 L 40 40 3 1 W 
X VSS_IO/CORE@K9 K9 1200 300 200 L 40 40 3 1 W 
X VSS_IO/CORE@K10 K10 1200 200 200 L 40 40 3 1 W 
X VSS_IO/CORE@K11 K11 1200 100 200 L 40 40 3 1 W 
X VSS_IO/CORE@K12 K12 1200 0 200 L 40 40 3 1 W 
X VSS_IO/CORE@L9 L9 1200 -100 200 L 40 40 3 1 W 
X VSS_IO/CORE@L10 L10 1200 -200 200 L 40 40 3 1 W 
X VSS_IO/CORE@L11 L11 1200 -300 200 L 40 40 3 1 W 
X VSS_IO/CORE@L12 L12 1200 -400 200 L 40 40 3 1 W 
X VSS_IO/CORE@M9 M9 1200 -500 200 L 40 40 3 1 W 
X VSS_IO/CORE@M10 M10 1200 -600 200 L 40 40 3 1 W 
X VSS_IO/CORE@M11 M11 1200 -700 200 L 40 40 3 1 W 
X VSS_IO/CORE@M12 M12 1200 -800 200 L 40 40 3 1 W 
X VSS_IO/CORE@U4 U4 1200 -900 200 L 40 40 3 1 W 
X VSS_IO/CORE@U17 U17 1200 -1000 200 L 40 40 3 1 W 
ENDDRAW
ENDDEF

#End Library