EESchema-LIBRARY Version 2.3 29/04/2008-12:23:16 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 57 # # Dev Name: 74160D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74160D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74160D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74160N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74160N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74160N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74161D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74161D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74161D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74161N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74161N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74161N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74162D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74162D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74162D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74162N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74162N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74162N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74163D # Package Name: SO16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74163D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74163D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74163N # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 74163N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74163N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS160D # Package Name: SO16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS160D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS160D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS160N # Package Name: DIL16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS160N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS160N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS161D # Package Name: SO16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS161D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS161D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS161N # Package Name: DIL16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS161N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS161N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS162D # Package Name: SO16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS162D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS162D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS162N # Package Name: DIL16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS162N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS162N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS163D # Package Name: SO16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS163D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS163D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74ALS163N # Package Name: DIL16 # Dev Tech: ALS # Dev Prefix: U # Gate count = 2 # DEF 74ALS163N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74ALS163N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F160D # Package Name: SO16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F160D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F160D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F160N # Package Name: DIL16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F160N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F160N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F161D # Package Name: SO16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F161D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F161D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F161N # Package Name: DIL16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F161N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F161N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F162D # Package Name: SO16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F162D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F162D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F162N # Package Name: DIL16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F162N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F162N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F163D # Package Name: SO16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F163D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F163D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74F163N # Package Name: DIL16 # Dev Tech: F # Dev Prefix: U # Gate count = 2 # DEF 74F163N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74F163N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS160D # Package Name: SO16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS160D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS160D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS160N # Package Name: DIL16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS160N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS160N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS161D # Package Name: SO16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS161D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS161D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS161N # Package Name: DIL16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS161N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS161N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS162D # Package Name: SO16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS162D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS162D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS162N # Package Name: DIL16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS162N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS162N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS163D # Package Name: SO16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS163D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS163D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74LS163N # Package Name: DIL16 # Dev Tech: LS # Dev Prefix: U # Gate count = 2 # DEF 74LS163N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74LS163N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S160D # Package Name: SO16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S160D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S160D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S160N # Package Name: DIL16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S160N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S160N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S161D # Package Name: SO16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S161D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S161D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S161N # Package Name: DIL16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S161N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S161N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S162D # Package Name: SO16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S162D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S162D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S162N # Package Name: DIL16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S162N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S162N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S163D # Package Name: SO16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S163D U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S163D" 0 50 50 H V L B F2 "oldchips-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 74S163N # Package Name: DIL16 # Dev Tech: S # Dev Prefix: U # Gate count = 2 # DEF 74S163N U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 74160-3 F0 "U" 0 150 50 H V L B F1 "74S163N" 0 50 50 H V L B F2 "oldchips-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1100 600 -1100 P 2 1 0 0 600 -1100 600 0 P 2 1 0 0 600 0 0 0 P 2 1 0 0 0 0 0 -1100 X A 3 -200 -100 200 R 40 40 1 1 I X B 4 -200 -200 200 R 40 40 1 1 I X C 5 -200 -300 200 R 40 40 1 1 I X CLK 2 -200 -600 200 R 40 40 1 1 I C X CLR 1 -200 -1000 200 R 40 40 1 1 I I X D 6 -200 -400 200 R 40 40 1 1 I X ENP 7 -200 -700 200 R 40 40 1 1 I X ENT 10 -200 -800 200 R 40 40 1 1 I X LD 9 -200 -900 200 R 40 40 1 1 I I X QA 14 800 -100 200 L 40 40 1 1 O X QB 13 800 -200 200 L 40 40 1 1 O X QC 12 800 -300 200 L 40 40 1 1 O X QD 11 800 -400 200 L 40 40 1 1 O X RCO 15 800 -1000 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 8 0 -300 200 U 40 40 2 1 W X VCC 16 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 80CE558 # Package Name: QFP80R # Dev Tech: '' # Dev Prefix: U # Gate count = 9 # DEF 80CE558 U 0 40 Y Y 9 L N # Gate Name: NC1 # Symbol Name: NC F0 "U" 25 -25 50 H V L B F1 "80CE558" 0 0 50 H V L B F2 "oldchips-QFP80R" 0 150 50 H I C C DRAW X NC 49 -100 0 100 R 40 40 1 1 U # Gate Name: NC2 # Symbol Name: NC X NC 50 -100 0 100 R 40 40 2 1 U # Gate Name: P1 # Symbol Name: VDDVSS T 1 50 180 50 0 3 0 VDD T 1 50 -155 50 0 3 0 VSS X VDD 14 0 300 200 D 40 40 3 1 W X VSS 13 0 -300 200 U 40 40 3 1 W # Gate Name: P2 # Symbol Name: VDDVSS T 1 50 180 50 0 4 0 VDD T 1 50 -155 50 0 4 0 VSS X VDD 28 0 300 200 D 40 40 4 1 W X VSS 29 0 -300 200 U 40 40 4 1 W # Gate Name: P3 # Symbol Name: VDDVSS T 1 50 180 50 0 5 0 VDD T 1 50 -155 50 0 5 0 VSS X VDD 53 0 300 200 D 40 40 5 1 W X VSS 54 0 -300 200 U 40 40 5 1 W # Gate Name: P4 # Symbol Name: VDDVSS T 1 50 180 50 0 6 0 VDD T 1 50 -155 50 0 6 0 VSS X VDD 66 0 300 200 D 40 40 6 1 W X VSS 67 0 -300 200 U 40 40 6 1 W # Gate Name: _ANALOG # Symbol Name: 558_ANALOG P 2 7 0 0 0 0 700 0 P 2 7 0 0 700 -2000 0 -2000 P 2 7 0 0 0 -2000 0 0 P 2 7 0 0 700 0 700 -2000 X ADEXS 15 -200 -100 200 R 40 40 7 1 I X AVDD1 4 -200 -300 200 R 40 40 7 1 I X AVDD2 76 -200 -400 200 R 40 40 7 1 I X AVREF+ 2 -200 -600 200 R 40 40 7 1 I X AVREF- 1 -200 -700 200 R 40 40 7 1 I X AVSS1 3 -200 -900 200 R 40 40 7 1 I X AVSS2 77 -200 -1000 200 R 40 40 7 1 I X P5.0-ADC0 12 -200 -1200 200 R 40 40 7 1 B X P5.1-ADC1 11 -200 -1300 200 R 40 40 7 1 B X P5.2-ADC2 10 -200 -1400 200 R 40 40 7 1 B X P5.3-ADC3 9 -200 -1500 200 R 40 40 7 1 B X P5.4-ADC4 8 -200 -1600 200 R 40 40 7 1 B X P5.5-ADC5 7 -200 -1700 200 R 40 40 7 1 B X P5.6-ADC6 6 -200 -1800 200 R 40 40 7 1 B X P5.7-ADC7 5 -200 -1900 200 R 40 40 7 1 B # Gate Name: _CPU # Symbol Name: 558_CPU P 2 8 0 0 0 0 1100 0 P 2 8 0 0 1100 -2300 0 -2300 P 2 8 0 0 0 -2300 0 0 P 2 8 0 0 1100 0 1100 -2300 X A08-P2.0 55 1300 -1300 200 L 40 40 8 1 B X A09-P2.1 56 1300 -1200 200 L 40 40 8 1 B X A10-P2.2 57 1300 -1100 200 L 40 40 8 1 B X A11-P2.3 58 1300 -1000 200 L 40 40 8 1 B X A12-P2.4 59 1300 -900 200 L 40 40 8 1 B X A13-P2.5 60 1300 -800 200 L 40 40 8 1 B X A14-P2.6 61 1300 -700 200 L 40 40 8 1 B X A15-P2.7 62 1300 -600 200 L 40 40 8 1 B X AD0-P0.0 75 1300 -2200 200 L 40 40 8 1 B X AD1-P0.1 74 1300 -2100 200 L 40 40 8 1 B X AD2-P0.2 73 1300 -2000 200 L 40 40 8 1 B X AD3-P0.3 72 1300 -1900 200 L 40 40 8 1 B X AD4-P0.4 71 1300 -1800 200 L 40 40 8 1 B X AD5-P0.5 70 1300 -1700 200 L 40 40 8 1 B X AD6-P0.6 69 1300 -1600 200 L 40 40 8 1 B X AD7-P0.7 68 1300 -1500 200 L 40 40 8 1 B X ALE-PROG/ 64 1300 -100 200 L 40 40 8 1 O X EA/VPP 65 -200 -1300 200 R 40 40 8 1 I X EW/ 18 -200 -300 200 R 40 40 8 1 I X P3.6-WR/ 47 1300 -400 200 L 40 40 8 1 B X P3.7-RD/ 48 1300 -300 200 L 40 40 8 1 B X PSEN/ 63 1300 -200 200 L 40 40 8 1 O X RSTIN 30 -200 -200 200 R 40 40 8 1 I X RSTOUT 23 -200 -100 200 R 40 40 8 1 O X SELXTAL1 80 -200 -1100 200 R 40 40 8 1 I X XTAL1 52 -200 -500 200 R 40 40 8 1 I X XTAL2 51 -200 -600 200 R 40 40 8 1 O X XTAL3 78 -200 -800 200 R 40 40 8 1 I X XTAL4 79 -200 -900 200 R 40 40 8 1 O # Gate Name: _PORTS # Symbol Name: 558_PORTS P 2 9 0 0 0 0 700 0 P 2 9 0 0 700 -3100 0 -3100 P 2 9 0 0 0 -3100 0 0 P 2 9 0 0 700 0 700 -3100 X CT0I-P1.0 31 900 -2100 200 L 40 40 9 1 B X CT1I-P1.1 32 900 -2000 200 L 40 40 9 1 B X CT2I-P1.2 33 900 -1900 200 L 40 40 9 1 B X CT3I-P1.3 34 900 -1800 200 L 40 40 9 1 B X P1.6 37 900 -1500 200 L 40 40 9 1 B X P1.7 38 900 -1400 200 L 40 40 9 1 B X P3.0-RXD 41 900 -1200 200 L 40 40 9 1 B X P3.1-TXD 42 900 -1100 200 L 40 40 9 1 B X P3.2-INT0/ 43 900 -1000 200 L 40 40 9 1 B X P3.3-INT1/ 44 900 -900 200 L 40 40 9 1 B X P3.4-T0 45 900 -800 200 L 40 40 9 1 B X P3.5-T1 46 900 -700 200 L 40 40 9 1 B X P4.0-CMSR0 19 900 -3000 200 L 40 40 9 1 B X P4.1-CMSR1 20 900 -2900 200 L 40 40 9 1 B X P4.2-CMSR2 21 900 -2800 200 L 40 40 9 1 B X P4.3-CMSR3 22 900 -2700 200 L 40 40 9 1 B X P4.4-CMSR4 24 900 -2600 200 L 40 40 9 1 B X P4.5-CMSR5 25 900 -2500 200 L 40 40 9 1 B X P4.6-CMT0 26 900 -2400 200 L 40 40 9 1 B X P4.7-CMT1 27 900 -2300 200 L 40 40 9 1 B X PWM0/ 16 900 -500 200 L 40 40 9 1 O X PWM1/ 17 900 -400 200 L 40 40 9 1 O X RT2-P1.5 36 900 -1600 200 L 40 40 9 1 B X SCL 39 900 -100 200 L 40 40 9 1 B X SDA 40 900 -200 200 L 40 40 9 1 B X T2-P1.4 35 900 -1700 200 L 40 40 9 1 B ENDDRAW ENDDEF # # Dev Name: 8742 # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 8742 U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 8742 F0 "U" 0 150 50 H V L B F1 "8742" 0 50 50 H V L B F2 "oldchips-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 0 -2500 P 2 1 0 0 0 -2500 900 -2500 P 2 1 0 0 900 -2500 900 0 P 2 1 0 0 900 0 0 0 X /CS 6 -200 -1100 200 R 40 40 1 1 I I X /RD 8 -200 -1200 200 R 40 40 1 1 I I X /RESET 4 -200 -1000 200 R 40 40 1 1 I I X /SS 5 -200 -700 200 R 40 40 1 1 I I X /WR 10 -200 -1300 200 R 40 40 1 1 I I X A0 9 -200 -1500 200 R 40 40 1 1 I X D0 12 -200 -2400 200 R 40 40 1 1 B X D1 13 -200 -2300 200 R 40 40 1 1 B X D2 14 -200 -2200 200 R 40 40 1 1 B X D3 15 -200 -2100 200 R 40 40 1 1 B X D4 16 -200 -2000 200 R 40 40 1 1 B X D5 17 -200 -1900 200 R 40 40 1 1 B X D6 18 -200 -1800 200 R 40 40 1 1 B X D7 19 -200 -1700 200 R 40 40 1 1 B X EA 7 -200 -800 200 R 40 40 1 1 I X P10 27 1100 -2400 200 L 40 40 1 1 B X P11 28 1100 -2300 200 L 40 40 1 1 B X P12 29 1100 -2200 200 L 40 40 1 1 B X P13 30 1100 -2100 200 L 40 40 1 1 B X P14 31 1100 -2000 200 L 40 40 1 1 B X P15 32 1100 -1900 200 L 40 40 1 1 B X P16 33 1100 -1800 200 L 40 40 1 1 B X P17 34 1100 -1700 200 L 40 40 1 1 B X P20 21 1100 -1500 200 L 40 40 1 1 B X P21 22 1100 -1400 200 L 40 40 1 1 B X P22 23 1100 -1300 200 L 40 40 1 1 B X P23 24 1100 -1200 200 L 40 40 1 1 B X P24/OBF 35 1100 -1100 200 L 40 40 1 1 B X P25//IBF 36 1100 -1000 200 L 40 40 1 1 B X P26/DRQ 37 1100 -900 200 L 40 40 1 1 B X P27//DACK 38 1100 -800 200 L 40 40 1 1 B X PROG 25 -200 -500 200 R 40 40 1 1 B X SYNC 11 -200 -400 200 R 40 40 1 1 O X TEST0 1 1100 -600 200 L 40 40 1 1 I X TEST1 39 1100 -500 200 L 40 40 1 1 I X VDD 26 -200 -600 200 R 40 40 1 1 w X XTAL1 2 -200 -100 200 R 40 40 1 1 I X XTAL2 3 -200 -200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: VCCVSS T 1 50 -155 50 0 2 0 VSS T 1 50 180 50 0 2 0 VCC X VCC 40 0 300 200 D 40 40 2 1 W X VSS 20 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: 8748 # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF 8748 U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: 8748 F0 "U" 0 150 50 H V L B F1 "8748" 0 50 50 H V L B F2 "oldchips-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 0 -2500 P 2 1 0 0 0 -2500 800 -2500 P 2 1 0 0 800 -2500 800 0 P 2 1 0 0 800 0 0 0 X /INT 6 -200 -1000 200 R 40 40 1 1 B I X /PSEN 9 -200 -1500 200 R 40 40 1 1 O I X /RD 8 -200 -1300 200 R 40 40 1 1 O I X /RESET 4 -200 -900 200 R 40 40 1 1 I I X /SS 5 -200 -600 200 R 40 40 1 1 I I X /WR 10 -200 -1400 200 R 40 40 1 1 O I X ALE 11 -200 -1200 200 R 40 40 1 1 O X DB0 12 -200 -2400 200 R 40 40 1 1 B X DB1 13 -200 -2300 200 R 40 40 1 1 B X DB2 14 -200 -2200 200 R 40 40 1 1 B X DB3 15 -200 -2100 200 R 40 40 1 1 B X DB4 16 -200 -2000 200 R 40 40 1 1 B X DB5 17 -200 -1900 200 R 40 40 1 1 B X DB6 18 -200 -1800 200 R 40 40 1 1 B X DB7 19 -200 -1700 200 R 40 40 1 1 B X EA 7 -200 -700 200 R 40 40 1 1 I X P10 27 1000 -2400 200 L 40 40 1 1 B X P11 28 1000 -2300 200 L 40 40 1 1 B X P12 29 1000 -2200 200 L 40 40 1 1 B X P13 30 1000 -2100 200 L 40 40 1 1 B X P14 31 1000 -2000 200 L 40 40 1 1 B X P15 32 1000 -1900 200 L 40 40 1 1 B X P16 33 1000 -1800 200 L 40 40 1 1 B X P17 34 1000 -1700 200 L 40 40 1 1 B X P20 21 1000 -1500 200 L 40 40 1 1 B X P21 22 1000 -1400 200 L 40 40 1 1 B X P22 23 1000 -1300 200 L 40 40 1 1 B X P23 24 1000 -1200 200 L 40 40 1 1 B X P24 35 1000 -1100 200 L 40 40 1 1 B X P25 36 1000 -1000 200 L 40 40 1 1 B X P26 37 1000 -900 200 L 40 40 1 1 B X P27 38 1000 -800 200 L 40 40 1 1 B X PROG 25 -200 -500 200 R 40 40 1 1 B X T0 1 1000 -600 200 L 40 40 1 1 I X T1 39 1000 -500 200 L 40 40 1 1 I X VDD 26 -200 -400 200 R 40 40 1 1 w X XTAL1 2 -200 -100 200 R 40 40 1 1 I X XTAL2 3 -200 -200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: VCCVSS T 1 50 -155 50 0 2 0 VSS T 1 50 180 50 0 2 0 VCC X VCC 40 0 300 200 D 40 40 2 1 W X VSS 20 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: AD7824N # Package Name: DIL24-3 # Dev Tech: '' # Dev Prefix: U # Gate count = 4 # DEF AD7824N U 0 40 Y Y 4 L N # Gate Name: G$1 # Symbol Name: AD7824 F0 "U" 0 150 50 H V L B F1 "AD7824N" 0 50 50 H V L B F2 "oldchips-DIL24-3" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 700 0 P 2 1 0 0 700 0 700 -1800 P 2 1 0 0 700 -1800 0 -1800 P 2 1 0 0 0 -1800 0 0 X /CS 16 900 -500 200 L 40 40 1 1 I I X /INT 11 900 -100 200 L 40 40 1 1 B I X /RD 10 900 -400 200 L 40 40 1 1 I I X A0 22 900 -800 200 L 40 40 1 1 I X A1 21 900 -700 200 L 40 40 1 1 I X AIN1 4 -200 -1400 200 R 40 40 1 1 I X AIN2 3 -200 -1300 200 R 40 40 1 1 I X AIN3 2 -200 -1200 200 R 40 40 1 1 I X AIN4 1 -200 -1100 200 R 40 40 1 1 I X DB0 6 900 -1700 200 L 40 40 1 1 B X DB1 7 900 -1600 200 L 40 40 1 1 B X DB2 8 900 -1500 200 L 40 40 1 1 B X DB3 9 900 -1400 200 L 40 40 1 1 B X DB4 17 900 -1300 200 L 40 40 1 1 B X DB5 18 900 -1200 200 L 40 40 1 1 B X DB6 19 900 -1100 200 L 40 40 1 1 B X DB7 20 900 -1000 200 L 40 40 1 1 B X RDY 15 900 -200 200 L 40 40 1 1 B X VREF+ 14 -200 -1600 200 R 40 40 1 1 W X VREF- 13 -200 -1700 200 R 40 40 1 1 W # Gate Name: NC1 # Symbol Name: NC X NC 5 -100 0 100 R 40 40 2 1 U # Gate Name: NC2 # Symbol Name: NC X NC 23 -100 0 100 R 40 40 3 1 U # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 4 0 VCC T 1 50 -155 50 0 4 0 GND X GND 12 0 -300 200 U 40 40 4 1 W X VCC 24 0 300 200 D 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: AD7824R # Package Name: SO24W # Dev Tech: '' # Dev Prefix: U # Gate count = 4 # DEF AD7824R U 0 40 Y Y 4 L N # Gate Name: G$1 # Symbol Name: AD7824 F0 "U" 0 150 50 H V L B F1 "AD7824R" 0 50 50 H V L B F2 "oldchips-SO24W" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 700 0 P 2 1 0 0 700 0 700 -1800 P 2 1 0 0 700 -1800 0 -1800 P 2 1 0 0 0 -1800 0 0 X /CS 16 900 -500 200 L 40 40 1 1 I I X /INT 11 900 -100 200 L 40 40 1 1 B I X /RD 10 900 -400 200 L 40 40 1 1 I I X A0 22 900 -800 200 L 40 40 1 1 I X A1 21 900 -700 200 L 40 40 1 1 I X AIN1 4 -200 -1400 200 R 40 40 1 1 I X AIN2 3 -200 -1300 200 R 40 40 1 1 I X AIN3 2 -200 -1200 200 R 40 40 1 1 I X AIN4 1 -200 -1100 200 R 40 40 1 1 I X DB0 6 900 -1700 200 L 40 40 1 1 B X DB1 7 900 -1600 200 L 40 40 1 1 B X DB2 8 900 -1500 200 L 40 40 1 1 B X DB3 9 900 -1400 200 L 40 40 1 1 B X DB4 17 900 -1300 200 L 40 40 1 1 B X DB5 18 900 -1200 200 L 40 40 1 1 B X DB6 19 900 -1100 200 L 40 40 1 1 B X DB7 20 900 -1000 200 L 40 40 1 1 B X RDY 15 900 -200 200 L 40 40 1 1 B X VREF+ 14 -200 -1600 200 R 40 40 1 1 W X VREF- 13 -200 -1700 200 R 40 40 1 1 W # Gate Name: NC1 # Symbol Name: NC X NC 5 -100 0 100 R 40 40 2 1 U # Gate Name: NC2 # Symbol Name: NC X NC 23 -100 0 100 R 40 40 3 1 U # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 4 0 VCC T 1 50 -155 50 0 4 0 GND X GND 12 0 -300 200 U 40 40 4 1 W X VCC 24 0 300 200 D 40 40 4 1 W ENDDRAW ENDDEF # # Dev Name: AY-3-1015 # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 3 # DEF AY-3-1015 U 0 40 Y Y 3 L N # Gate Name: >NAME # Symbol Name: AY-3-1015 F0 "U" 0 150 50 H V L B F1 "AY-3-1015" 0 50 50 H V L B F2 "oldchips-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 700 0 P 2 1 0 0 700 0 700 -2600 P 2 1 0 0 700 -2600 0 -2600 P 2 1 0 0 0 -2600 0 0 X /DS 23 -200 -600 200 R 40 40 1 1 I I X /RDAV 18 -200 -200 200 R 40 40 1 1 I I X /RDE 4 -200 -400 200 R 40 40 1 1 I I X /SWE 16 -200 -500 200 R 40 40 1 1 I I X CS 34 -200 -700 200 R 40 40 1 1 I X DAV 19 900 -1500 200 L 40 40 1 1 T X DB1 26 -200 -2500 200 R 40 40 1 1 I X DB2 27 -200 -2400 200 R 40 40 1 1 I X DB3 28 -200 -2300 200 R 40 40 1 1 I X DB4 29 -200 -2200 200 R 40 40 1 1 I X DB5 30 -200 -2100 200 R 40 40 1 1 I X DB6 31 -200 -2000 200 R 40 40 1 1 I X DB7 32 -200 -1900 200 R 40 40 1 1 I X DB8 33 -200 -1800 200 R 40 40 1 1 I X EOC 24 900 -2500 200 L 40 40 1 1 O X EPS 39 900 -2200 200 L 40 40 1 1 I X FE 14 900 -1300 200 L 40 40 1 1 T X NB1 38 900 -2100 200 L 40 40 1 1 I X NB2 37 900 -2000 200 L 40 40 1 1 I X NP 35 900 -1800 200 L 40 40 1 1 I X OR 15 900 -1400 200 L 40 40 1 1 T X PE 13 900 -1200 200 L 40 40 1 1 T X RCP 17 900 -100 200 L 40 40 1 1 I X RD1 12 -200 -1600 200 R 40 40 1 1 T X RD2 11 -200 -1500 200 R 40 40 1 1 T X RD3 10 -200 -1400 200 R 40 40 1 1 T X RD4 9 -200 -1300 200 R 40 40 1 1 T X RD5 8 -200 -1200 200 R 40 40 1 1 T X RD6 7 -200 -1100 200 R 40 40 1 1 T X RD7 6 -200 -1000 200 R 40 40 1 1 T X RD8 5 -200 -900 200 R 40 40 1 1 T X SI 20 900 -400 200 L 40 40 1 1 I X SO 25 900 -500 200 L 40 40 1 1 O X TBMT 22 900 -1600 200 L 40 40 1 1 T X TCP 40 900 -200 200 L 40 40 1 1 I X TSB 36 900 -1900 200 L 40 40 1 1 I X XR 21 -200 -100 200 R 40 40 1 1 I # Gate Name: NC # Symbol Name: NC X NC 2 -100 0 100 R 40 40 2 1 U # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 3 0 VCC T 1 50 -155 50 0 3 0 GND X GND 3 0 -300 200 U 40 40 3 1 W X VCC 1 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: AY-3-8910 # Package Name: DIL28-6 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF AY-3-8910 U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: AY-3-8910 F0 "U" 0 150 50 H V L B F1 "AY-3-8910" 0 50 50 H V L B F2 "oldchips-DIL28-6" 0 150 50 H I C C DRAW P 2 1 0 0 0 -1700 0 0 P 2 1 0 0 0 0 800 0 P 2 1 0 0 800 -1700 0 -1700 P 2 1 0 0 800 0 800 -1700 X /RST 16 -200 -100 200 R 40 40 1 1 I I X A8 17 -200 -300 200 R 40 40 1 1 I X A_CHA 5 1000 -100 200 L 40 40 1 1 O X A_CHB 4 1000 -200 200 L 40 40 1 1 O X A_CHC 1 1000 -300 200 L 40 40 1 1 O X BC1 20 -200 -500 200 R 40 40 1 1 I X BC2 19 -200 -600 200 R 40 40 1 1 I X BDIR 18 -200 -700 200 R 40 40 1 1 I X CLK 15 -200 -200 200 R 40 40 1 1 I C X DA0 28 -200 -900 200 R 40 40 1 1 B X DA1 27 -200 -1000 200 R 40 40 1 1 B X DA2 26 -200 -1100 200 R 40 40 1 1 B X DA3 25 -200 -1200 200 R 40 40 1 1 B X DA4 24 -200 -1300 200 R 40 40 1 1 B X DA5 23 -200 -1400 200 R 40 40 1 1 B X DA6 22 -200 -1500 200 R 40 40 1 1 B X DA7 21 -200 -1600 200 R 40 40 1 1 B X IOA0 14 1000 -900 200 L 40 40 1 1 B X IOA1 13 1000 -1000 200 L 40 40 1 1 B X IOA2 12 1000 -1100 200 L 40 40 1 1 B X IOA3 11 1000 -1200 200 L 40 40 1 1 B X IOA4 10 1000 -1300 200 L 40 40 1 1 B X IOA5 9 1000 -1400 200 L 40 40 1 1 B X IOA6 8 1000 -1500 200 L 40 40 1 1 B X IOA7 7 1000 -1600 200 L 40 40 1 1 B X TEST1 2 1000 -500 200 L 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 6 0 -300 200 U 40 40 2 1 W X VCC 3 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: AY-3-8912 # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF AY-3-8912 U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: AY-3-8912 F0 "U" 0 150 50 H V L B F1 "AY-3-8912" 0 50 50 H V L B F2 "oldchips-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 0 -2400 0 0 P 2 1 0 0 800 0 800 -2400 P 2 1 0 0 800 -2400 0 -2400 P 2 1 0 0 0 0 800 0 X /A9 24 -200 -900 200 R 40 40 1 1 I I X /RESET 23 -200 -600 200 R 40 40 1 1 I I X A8 25 -200 -800 200 R 40 40 1 1 I X A_CHA 4 1000 -100 200 L 40 40 1 1 O X A_CHB 3 1000 -200 200 L 40 40 1 1 O X A_CHC 38 1000 -300 200 L 40 40 1 1 O X BC1 29 -200 -1200 200 R 40 40 1 1 I X BC2 28 -200 -1300 200 R 40 40 1 1 I X BDIR 27 -200 -1400 200 R 40 40 1 1 I X CLOCK 22 -200 -700 200 R 40 40 1 1 I C X DA0 37 -200 -1600 200 R 40 40 1 1 B X DA1 36 -200 -1700 200 R 40 40 1 1 B X DA2 35 -200 -1800 200 R 40 40 1 1 B X DA3 34 -200 -1900 200 R 40 40 1 1 B X DA4 33 -200 -2000 200 R 40 40 1 1 B X DA5 32 -200 -2100 200 R 40 40 1 1 B X DA6 31 -200 -2200 200 R 40 40 1 1 B X DA7 30 -200 -2300 200 R 40 40 1 1 B X IOA0 21 1000 -700 200 L 40 40 1 1 B X IOA1 20 1000 -800 200 L 40 40 1 1 B X IOA2 19 1000 -900 200 L 40 40 1 1 B X IOA3 18 1000 -1000 200 L 40 40 1 1 B X IOA4 17 1000 -1100 200 L 40 40 1 1 B X IOA5 16 1000 -1200 200 L 40 40 1 1 B X IOA6 15 1000 -1300 200 L 40 40 1 1 B X IOA7 14 1000 -1400 200 L 40 40 1 1 B X IOB0 13 1000 -1600 200 L 40 40 1 1 B X IOB1 12 1000 -1700 200 L 40 40 1 1 B X IOB2 11 1000 -1800 200 L 40 40 1 1 B X IOB3 10 1000 -1900 200 L 40 40 1 1 B X IOB4 9 1000 -2000 200 L 40 40 1 1 B X IOB5 8 1000 -2100 200 L 40 40 1 1 B X IOB6 7 1000 -2200 200 L 40 40 1 1 B X IOB7 6 1000 -2300 200 L 40 40 1 1 B X NC 2 -200 -100 200 R 40 40 1 1 U X NC2 5 -200 -200 200 R 40 40 1 1 U X TEST1 39 -200 -300 200 R 40 40 1 1 I X TEST2 26 -200 -400 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 1 0 -300 200 U 40 40 2 1 W X VCC 40 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: AY-5-1013A # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF AY-5-1013A U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: AY-3-1015 F0 "U" 0 150 50 H V L B F1 "AY-5-1013A" 0 50 50 H V L B F2 "oldchips-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 700 0 P 2 1 0 0 700 0 700 -2600 P 2 1 0 0 700 -2600 0 -2600 P 2 1 0 0 0 -2600 0 0 X /DS 23 -200 -600 200 R 40 40 1 1 I I X /RDAV 18 -200 -200 200 R 40 40 1 1 I I X /RDE 4 -200 -400 200 R 40 40 1 1 I I X /SWE 16 -200 -500 200 R 40 40 1 1 I I X CS 34 -200 -700 200 R 40 40 1 1 I X DAV 19 900 -1500 200 L 40 40 1 1 T X DB1 26 -200 -2500 200 R 40 40 1 1 I X DB2 27 -200 -2400 200 R 40 40 1 1 I X DB3 28 -200 -2300 200 R 40 40 1 1 I X DB4 29 -200 -2200 200 R 40 40 1 1 I X DB5 30 -200 -2100 200 R 40 40 1 1 I X DB6 31 -200 -2000 200 R 40 40 1 1 I X DB7 32 -200 -1900 200 R 40 40 1 1 I X DB8 33 -200 -1800 200 R 40 40 1 1 I X EOC 24 900 -2500 200 L 40 40 1 1 O X EPS 39 900 -2200 200 L 40 40 1 1 I X FE 14 900 -1300 200 L 40 40 1 1 T X NB1 38 900 -2100 200 L 40 40 1 1 I X NB2 37 900 -2000 200 L 40 40 1 1 I X NP 35 900 -1800 200 L 40 40 1 1 I X OR 15 900 -1400 200 L 40 40 1 1 T X PE 13 900 -1200 200 L 40 40 1 1 T X RCP 17 900 -100 200 L 40 40 1 1 I X RD1 12 -200 -1600 200 R 40 40 1 1 T X RD2 11 -200 -1500 200 R 40 40 1 1 T X RD3 10 -200 -1400 200 R 40 40 1 1 T X RD4 9 -200 -1300 200 R 40 40 1 1 T X RD5 8 -200 -1200 200 R 40 40 1 1 T X RD6 7 -200 -1100 200 R 40 40 1 1 T X RD7 6 -200 -1000 200 R 40 40 1 1 T X RD8 5 -200 -900 200 R 40 40 1 1 T X SI 20 900 -400 200 L 40 40 1 1 I X SO 25 900 -500 200 L 40 40 1 1 O X TBMT 22 900 -1600 200 L 40 40 1 1 T X TCP 40 900 -200 200 L 40 40 1 1 I X TSB 36 900 -1900 200 L 40 40 1 1 I X XR 21 -200 -100 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: VCCVGGGND T 1 -50 180 50 0 2 0 VCC T 1 150 180 50 0 2 0 VGG T 1 50 -155 50 0 2 0 GND X GND 3 0 -300 200 U 40 40 2 1 W X VCC 1 -100 300 200 D 40 40 2 1 W X VGG 2 100 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: HD6305X2 # Package Name: DIL64-0.70 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF HD6305X2 U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: HD6305 F0 "U" 0 150 50 H V L B F1 "HD6305X2" 0 50 50 H V L B F2 "oldchips-DIL64-0.70" 0 150 50 H I C C DRAW P 2 1 0 0 0 -3700 0 0 P 2 1 0 0 0 0 900 0 P 2 1 0 0 900 0 900 -3700 P 2 1 0 0 900 -3700 0 -3700 X /INT 3 -200 -700 200 R 40 40 1 1 I I X /RES 2 -200 -500 200 R 40 40 1 1 I I X /STBY 4 -200 -900 200 R 40 40 1 1 I I X A0 16 1100 -3600 200 L 40 40 1 1 B X A1 15 1100 -3500 200 L 40 40 1 1 B X A2 14 1100 -3400 200 L 40 40 1 1 B X A3 13 1100 -3300 200 L 40 40 1 1 B X A4 12 1100 -3200 200 L 40 40 1 1 B X A5 11 1100 -3100 200 L 40 40 1 1 B X A6 10 1100 -3000 200 L 40 40 1 1 B X A7 9 1100 -2900 200 L 40 40 1 1 B X ADR0 41 -200 -2700 200 R 40 40 1 1 O X ADR1 42 -200 -2600 200 R 40 40 1 1 O X ADR2 43 -200 -2500 200 R 40 40 1 1 O X ADR3 44 -200 -2400 200 R 40 40 1 1 O X ADR4 45 -200 -2300 200 R 40 40 1 1 O X ADR5 46 -200 -2200 200 R 40 40 1 1 O X ADR6 47 -200 -2100 200 R 40 40 1 1 O X ADR7 48 -200 -2000 200 R 40 40 1 1 O X ADR8 49 -200 -1900 200 R 40 40 1 1 O X ADR9 50 -200 -1800 200 R 40 40 1 1 O X ADR10 51 -200 -1700 200 R 40 40 1 1 O X ADR11 52 -200 -1600 200 R 40 40 1 1 O X ADR12 53 -200 -1500 200 R 40 40 1 1 O X ADR13 54 -200 -1400 200 R 40 40 1 1 O X B0 24 1100 -2700 200 L 40 40 1 1 B X B1 23 1100 -2600 200 L 40 40 1 1 B X B2 22 1100 -2500 200 L 40 40 1 1 B X B3 21 1100 -2400 200 L 40 40 1 1 B X B4 20 1100 -2300 200 L 40 40 1 1 B X B5 19 1100 -2200 200 L 40 40 1 1 B X B6 18 1100 -2100 200 L 40 40 1 1 B X B7 17 1100 -2000 200 L 40 40 1 1 B X C0 32 1100 -1800 200 L 40 40 1 1 B X C1 31 1100 -1700 200 L 40 40 1 1 B X C2 30 1100 -1600 200 L 40 40 1 1 B X C3 29 1100 -1500 200 L 40 40 1 1 B X C4 28 1100 -1400 200 L 40 40 1 1 B X C5//CK 27 1100 -1300 200 L 40 40 1 1 B X C6/RX 26 1100 -1200 200 L 40 40 1 1 B X C7/TX 25 1100 -1100 200 L 40 40 1 1 B X D1 34 1100 -900 200 L 40 40 1 1 B X D2 35 1100 -800 200 L 40 40 1 1 B X D3 36 1100 -700 200 L 40 40 1 1 B X D4 37 1100 -600 200 L 40 40 1 1 B X D5 38 1100 -500 200 L 40 40 1 1 B X D6//INT2 39 1100 -400 200 L 40 40 1 1 B X D7 40 1100 -300 200 L 40 40 1 1 B X DATA0 64 -200 -3600 200 R 40 40 1 1 B X DATA1 63 -200 -3500 200 R 40 40 1 1 B X DATA2 62 -200 -3400 200 R 40 40 1 1 B X DATA3 61 -200 -3300 200 R 40 40 1 1 B X DATA4 60 -200 -3200 200 R 40 40 1 1 B X DATA5 59 -200 -3100 200 R 40 40 1 1 B X DATA6 58 -200 -3000 200 R 40 40 1 1 B X DATA7 57 -200 -2900 200 R 40 40 1 1 B X E 56 -200 -1200 200 R 40 40 1 1 O X EXTAL 6 -200 -100 200 R 40 40 1 1 I X NUM 7 -200 -800 200 R 40 40 1 1 I X R//W 55 -200 -1100 200 R 40 40 1 1 O X TIMER 8 1100 -100 200 L 40 40 1 1 I X XTAL 5 -200 -200 200 R 40 40 1 1 I # Gate Name: P # Symbol Name: VCCVSS T 1 50 -155 50 0 2 0 VSS T 1 50 180 50 0 2 0 VCC X VCC 33 0 300 200 D 40 40 2 1 W X VSS 1 0 -300 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: Z8 # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF Z8 U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: Z8 F0 "U" 0 150 50 H V L B F1 "Z8" 0 50 50 H V L B F2 "oldchips-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 0 -2300 0 0 P 2 1 0 0 0 0 800 0 P 2 1 0 0 800 0 800 -2300 P 2 1 0 0 800 -2300 0 -2300 X /AS 9 1000 -400 200 L 40 40 1 1 O I X /DS 8 1000 -300 200 L 40 40 1 1 O I X /RESET 6 -200 -400 200 R 40 40 1 1 I I X P0.0/A8 13 1000 -1300 200 L 40 40 1 1 B X P0.1/A9 14 1000 -1200 200 L 40 40 1 1 B X P0.2/A10 15 1000 -1100 200 L 40 40 1 1 B X P0.3/A11 16 1000 -1000 200 L 40 40 1 1 B X P0.4/A12 17 1000 -900 200 L 40 40 1 1 B X P0.5/A13 18 1000 -800 200 L 40 40 1 1 B X P0.6/A14 19 1000 -700 200 L 40 40 1 1 B X P0.7/A15 20 1000 -600 200 L 40 40 1 1 B X P1.0/AD0 21 1000 -2200 200 L 40 40 1 1 B X P1.1/AD1 22 1000 -2100 200 L 40 40 1 1 B X P1.2/AD2 23 1000 -2000 200 L 40 40 1 1 B X P1.3/AD3 24 1000 -1900 200 L 40 40 1 1 B X P1.4/AD4 25 1000 -1800 200 L 40 40 1 1 B X P1.5/AD5 26 1000 -1700 200 L 40 40 1 1 B X P1.6/AD6 27 1000 -1600 200 L 40 40 1 1 B X P1.7/AD7 28 1000 -1500 200 L 40 40 1 1 B X P2.0 31 -200 -1300 200 R 40 40 1 1 B X P2.1 32 -200 -1200 200 R 40 40 1 1 B X P2.2 33 -200 -1100 200 R 40 40 1 1 B X P2.3 34 -200 -1000 200 R 40 40 1 1 B X P2.4 35 -200 -900 200 R 40 40 1 1 B X P2.5 36 -200 -800 200 R 40 40 1 1 B X P2.6 37 -200 -700 200 R 40 40 1 1 B X P2.7 38 -200 -600 200 R 40 40 1 1 B X P3.0 5 -200 -2200 200 R 40 40 1 1 B X P3.1 39 -200 -2100 200 R 40 40 1 1 B X P3.2 12 -200 -2000 200 R 40 40 1 1 B X P3.3 30 -200 -1900 200 R 40 40 1 1 B X P3.4 29 -200 -1800 200 R 40 40 1 1 B X P3.5 10 -200 -1700 200 R 40 40 1 1 B X P3.6 40 -200 -1600 200 R 40 40 1 1 B X P3.7 4 -200 -1500 200 R 40 40 1 1 B X R//W 7 1000 -200 200 L 40 40 1 1 O X XTAL1 3 -200 -100 200 R 40 40 1 1 I X XTAL2 2 -200 -200 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 11 0 -300 200 U 40 40 2 1 W X VCC 1 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: Z180 # Package Name: DIL64-0.70 # Dev Tech: '' # Dev Prefix: U # Gate count = 4 # DEF Z180 U 0 40 Y Y 4 L N # Gate Name: P1 # Symbol Name: VCCVSS F0 "U" -25 -25 50 H V L B F1 "Z180" 0 0 50 H V L B F2 "oldchips-DIL64-0.70" 0 150 50 H I C C DRAW T 1 50 -155 50 0 1 0 VSS T 1 50 180 50 0 1 0 VCC X VCC 32 0 300 200 D 40 40 1 1 W X VSS 1 0 -300 200 U 40 40 1 1 W # Gate Name: P2 # Symbol Name: VSS T 0 0 50 50 0 2 0 VSS X VSS 33 0 -100 100 U 40 40 2 1 W # Gate Name: _CPU # Symbol Name: Z180 P 2 3 0 0 0 0 0 -3400 P 2 3 0 0 900 -3400 0 -3400 P 2 3 0 0 900 -3400 900 0 P 2 3 0 0 0 0 900 0 X /BUSACK 5 -200 -1700 200 R 40 40 3 1 O I X /BUSREQ 6 -200 -1800 200 R 40 40 3 1 I I X /DREQ1 54 -200 -3000 200 R 40 40 3 1 I I X /HALT 56 -200 -200 200 R 40 40 3 1 O I X /INT0 9 -200 -2100 200 R 40 40 3 1 I I X /INT1 10 -200 -2200 200 R 40 40 3 1 I I X /INT2 11 -200 -2300 200 R 40 40 3 1 I I X /IORQ 58 1100 -200 200 L 40 40 3 1 O I X /M1 61 -200 -400 200 R 40 40 3 1 O I X /MREQ 59 1100 -100 200 L 40 40 3 1 O I X /NMI 8 -200 -2000 200 R 40 40 3 1 I I X /RD 63 1100 -400 200 L 40 40 3 1 O I X /RESET 7 -200 -2600 200 R 40 40 3 1 I I X /RFSH 57 -200 -300 200 R 40 40 3 1 O I X /TEND1 55 -200 -2900 200 R 40 40 3 1 O I X /WAIT 4 -200 -2500 200 R 40 40 3 1 I I X /WR 62 1100 -300 200 L 40 40 3 1 O I X A0 13 1100 -2400 200 L 40 40 3 1 O X A1 14 1100 -2300 200 L 40 40 3 1 O X A2 15 1100 -2200 200 L 40 40 3 1 O X A3 16 1100 -2100 200 L 40 40 3 1 O X A4 17 1100 -2000 200 L 40 40 3 1 O X A5 18 1100 -1900 200 L 40 40 3 1 O X A6 19 1100 -1800 200 L 40 40 3 1 O X A7 20 1100 -1700 200 L 40 40 3 1 O X A8 21 1100 -1600 200 L 40 40 3 1 O X A9 22 1100 -1500 200 L 40 40 3 1 O X A10 23 1100 -1400 200 L 40 40 3 1 O X A11 24 1100 -1300 200 L 40 40 3 1 O X A12 25 1100 -1200 200 L 40 40 3 1 O X A13 26 1100 -1100 200 L 40 40 3 1 O X A14 27 1100 -1000 200 L 40 40 3 1 O X A15 28 1100 -900 200 L 40 40 3 1 O X A16 29 1100 -800 200 L 40 40 3 1 O X A17 30 1100 -700 200 L 40 40 3 1 O X A18/TOUT 31 1100 -600 200 L 40 40 3 1 O X CKA0//DREQ0 47 -200 -3300 200 R 40 40 3 1 B I X CKA1//TEND0 50 -200 -3200 200 R 40 40 3 1 B I X D0 34 1100 -3300 200 L 40 40 3 1 B X D1 35 1100 -3200 200 L 40 40 3 1 B X D2 36 1100 -3100 200 L 40 40 3 1 B X D3 37 1100 -3000 200 L 40 40 3 1 B X D4 38 1100 -2900 200 L 40 40 3 1 B X D5 39 1100 -2800 200 L 40 40 3 1 B X D6 40 1100 -2700 200 L 40 40 3 1 B X D7 41 1100 -2600 200 L 40 40 3 1 B X E 60 -200 -1200 200 R 40 40 3 1 O X EXTAL 3 -200 -1500 200 R 40 40 3 1 I C X PHI 64 -200 -1100 200 R 40 40 3 1 O X ST 12 -200 -100 200 R 40 40 3 1 O X XTAL 2 -200 -1400 200 R 40 40 3 1 I C # Gate Name: _UARTS # Symbol Name: UART P 2 4 0 0 0 0 0 -1300 P 2 4 0 0 600 -1300 0 -1300 P 2 4 0 0 600 -1300 600 0 P 2 4 0 0 0 0 600 0 X /CTS0 43 800 -300 200 L 40 40 4 1 I I X /DCD0 44 800 -100 200 L 40 40 4 1 I I X /RTS0 42 800 -200 200 L 40 40 4 1 O I X CKS 53 800 -1000 200 L 40 40 4 1 O X RXA0 46 800 -400 200 L 40 40 4 1 I X RXA1 49 800 -700 200 L 40 40 4 1 I X RXS/CTS1 52 800 -1200 200 L 40 40 4 1 I X TXA0 45 800 -500 200 L 40 40 4 1 O X TXA1 48 800 -800 200 L 40 40 4 1 O X TXS 51 800 -1100 200 L 40 40 4 1 O ENDDRAW ENDDEF # # Dev Name: Z8001P # Package Name: DIL48 # Dev Tech: '' # Dev Prefix: U # Gate count = 3 # DEF Z8001P U 0 40 Y Y 3 L N # Gate Name: >NAME # Symbol Name: Z8001 F0 "U" 0 150 50 H V L B F1 "Z8001P" 0 50 50 H V L B F2 "oldchips-DIL48" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 0 -3300 P 2 1 0 0 0 -3300 900 -3300 P 2 1 0 0 900 -3300 900 0 P 2 1 0 0 900 0 0 0 X /AS 34 1100 -600 200 L 40 40 1 1 O I X /BUSACK 29 -200 -1300 200 R 40 40 1 1 O I X /BUSREQ 27 -200 -1200 200 R 40 40 1 1 I I X /DS 19 1100 -700 200 L 40 40 1 1 O I X /MI 8 -200 -900 200 R 40 40 1 1 I I X /MO 17 -200 -1000 200 R 40 40 1 1 O I X /MREQ 18 1100 -100 200 L 40 40 1 1 O I X /NMI 15 -200 -1500 200 R 40 40 1 1 I I X /NVI 13 -200 -1600 200 R 40 40 1 1 I I X /RESET 16 -200 -1800 200 R 40 40 1 1 I I X /SEGT 14 -200 -2000 200 R 40 40 1 1 I I X /STOP 7 -200 -2100 200 R 40 40 1 1 I I X /VI 12 -200 -2200 200 R 40 40 1 1 I I X /WAIT 28 -200 -2300 200 R 40 40 1 1 I I X AD0 1 1100 -1700 200 L 40 40 1 1 B X AD1 38 1100 -1800 200 L 40 40 1 1 B X AD2 39 1100 -1900 200 L 40 40 1 1 B X AD3 40 1100 -2000 200 L 40 40 1 1 B X AD4 43 1100 -2100 200 L 40 40 1 1 B X AD5 41 1100 -2200 200 L 40 40 1 1 B X AD6 44 1100 -2300 200 L 40 40 1 1 B X AD7 45 1100 -2400 200 L 40 40 1 1 B X AD8 48 1100 -2500 200 L 40 40 1 1 B X AD9 2 1100 -2600 200 L 40 40 1 1 B X AD10 3 1100 -2700 200 L 40 40 1 1 B X AD11 4 1100 -2800 200 L 40 40 1 1 B X AD12 5 1100 -2900 200 L 40 40 1 1 B X AD13 6 1100 -3000 200 L 40 40 1 1 B X AD14 10 1100 -3100 200 L 40 40 1 1 B X AD15 9 1100 -3200 200 L 40 40 1 1 B X B//W 32 1100 -400 200 L 40 40 1 1 O X CLK 35 -200 -2700 200 R 40 40 1 1 I X N//S 31 -200 -2500 200 R 40 40 1 1 O X R//W 30 1100 -300 200 L 40 40 1 1 O X SN0 26 1100 -900 200 L 40 40 1 1 O X SN1 25 1100 -1000 200 L 40 40 1 1 O X SN2 37 1100 -1100 200 L 40 40 1 1 O X SN3 24 1100 -1200 200 L 40 40 1 1 O X SN4 42 1100 -1300 200 L 40 40 1 1 O X SN5 46 1100 -1400 200 L 40 40 1 1 O X SN6 47 1100 -1500 200 L 40 40 1 1 O X ST0 23 -200 -2900 200 R 40 40 1 1 O X ST1 22 -200 -3000 200 R 40 40 1 1 O X ST2 21 -200 -3100 200 R 40 40 1 1 O X ST3 20 -200 -3200 200 R 40 40 1 1 O # Gate Name: NC # Symbol Name: NC X NC 33 -100 0 100 R 40 40 2 1 U # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 3 0 VCC T 1 50 -155 50 0 3 0 GND X GND 36 0 -300 200 U 40 40 3 1 W X VCC 11 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: Z8001V # Package Name: PLCC68 # Dev Tech: '' # Dev Prefix: U # Gate count = 22 # DEF Z8001V U 0 40 Y Y 22 L N # Gate Name: G$1 # Symbol Name: Z8001 F0 "U" 0 150 50 H V L B F1 "Z8001V" 0 50 50 H V L B F2 "oldchips-PLCC68" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 0 -3300 P 2 1 0 0 0 -3300 900 -3300 P 2 1 0 0 900 -3300 900 0 P 2 1 0 0 900 0 0 0 X /AS 49 1100 -600 200 L 40 40 1 1 O I X /BUSACK 39 -200 -1300 200 R 40 40 1 1 O I X /BUSREQ 37 -200 -1200 200 R 40 40 1 1 I I X /DS 29 1100 -700 200 L 40 40 1 1 O I X /MI 12 -200 -900 200 R 40 40 1 1 I I X /MO 24 -200 -1000 200 R 40 40 1 1 O I X /MREQ 25 1100 -100 200 L 40 40 1 1 O I X /NMI 22 -200 -1500 200 R 40 40 1 1 I I X /NVI 20 -200 -1600 200 R 40 40 1 1 I I X /RESET 23 -200 -1800 200 R 40 40 1 1 I I X /SEGT 21 -200 -2000 200 R 40 40 1 1 I I X /STOP 11 -200 -2100 200 R 40 40 1 1 I I X /VI 19 -200 -2200 200 R 40 40 1 1 I I X /WAIT 38 -200 -2300 200 R 40 40 1 1 I I X AD0 3 1100 -1700 200 L 40 40 1 1 B X AD1 55 1100 -1800 200 L 40 40 1 1 B X AD2 56 1100 -1900 200 L 40 40 1 1 B X AD3 57 1100 -2000 200 L 40 40 1 1 B X AD4 63 1100 -2100 200 L 40 40 1 1 B X AD5 58 1100 -2200 200 L 40 40 1 1 B X AD6 64 1100 -2300 200 L 40 40 1 1 B X AD7 65 1100 -2400 200 L 40 40 1 1 B X AD8 68 1100 -2500 200 L 40 40 1 1 B X AD9 4 1100 -2600 200 L 40 40 1 1 B X AD10 5 1100 -2700 200 L 40 40 1 1 B X AD11 6 1100 -2800 200 L 40 40 1 1 B X AD12 7 1100 -2900 200 L 40 40 1 1 B X AD13 8 1100 -3000 200 L 40 40 1 1 B X AD14 14 1100 -3100 200 L 40 40 1 1 B X AD15 13 1100 -3200 200 L 40 40 1 1 B X B//W 47 1100 -400 200 L 40 40 1 1 O X CLK 51 -200 -2700 200 R 40 40 1 1 I X N//S 46 -200 -2500 200 R 40 40 1 1 O X R//W 45 1100 -300 200 L 40 40 1 1 O X SN0 36 1100 -900 200 L 40 40 1 1 O X SN1 35 1100 -1000 200 L 40 40 1 1 O X SN2 54 1100 -1100 200 L 40 40 1 1 O X SN3 34 1100 -1200 200 L 40 40 1 1 O X SN4 59 1100 -1300 200 L 40 40 1 1 O X SN5 66 1100 -1400 200 L 40 40 1 1 O X SN6 67 1100 -1500 200 L 40 40 1 1 O X ST0 33 -200 -2900 200 R 40 40 1 1 O X ST1 32 -200 -3000 200 R 40 40 1 1 O X ST2 31 -200 -3100 200 R 40 40 1 1 O X ST3 30 -200 -3200 200 R 40 40 1 1 O # Gate Name: NC1 # Symbol Name: NC X NC 9 -100 0 100 R 40 40 2 1 U # Gate Name: NC2 # Symbol Name: NC X NC 10 -100 0 100 R 40 40 3 1 U # Gate Name: NC3 # Symbol Name: NC X NC 16 -100 0 100 R 40 40 4 1 U # Gate Name: NC4 # Symbol Name: NC X NC 17 -100 0 100 R 40 40 5 1 U # Gate Name: NC5 # Symbol Name: NC X NC 18 -100 0 100 R 40 40 6 1 U # Gate Name: NC6 # Symbol Name: NC X NC 26 -100 0 100 R 40 40 7 1 U # Gate Name: NC7 # Symbol Name: NC X NC 27 -100 0 100 R 40 40 8 1 U # Gate Name: NC8 # Symbol Name: NC X NC 28 -100 0 100 R 40 40 9 1 U # Gate Name: NC9 # Symbol Name: NC X NC 40 -100 0 100 R 40 40 10 1 U # Gate Name: NC10 # Symbol Name: NC X NC 41 -100 0 100 R 40 40 11 1 U # Gate Name: NC11 # Symbol Name: NC X NC 42 -100 0 100 R 40 40 12 1 U # Gate Name: NC12 # Symbol Name: NC X NC 43 -100 0 100 R 40 40 13 1 U # Gate Name: NC13 # Symbol Name: NC X NC 44 -100 0 100 R 40 40 14 1 U # Gate Name: NC14 # Symbol Name: NC X NC 50 -100 0 100 R 40 40 15 1 U # Gate Name: NC15 # Symbol Name: NC X NC 52 -100 0 100 R 40 40 16 1 U # Gate Name: NC16 # Symbol Name: NC X NC 60 -100 0 100 R 40 40 17 1 U # Gate Name: NC17 # Symbol Name: NC X NC 61 -100 0 100 R 40 40 18 1 U # Gate Name: NC18 # Symbol Name: NC X NC 62 -100 0 100 R 40 40 19 1 U # Gate Name: P1 # Symbol Name: PWRN T 1 50 180 50 0 20 0 VCC T 1 50 -155 50 0 20 0 GND X GND 1 0 -300 200 U 40 40 20 1 W X VCC 2 0 300 200 D 40 40 20 1 W # Gate Name: P2 # Symbol Name: PWRN T 1 50 180 50 0 21 0 VCC T 1 50 -155 50 0 21 0 GND X GND 53 0 -300 200 U 40 40 21 1 W X VCC 15 0 300 200 D 40 40 21 1 W # Gate Name: RESERVED # Symbol Name: NU X IC-NU 48 -100 0 100 R 40 40 22 1 U ENDDRAW ENDDEF # # Dev Name: Z8002 # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 3 # DEF Z8002 U 0 40 Y Y 3 L N # Gate Name: >NAME # Symbol Name: Z8002 F0 "U" 0 150 50 H V L B F1 "Z8002" 0 50 50 H V L B F2 "oldchips-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 0 -2500 P 2 1 0 0 0 -2500 900 -2500 P 2 1 0 0 900 -2500 900 0 P 2 1 0 0 900 0 0 0 X /AS 29 1100 -600 200 L 40 40 1 1 O I X /BUSACK 24 -200 -500 200 R 40 40 1 1 O I X /BUSREQ 22 -200 -400 200 R 40 40 1 1 I I X /DS 17 1100 -700 200 L 40 40 1 1 O I X /MI 7 -200 -100 200 R 40 40 1 1 I I X /MO 15 -200 -200 200 R 40 40 1 1 O I X /MREQ 16 1100 -100 200 L 40 40 1 1 O I X /NMI 13 -200 -700 200 R 40 40 1 1 I I X /NVI 12 -200 -800 200 R 40 40 1 1 I I X /RESET 14 -200 -1000 200 R 40 40 1 1 I I X /STOP 6 -200 -1300 200 R 40 40 1 1 I I X /VI 11 -200 -1400 200 R 40 40 1 1 I I X /WAIT 23 -200 -1500 200 R 40 40 1 1 I I X AD0 40 1100 -900 200 L 40 40 1 1 B X AD1 32 1100 -1000 200 L 40 40 1 1 B X AD2 33 1100 -1100 200 L 40 40 1 1 B X AD3 34 1100 -1200 200 L 40 40 1 1 B X AD4 36 1100 -1300 200 L 40 40 1 1 B X AD5 35 1100 -1400 200 L 40 40 1 1 B X AD6 37 1100 -1500 200 L 40 40 1 1 B X AD7 38 1100 -1600 200 L 40 40 1 1 B X AD8 39 1100 -1700 200 L 40 40 1 1 B X AD9 1 1100 -1800 200 L 40 40 1 1 B X AD10 2 1100 -1900 200 L 40 40 1 1 B X AD11 3 1100 -2000 200 L 40 40 1 1 B X AD12 4 1100 -2100 200 L 40 40 1 1 B X AD13 5 1100 -2200 200 L 40 40 1 1 B X AD14 9 1100 -2300 200 L 40 40 1 1 B X AD15 8 1100 -2400 200 L 40 40 1 1 B X B//W 27 1100 -400 200 L 40 40 1 1 O X CLK 30 -200 -1900 200 R 40 40 1 1 I X N//S 26 -200 -1700 200 R 40 40 1 1 O X R//W 25 1100 -300 200 L 40 40 1 1 O X ST0 21 -200 -2100 200 R 40 40 1 1 O X ST1 20 -200 -2200 200 R 40 40 1 1 O X ST2 19 -200 -2300 200 R 40 40 1 1 O X ST3 18 -200 -2400 200 R 40 40 1 1 O # Gate Name: NC # Symbol Name: NC X NC 28 -100 0 100 R 40 40 2 1 U # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 3 0 VCC T 1 50 -155 50 0 3 0 GND X GND 31 0 -300 200 U 40 40 3 1 W X VCC 10 0 300 200 D 40 40 3 1 W ENDDRAW ENDDEF # # Dev Name: Z8002V # Package Name: PLCC44 # Dev Tech: '' # Dev Prefix: U # Gate count = 7 # DEF Z8002V U 0 40 Y Y 7 L N # Gate Name: >NAME # Symbol Name: Z8002 F0 "U" 0 150 50 H V L B F1 "Z8002V" 0 50 50 H V L B F2 "oldchips-PLCC44" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 0 -2500 P 2 1 0 0 0 -2500 900 -2500 P 2 1 0 0 900 -2500 900 0 P 2 1 0 0 900 0 0 0 X /AS 33 1100 -600 200 L 40 40 1 1 O I X /BUSACK 28 -200 -500 200 R 40 40 1 1 O I X /BUSREQ 26 -200 -400 200 R 40 40 1 1 I I X /DS 19 1100 -700 200 L 40 40 1 1 O I X /MI 8 -200 -100 200 R 40 40 1 1 I I X /MO 17 -200 -200 200 R 40 40 1 1 O I X /MREQ 18 1100 -100 200 L 40 40 1 1 O I X /NMI 15 -200 -700 200 R 40 40 1 1 I I X /NVI 14 -200 -800 200 R 40 40 1 1 I I X /RESET 16 -200 -1000 200 R 40 40 1 1 I I X /STOP 7 -200 -1300 200 R 40 40 1 1 I I X /VI 13 -200 -1400 200 R 40 40 1 1 I I X /WAIT 27 -200 -1500 200 R 40 40 1 1 I I X AD0 44 1100 -900 200 L 40 40 1 1 B X AD1 36 1100 -1000 200 L 40 40 1 1 B X AD2 37 1100 -1100 200 L 40 40 1 1 B X AD3 38 1100 -1200 200 L 40 40 1 1 B X AD4 40 1100 -1300 200 L 40 40 1 1 B X AD5 39 1100 -1400 200 L 40 40 1 1 B X AD6 41 1100 -1500 200 L 40 40 1 1 B X AD7 42 1100 -1600 200 L 40 40 1 1 B X AD8 43 1100 -1700 200 L 40 40 1 1 B X AD9 1 1100 -1800 200 L 40 40 1 1 B X AD10 2 1100 -1900 200 L 40 40 1 1 B X AD11 3 1100 -2000 200 L 40 40 1 1 B X AD12 4 1100 -2100 200 L 40 40 1 1 B X AD13 5 1100 -2200 200 L 40 40 1 1 B X AD14 10 1100 -2300 200 L 40 40 1 1 B X AD15 9 1100 -2400 200 L 40 40 1 1 B X B//W 31 1100 -400 200 L 40 40 1 1 O X CLK 34 -200 -1900 200 R 40 40 1 1 I X N//S 30 -200 -1700 200 R 40 40 1 1 O X R//W 29 1100 -300 200 L 40 40 1 1 O X ST0 23 -200 -2100 200 R 40 40 1 1 O X ST1 22 -200 -2200 200 R 40 40 1 1 O X ST2 21 -200 -2300 200 R 40 40 1 1 O X ST3 20 -200 -2400 200 R 40 40 1 1 O # Gate Name: NC1 # Symbol Name: NC X NC 6 -100 0 100 R 40 40 2 1 U # Gate Name: NC2 # Symbol Name: NC X NC 12 -100 0 100 R 40 40 3 1 U # Gate Name: NC3 # Symbol Name: NC X NC 24 -100 0 100 R 40 40 4 1 U # Gate Name: NC4 # Symbol Name: NC X NC 25 -100 0 100 R 40 40 5 1 U # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 6 0 VCC T 1 50 -155 50 0 6 0 GND X GND 35 0 -300 200 U 40 40 6 1 W X VCC 11 0 300 200 D 40 40 6 1 W # Gate Name: RESERVED # Symbol Name: NU X IC-NU 32 -100 0 100 R 40 40 7 1 U ENDDRAW ENDDEF # # Dev Name: Z8581 # Package Name: DIL18 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF Z8581 U 0 40 Y Y 2 L N # Gate Name: >NAME # Symbol Name: Z8581 F0 "U" 0 150 50 H V L B F1 "Z8581" 0 50 50 H V L B F2 "oldchips-DIL18" 0 150 50 H I C C DRAW P 2 1 0 0 0 0 0 -1200 P 2 1 0 0 0 -1200 800 -1200 P 2 1 0 0 800 -1200 800 0 P 2 1 0 0 800 0 0 0 X /ADDR1 6 -200 -100 200 R 40 40 1 1 I I X /ADDR2 7 -200 -200 200 R 40 40 1 1 I I X /INH 4 -200 -400 200 R 40 40 1 1 I I X /RSTI 18 -200 -600 200 R 40 40 1 1 I I X /RTSO 17 -200 -700 200 R 40 40 1 1 O I X /STRH 3 -200 -300 200 R 40 40 1 1 I I X /STRT 8 -200 -900 200 R 40 40 1 1 I I X C0 9 -200 -1000 200 R 40 40 1 1 O X C1 10 -200 -1100 200 R 40 40 1 1 O X OSC 16 1000 -400 200 L 40 40 1 1 O X TCLK 13 1000 -1100 200 L 40 40 1 1 O X XTL1A 1 1000 -100 200 L 40 40 1 1 I X XTL1B 2 1000 -200 200 L 40 40 1 1 O X XTL2A 12 1000 -800 200 L 40 40 1 1 I X XTL2B 11 1000 -900 200 L 40 40 1 1 O X ZCLK 15 1000 -600 200 L 40 40 1 1 O # Gate Name: P # Symbol Name: PWRN T 1 50 180 50 0 2 0 VCC T 1 50 -155 50 0 2 0 GND X GND 14 0 -300 200 U 40 40 2 1 W X VCC 5 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF #End Library