EESchema-LIBRARY Version 2.3 29/04/2008-12:23:20 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 28 # # Dev Name: PIC16F870P # Package Name: DIL28-3 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F870P U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F870 F0 "U" 0 0 50 H V R T F1 "PIC16F870P" -700 1100 50 H V R T F2 "pic16f87x-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -900 P 2 1 0 0 700 -900 -700 -900 P 2 1 0 0 -700 -900 -700 1000 T 0 -875 1165 70 0 1 0 >PART T 0 115 930 60 0 1 0 VDD T 0 565 930 60 0 1 0 VSS X MCLR*/VPP/THV 1 -900 800 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -700 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -800 200 R 40 40 1 1 O X RA0/AN0 2 -900 600 200 R 40 40 1 1 B X RA1/AN1 3 -900 500 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 400 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 300 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 200 200 R 40 40 1 1 B X RA5/AN4 7 -900 100 200 R 40 40 1 1 B X RB0/INT 21 900 800 200 L 40 40 1 1 B X RB1 22 900 700 200 L 40 40 1 1 B X RB2 23 900 600 200 L 40 40 1 1 B X RB3/PGM 24 900 500 200 L 40 40 1 1 B X RB4 25 900 400 200 L 40 40 1 1 B X RB5 26 900 300 200 L 40 40 1 1 B X RB6/PGC 27 900 200 200 L 40 40 1 1 B X RB7/PGD 28 900 100 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -100 200 L 40 40 1 1 B X RC1/T1OSI 12 900 -200 200 L 40 40 1 1 B X RC2/CCP1 13 900 -300 200 L 40 40 1 1 B X RC3 14 900 -400 200 L 40 40 1 1 B X RC4 15 900 -500 200 L 40 40 1 1 B X RC5 16 900 -600 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -700 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -800 200 L 40 40 1 1 B X VDD 20 100 1200 200 D 40 40 1 1 W X VSS@1 8 600 1200 200 D 40 40 1 1 W X VSS@2 19 500 1200 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F870SO # Package Name: S0-28 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F870SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F870 F0 "U" 0 0 50 H V R T F1 "PIC16F870SO" -700 1100 50 H V R T F2 "pic16f87x-S0-28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -900 P 2 1 0 0 700 -900 -700 -900 P 2 1 0 0 -700 -900 -700 1000 T 0 -875 1165 70 0 1 0 >PART T 0 115 930 60 0 1 0 VDD T 0 565 930 60 0 1 0 VSS X MCLR*/VPP/THV 1 -900 800 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -700 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -800 200 R 40 40 1 1 O X RA0/AN0 2 -900 600 200 R 40 40 1 1 B X RA1/AN1 3 -900 500 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 400 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 300 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 200 200 R 40 40 1 1 B X RA5/AN4 7 -900 100 200 R 40 40 1 1 B X RB0/INT 21 900 800 200 L 40 40 1 1 B X RB1 22 900 700 200 L 40 40 1 1 B X RB2 23 900 600 200 L 40 40 1 1 B X RB3/PGM 24 900 500 200 L 40 40 1 1 B X RB4 25 900 400 200 L 40 40 1 1 B X RB5 26 900 300 200 L 40 40 1 1 B X RB6/PGC 27 900 200 200 L 40 40 1 1 B X RB7/PGD 28 900 100 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -100 200 L 40 40 1 1 B X RC1/T1OSI 12 900 -200 200 L 40 40 1 1 B X RC2/CCP1 13 900 -300 200 L 40 40 1 1 B X RC3 14 900 -400 200 L 40 40 1 1 B X RC4 15 900 -500 200 L 40 40 1 1 B X RC5 16 900 -600 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -700 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -800 200 L 40 40 1 1 B X VDD 20 100 1200 200 D 40 40 1 1 W X VSS@1 8 600 1200 200 D 40 40 1 1 W X VSS@2 19 500 1200 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F870SS # Package Name: SSOP28 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F870SS U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F870 F0 "U" 0 0 50 H V R T F1 "PIC16F870SS" -700 1100 50 H V R T F2 "pic16f87x-SSOP28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -900 P 2 1 0 0 700 -900 -700 -900 P 2 1 0 0 -700 -900 -700 1000 T 0 -875 1165 70 0 1 0 >PART T 0 115 930 60 0 1 0 VDD T 0 565 930 60 0 1 0 VSS X MCLR*/VPP/THV 1 -900 800 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -700 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -800 200 R 40 40 1 1 O X RA0/AN0 2 -900 600 200 R 40 40 1 1 B X RA1/AN1 3 -900 500 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 400 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 300 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 200 200 R 40 40 1 1 B X RA5/AN4 7 -900 100 200 R 40 40 1 1 B X RB0/INT 21 900 800 200 L 40 40 1 1 B X RB1 22 900 700 200 L 40 40 1 1 B X RB2 23 900 600 200 L 40 40 1 1 B X RB3/PGM 24 900 500 200 L 40 40 1 1 B X RB4 25 900 400 200 L 40 40 1 1 B X RB5 26 900 300 200 L 40 40 1 1 B X RB6/PGC 27 900 200 200 L 40 40 1 1 B X RB7/PGD 28 900 100 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -100 200 L 40 40 1 1 B X RC1/T1OSI 12 900 -200 200 L 40 40 1 1 B X RC2/CCP1 13 900 -300 200 L 40 40 1 1 B X RC3 14 900 -400 200 L 40 40 1 1 B X RC4 15 900 -500 200 L 40 40 1 1 B X RC5 16 900 -600 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -700 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -800 200 L 40 40 1 1 B X VDD 20 100 1200 200 D 40 40 1 1 W X VSS@1 8 600 1200 200 D 40 40 1 1 W X VSS@2 19 500 1200 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F871L # Package Name: PLCC-44 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F871L U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F871 F0 "U" 0 0 50 H V R T F1 "PIC16F871L" -900 1200 50 H V R T F2 "pic16f87x-PLCC-44" 0 150 50 H I C C DRAW P 2 1 0 0 -900 1100 900 1100 P 2 1 0 0 900 1100 900 -1200 P 2 1 0 0 900 -1200 -900 -1200 P 2 1 0 0 -900 -1200 -900 1100 T 0 -1075 1265 70 0 1 0 >PART T 0 265 1030 60 0 1 0 VDD T 0 765 1030 60 0 1 0 VSS X MCLR*/VPP/THV 2 -1100 900 200 R 40 40 1 1 I X OSC1/CLKIN 14 1100 -1000 200 L 40 40 1 1 I X OSC2/CLKOUT 15 1100 -1100 200 L 40 40 1 1 O X RA0/AN0 3 -1100 700 200 R 40 40 1 1 B X RA1/AN1 4 -1100 600 200 R 40 40 1 1 B X RA2/AN2/VREF- 5 -1100 500 200 R 40 40 1 1 B X RA3/AN3/VREF+ 6 -1100 400 200 R 40 40 1 1 B X RA4/T0CKI 7 -1100 300 200 R 40 40 1 1 B X RA5/AN4 8 -1100 200 200 R 40 40 1 1 B X RB0/INT 36 1100 900 200 L 40 40 1 1 B X RB1 37 1100 800 200 L 40 40 1 1 B X RB2 38 1100 700 200 L 40 40 1 1 B X RB3/PGM 39 1100 600 200 L 40 40 1 1 B X RB4 41 1100 500 200 L 40 40 1 1 B X RB5 42 1100 400 200 L 40 40 1 1 B X RB6/PGC 43 1100 300 200 L 40 40 1 1 B X RB7/PGD 44 1100 200 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 16 1100 0 200 L 40 40 1 1 B X RC1/T1OSI 18 1100 -100 200 L 40 40 1 1 B X RC2/CCP1 19 1100 -200 200 L 40 40 1 1 B X RC3 20 1100 -300 200 L 40 40 1 1 B X RC4 25 1100 -400 200 L 40 40 1 1 B X RC5 26 1100 -500 200 L 40 40 1 1 B X RC6/TX/CK 27 1100 -600 200 L 40 40 1 1 B X RC7/RX/DT 29 1100 -700 200 L 40 40 1 1 B X RD0/PSP0 21 -1100 -400 200 R 40 40 1 1 B X RD1/PSP1 22 -1100 -500 200 R 40 40 1 1 B X RD2/PSP2 23 -1100 -600 200 R 40 40 1 1 B X RD3/PSP3 24 -1100 -700 200 R 40 40 1 1 B X RD4/PSP4 30 -1100 -800 200 R 40 40 1 1 B X RD5/PSP5 31 -1100 -900 200 R 40 40 1 1 B X RD6/PSP6 32 -1100 -1000 200 R 40 40 1 1 B X RD7/PSP7 33 -1100 -1100 200 R 40 40 1 1 B X RE0/RD*/AN5 9 -1100 0 200 R 40 40 1 1 B X RE1/WR*/AN6 10 -1100 -100 200 R 40 40 1 1 B X RE2/CS*/AN7 11 -1100 -200 200 R 40 40 1 1 B X VDD@1 12 300 1300 200 D 40 40 1 1 W X VDD@2 35 200 1300 200 D 40 40 1 1 W X VSS@1 13 800 1300 200 D 40 40 1 1 W X VSS@2 34 700 1300 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F871P # Package Name: DIL40 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F871P U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F871 F0 "U" 0 0 50 H V R T F1 "PIC16F871P" -900 1200 50 H V R T F2 "pic16f87x-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -900 1100 900 1100 P 2 1 0 0 900 1100 900 -1200 P 2 1 0 0 900 -1200 -900 -1200 P 2 1 0 0 -900 -1200 -900 1100 T 0 -1075 1265 70 0 1 0 >PART T 0 265 1030 60 0 1 0 VDD T 0 765 1030 60 0 1 0 VSS X MCLR*/VPP/THV 1 -1100 900 200 R 40 40 1 1 I X OSC1/CLKIN 13 1100 -1000 200 L 40 40 1 1 I X OSC2/CLKOUT 14 1100 -1100 200 L 40 40 1 1 O X RA0/AN0 2 -1100 700 200 R 40 40 1 1 B X RA1/AN1 3 -1100 600 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -1100 500 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -1100 400 200 R 40 40 1 1 B X RA4/T0CKI 6 -1100 300 200 R 40 40 1 1 B X RA5/AN4 7 -1100 200 200 R 40 40 1 1 B X RB0/INT 33 1100 900 200 L 40 40 1 1 B X RB1 34 1100 800 200 L 40 40 1 1 B X RB2 35 1100 700 200 L 40 40 1 1 B X RB3/PGM 36 1100 600 200 L 40 40 1 1 B X RB4 37 1100 500 200 L 40 40 1 1 B X RB5 38 1100 400 200 L 40 40 1 1 B X RB6/PGC 39 1100 300 200 L 40 40 1 1 B X RB7/PGD 40 1100 200 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 15 1100 0 200 L 40 40 1 1 B X RC1/T1OSI 16 1100 -100 200 L 40 40 1 1 B X RC2/CCP1 17 1100 -200 200 L 40 40 1 1 B X RC3 18 1100 -300 200 L 40 40 1 1 B X RC4 23 1100 -400 200 L 40 40 1 1 B X RC5 24 1100 -500 200 L 40 40 1 1 B X RC6/TX/CK 25 1100 -600 200 L 40 40 1 1 B X RC7/RX/DT 26 1100 -700 200 L 40 40 1 1 B X RD0/PSP0 19 -1100 -400 200 R 40 40 1 1 B X RD1/PSP1 20 -1100 -500 200 R 40 40 1 1 B X RD2/PSP2 21 -1100 -600 200 R 40 40 1 1 B X RD3/PSP3 22 -1100 -700 200 R 40 40 1 1 B X RD4/PSP4 27 -1100 -800 200 R 40 40 1 1 B X RD5/PSP5 28 -1100 -900 200 R 40 40 1 1 B X RD6/PSP6 29 -1100 -1000 200 R 40 40 1 1 B X RD7/PSP7 30 -1100 -1100 200 R 40 40 1 1 B X RE0/RD*/AN5 8 -1100 0 200 R 40 40 1 1 B X RE1/WR*/AN6 9 -1100 -100 200 R 40 40 1 1 B X RE2/CS*/AN7 10 -1100 -200 200 R 40 40 1 1 B X VDD@1 11 300 1300 200 D 40 40 1 1 W X VDD@2 32 200 1300 200 D 40 40 1 1 W X VSS@1 12 800 1300 200 D 40 40 1 1 W X VSS@2 31 700 1300 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F871T # Package Name: TQFP44 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F871T U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F871 F0 "U" 0 0 50 H V R T F1 "PIC16F871T" -900 1200 50 H V R T F2 "pic16f87x-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -900 1100 900 1100 P 2 1 0 0 900 1100 900 -1200 P 2 1 0 0 900 -1200 -900 -1200 P 2 1 0 0 -900 -1200 -900 1100 T 0 -1075 1265 70 0 1 0 >PART T 0 265 1030 60 0 1 0 VDD T 0 765 1030 60 0 1 0 VSS X MCLR*/VPP/THV 18 -1100 900 200 R 40 40 1 1 I X OSC1/CLKIN 30 1100 -1000 200 L 40 40 1 1 I X OSC2/CLKOUT 31 1100 -1100 200 L 40 40 1 1 O X RA0/AN0 19 -1100 700 200 R 40 40 1 1 B X RA1/AN1 20 -1100 600 200 R 40 40 1 1 B X RA2/AN2/VREF- 21 -1100 500 200 R 40 40 1 1 B X RA3/AN3/VREF+ 22 -1100 400 200 R 40 40 1 1 B X RA4/T0CKI 23 -1100 300 200 R 40 40 1 1 B X RA5/AN4 24 -1100 200 200 R 40 40 1 1 B X RB0/INT 8 1100 900 200 L 40 40 1 1 B X RB1 9 1100 800 200 L 40 40 1 1 B X RB2 10 1100 700 200 L 40 40 1 1 B X RB3/PGM 11 1100 600 200 L 40 40 1 1 B X RB4 14 1100 500 200 L 40 40 1 1 B X RB5 15 1100 400 200 L 40 40 1 1 B X RB6/PGC 16 1100 300 200 L 40 40 1 1 B X RB7/PGD 17 1100 200 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 32 1100 0 200 L 40 40 1 1 B X RC1/T1OSI 35 1100 -100 200 L 40 40 1 1 B X RC2/CCP1 36 1100 -200 200 L 40 40 1 1 B X RC3 37 1100 -300 200 L 40 40 1 1 B X RC4 42 1100 -400 200 L 40 40 1 1 B X RC5 43 1100 -500 200 L 40 40 1 1 B X RC6/TX/CK 44 1100 -600 200 L 40 40 1 1 B X RC7/RX/DT 1 1100 -700 200 L 40 40 1 1 B X RD0/PSP0 38 -1100 -400 200 R 40 40 1 1 B X RD1/PSP1 39 -1100 -500 200 R 40 40 1 1 B X RD2/PSP2 40 -1100 -600 200 R 40 40 1 1 B X RD3/PSP3 41 -1100 -700 200 R 40 40 1 1 B X RD4/PSP4 2 -1100 -800 200 R 40 40 1 1 B X RD5/PSP5 3 -1100 -900 200 R 40 40 1 1 B X RD6/PSP6 4 -1100 -1000 200 R 40 40 1 1 B X RD7/PSP7 5 -1100 -1100 200 R 40 40 1 1 B X RE0/RD*/AN5 25 -1100 0 200 R 40 40 1 1 B X RE1/WR*/AN6 26 -1100 -100 200 R 40 40 1 1 B X RE2/CS*/AN7 27 -1100 -200 200 R 40 40 1 1 B X VDD@1 7 300 1300 200 D 40 40 1 1 W X VDD@2 28 200 1300 200 D 40 40 1 1 W X VSS@1 6 800 1300 200 D 40 40 1 1 W X VSS@2 29 700 1300 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F872P # Package Name: DIL28-3 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F872P U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F872 F0 "U" 0 0 50 H V R T F1 "PIC16F872P" -700 1000 50 H V R T F2 "pic16f87x-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 115 830 60 0 1 0 VDD T 0 565 830 60 0 1 0 VSS X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 O X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 600 1100 200 D 40 40 1 1 W X VSS@2 19 500 1100 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F872SO # Package Name: S0-28 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F872SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F872 F0 "U" 0 0 50 H V R T F1 "PIC16F872SO" -700 1000 50 H V R T F2 "pic16f87x-S0-28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 115 830 60 0 1 0 VDD T 0 565 830 60 0 1 0 VSS X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 O X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 600 1100 200 D 40 40 1 1 W X VSS@2 19 500 1100 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F872SS # Package Name: SSOP28 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC16F872SS U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F872 F0 "U" 0 0 50 H V R T F1 "PIC16F872SS" -700 1000 50 H V R T F2 "pic16f87x-SSOP28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 115 830 60 0 1 0 VDD T 0 565 830 60 0 1 0 VSS X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 O X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 600 1100 200 D 40 40 1 1 W X VSS@2 19 500 1100 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16F873SO # Package Name: S0-28 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F873SO U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F873 F0 "U" 0 0 50 H V R T F1 "PIC16F873SO" -700 1000 50 H V R T F2 "pic16f87x-S0-28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 565 830 60 0 1 0 VSS T 0 115 830 60 0 1 0 VDD X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 B X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 B X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 B X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 500 1100 200 D 40 40 1 1 w X VSS@2 19 600 1100 200 D 40 40 1 1 w ENDDRAW ENDDEF # # Dev Name: PIC16F873SP # Package Name: DIL28-3 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F873SP U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F873 F0 "U" 0 0 50 H V R T F1 "PIC16F873SP" -700 1000 50 H V R T F2 "pic16f87x-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 565 830 60 0 1 0 VSS T 0 115 830 60 0 1 0 VDD X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 B X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 B X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 B X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 500 1100 200 D 40 40 1 1 w X VSS@2 19 600 1100 200 D 40 40 1 1 w ENDDRAW ENDDEF # # Dev Name: PIC16F874L # Package Name: PLCC-44 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F874L U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F874 F0 "U" 0 0 50 H V R T F1 "PIC16F874L" -800 1400 50 H V R T F2 "pic16f87x-PLCC-44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1300 900 1300 P 2 1 0 0 900 1300 900 -1000 P 2 1 0 0 900 -1000 -800 -1000 P 2 1 0 0 -800 -1000 -800 1300 T 0 -975 1465 70 0 1 0 >PART T 0 259 1228 56 0 1 0 VDD T 0 759 1228 56 0 1 0 VSS X MCLR*/VPP 2 -1000 1100 200 R 40 40 1 1 I X OSC1/CLKIN 14 1100 -800 200 L 40 40 1 1 I X OSC2/CLKOUT 15 1100 -900 200 L 40 40 1 1 O X RA0/AN0 3 -1000 900 200 R 40 40 1 1 B X RA1/AN1 4 -1000 800 200 R 40 40 1 1 B X RA2/AN2/VREF- 5 -1000 700 200 R 40 40 1 1 B X RA3/AN3/VREF+ 6 -1000 600 200 R 40 40 1 1 B X RA4/T0CKI 7 -1000 500 200 R 40 40 1 1 B X RA5/AN4/SS* 8 -1000 400 200 R 40 40 1 1 B X RB0/INT 36 1100 1100 200 L 40 40 1 1 B X RB1 37 1100 1000 200 L 40 40 1 1 B X RB2 38 1100 900 200 L 40 40 1 1 B X RB3/PGM 39 1100 800 200 L 40 40 1 1 B X RB4 41 1100 700 200 L 40 40 1 1 B X RB5 42 1100 600 200 L 40 40 1 1 B X RB6/PGC 43 1100 500 200 L 40 40 1 1 B X RB7/PGD 44 1100 400 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 16 1100 200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 18 1100 100 200 L 40 40 1 1 B X RC2/CCP1 19 1100 0 200 L 40 40 1 1 B X RC3/SCK/SCL 20 1100 -100 200 L 40 40 1 1 B X RC4/SDI/SDA 25 1100 -200 200 L 40 40 1 1 B X RC5/SDO 26 1100 -300 200 L 40 40 1 1 B X RC6/TX/CK 27 1100 -400 200 L 40 40 1 1 B X RC7/RX/DT 29 1100 -500 200 L 40 40 1 1 B X RD0/PSP0 21 -1000 -200 200 R 40 40 1 1 B X RD1/PSP1 22 -1000 -300 200 R 40 40 1 1 B X RD2/PSP2 23 -1000 -400 200 R 40 40 1 1 B X RD3/PSP3 24 -1000 -500 200 R 40 40 1 1 B X RD4/PSP4 30 -1000 -600 200 R 40 40 1 1 B X RD5/PSP5 31 -1000 -700 200 R 40 40 1 1 B X RD6/PSP6 32 -1000 -800 200 R 40 40 1 1 B X RD7/PSP7 33 -1000 -900 200 R 40 40 1 1 B X RE0/RD*/AN5 9 -1000 200 200 R 40 40 1 1 B X RE1/WR*/AN6 10 -1000 100 200 R 40 40 1 1 B X RE2/CS*/AN7 11 -1000 0 200 R 40 40 1 1 B X VDD@1 12 200 1500 200 D 40 40 1 1 B X VDD@2 35 300 1500 200 D 40 40 1 1 B X VSS@1 13 700 1500 200 D 40 40 1 1 B X VSS@2 34 800 1500 200 D 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC16F874P # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F874P U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F874 F0 "U" 0 0 50 H V R T F1 "PIC16F874P" -800 1400 50 H V R T F2 "pic16f87x-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1300 900 1300 P 2 1 0 0 900 1300 900 -1000 P 2 1 0 0 900 -1000 -800 -1000 P 2 1 0 0 -800 -1000 -800 1300 T 0 -975 1465 70 0 1 0 >PART T 0 259 1228 56 0 1 0 VDD T 0 759 1228 56 0 1 0 VSS X MCLR*/VPP 1 -1000 1100 200 R 40 40 1 1 I X OSC1/CLKIN 13 1100 -800 200 L 40 40 1 1 I X OSC2/CLKOUT 14 1100 -900 200 L 40 40 1 1 O X RA0/AN0 2 -1000 900 200 R 40 40 1 1 B X RA1/AN1 3 -1000 800 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -1000 700 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -1000 600 200 R 40 40 1 1 B X RA4/T0CKI 6 -1000 500 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -1000 400 200 R 40 40 1 1 B X RB0/INT 33 1100 1100 200 L 40 40 1 1 B X RB1 34 1100 1000 200 L 40 40 1 1 B X RB2 35 1100 900 200 L 40 40 1 1 B X RB3/PGM 36 1100 800 200 L 40 40 1 1 B X RB4 37 1100 700 200 L 40 40 1 1 B X RB5 38 1100 600 200 L 40 40 1 1 B X RB6/PGC 39 1100 500 200 L 40 40 1 1 B X RB7/PGD 40 1100 400 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 15 1100 200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 16 1100 100 200 L 40 40 1 1 B X RC2/CCP1 17 1100 0 200 L 40 40 1 1 B X RC3/SCK/SCL 18 1100 -100 200 L 40 40 1 1 B X RC4/SDI/SDA 23 1100 -200 200 L 40 40 1 1 B X RC5/SDO 24 1100 -300 200 L 40 40 1 1 B X RC6/TX/CK 25 1100 -400 200 L 40 40 1 1 B X RC7/RX/DT 26 1100 -500 200 L 40 40 1 1 B X RD0/PSP0 19 -1000 -200 200 R 40 40 1 1 B X RD1/PSP1 20 -1000 -300 200 R 40 40 1 1 B X RD2/PSP2 21 -1000 -400 200 R 40 40 1 1 B X RD3/PSP3 22 -1000 -500 200 R 40 40 1 1 B X RD4/PSP4 27 -1000 -600 200 R 40 40 1 1 B X RD5/PSP5 28 -1000 -700 200 R 40 40 1 1 B X RD6/PSP6 29 -1000 -800 200 R 40 40 1 1 B X RD7/PSP7 30 -1000 -900 200 R 40 40 1 1 B X RE0/RD*/AN5 8 -1000 200 200 R 40 40 1 1 B X RE1/WR*/AN6 9 -1000 100 200 R 40 40 1 1 B X RE2/CS*/AN7 10 -1000 0 200 R 40 40 1 1 B X VDD@1 11 200 1500 200 D 40 40 1 1 B X VDD@2 32 300 1500 200 D 40 40 1 1 B X VSS@1 12 700 1500 200 D 40 40 1 1 B X VSS@2 31 800 1500 200 D 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC16F874PT # Package Name: TQFP44 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F874PT U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F874 F0 "U" 0 0 50 H V R T F1 "PIC16F874PT" -800 1400 50 H V R T F2 "pic16f87x-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1300 900 1300 P 2 1 0 0 900 1300 900 -1000 P 2 1 0 0 900 -1000 -800 -1000 P 2 1 0 0 -800 -1000 -800 1300 T 0 -975 1465 70 0 1 0 >PART T 0 259 1228 56 0 1 0 VDD T 0 759 1228 56 0 1 0 VSS X MCLR*/VPP 18 -1000 1100 200 R 40 40 1 1 I X OSC1/CLKIN 30 1100 -800 200 L 40 40 1 1 I X OSC2/CLKOUT 31 1100 -900 200 L 40 40 1 1 O X RA0/AN0 19 -1000 900 200 R 40 40 1 1 B X RA1/AN1 20 -1000 800 200 R 40 40 1 1 B X RA2/AN2/VREF- 21 -1000 700 200 R 40 40 1 1 B X RA3/AN3/VREF+ 22 -1000 600 200 R 40 40 1 1 B X RA4/T0CKI 23 -1000 500 200 R 40 40 1 1 B X RA5/AN4/SS* 24 -1000 400 200 R 40 40 1 1 B X RB0/INT 8 1100 1100 200 L 40 40 1 1 B X RB1 9 1100 1000 200 L 40 40 1 1 B X RB2 10 1100 900 200 L 40 40 1 1 B X RB3/PGM 11 1100 800 200 L 40 40 1 1 B X RB4 14 1100 700 200 L 40 40 1 1 B X RB5 15 1100 600 200 L 40 40 1 1 B X RB6/PGC 16 1100 500 200 L 40 40 1 1 B X RB7/PGD 17 1100 400 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 32 1100 200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 35 1100 100 200 L 40 40 1 1 B X RC2/CCP1 36 1100 0 200 L 40 40 1 1 B X RC3/SCK/SCL 37 1100 -100 200 L 40 40 1 1 B X RC4/SDI/SDA 42 1100 -200 200 L 40 40 1 1 B X RC5/SDO 43 1100 -300 200 L 40 40 1 1 B X RC6/TX/CK 44 1100 -400 200 L 40 40 1 1 B X RC7/RX/DT 1 1100 -500 200 L 40 40 1 1 B X RD0/PSP0 38 -1000 -200 200 R 40 40 1 1 B X RD1/PSP1 39 -1000 -300 200 R 40 40 1 1 B X RD2/PSP2 40 -1000 -400 200 R 40 40 1 1 B X RD3/PSP3 41 -1000 -500 200 R 40 40 1 1 B X RD4/PSP4 2 -1000 -600 200 R 40 40 1 1 B X RD5/PSP5 3 -1000 -700 200 R 40 40 1 1 B X RD6/PSP6 4 -1000 -800 200 R 40 40 1 1 B X RD7/PSP7 5 -1000 -900 200 R 40 40 1 1 B X RE0/RD*/AN5 25 -1000 200 200 R 40 40 1 1 B X RE1/WR*/AN6 26 -1000 100 200 R 40 40 1 1 B X RE2/CS*/AN7 27 -1000 0 200 R 40 40 1 1 B X VDD@1 7 200 1500 200 D 40 40 1 1 B X VDD@2 28 300 1500 200 D 40 40 1 1 B X VSS@1 6 700 1500 200 D 40 40 1 1 B X VSS@2 29 800 1500 200 D 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC16F876SO # Package Name: S0-28 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F876SO U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F873 F0 "U" 0 0 50 H V R T F1 "PIC16F876SO" -700 1000 50 H V R T F2 "pic16f87x-S0-28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 565 830 60 0 1 0 VSS T 0 115 830 60 0 1 0 VDD X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 B X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 B X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 B X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 500 1100 200 D 40 40 1 1 w X VSS@2 19 600 1100 200 D 40 40 1 1 w ENDDRAW ENDDEF # # Dev Name: PIC16F876SP # Package Name: DIL28-3 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F876SP U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F873 F0 "U" 0 0 50 H V R T F1 "PIC16F876SP" -700 1000 50 H V R T F2 "pic16f87x-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 565 830 60 0 1 0 VSS T 0 115 830 60 0 1 0 VDD X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 B X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 B X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 B X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 500 1100 200 D 40 40 1 1 w X VSS@2 19 600 1100 200 D 40 40 1 1 w ENDDRAW ENDDEF # # Dev Name: PIC16F877L # Package Name: PLCC-44 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F877L U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F874 F0 "U" 0 0 50 H V R T F1 "PIC16F877L" -800 1400 50 H V R T F2 "pic16f87x-PLCC-44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1300 900 1300 P 2 1 0 0 900 1300 900 -1000 P 2 1 0 0 900 -1000 -800 -1000 P 2 1 0 0 -800 -1000 -800 1300 T 0 -975 1465 70 0 1 0 >PART T 0 259 1228 56 0 1 0 VDD T 0 759 1228 56 0 1 0 VSS X MCLR*/VPP 2 -1000 1100 200 R 40 40 1 1 I X OSC1/CLKIN 14 1100 -800 200 L 40 40 1 1 I X OSC2/CLKOUT 15 1100 -900 200 L 40 40 1 1 O X RA0/AN0 3 -1000 900 200 R 40 40 1 1 B X RA1/AN1 4 -1000 800 200 R 40 40 1 1 B X RA2/AN2/VREF- 5 -1000 700 200 R 40 40 1 1 B X RA3/AN3/VREF+ 6 -1000 600 200 R 40 40 1 1 B X RA4/T0CKI 7 -1000 500 200 R 40 40 1 1 B X RA5/AN4/SS* 8 -1000 400 200 R 40 40 1 1 B X RB0/INT 36 1100 1100 200 L 40 40 1 1 B X RB1 37 1100 1000 200 L 40 40 1 1 B X RB2 38 1100 900 200 L 40 40 1 1 B X RB3/PGM 39 1100 800 200 L 40 40 1 1 B X RB4 41 1100 700 200 L 40 40 1 1 B X RB5 42 1100 600 200 L 40 40 1 1 B X RB6/PGC 43 1100 500 200 L 40 40 1 1 B X RB7/PGD 44 1100 400 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 16 1100 200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 18 1100 100 200 L 40 40 1 1 B X RC2/CCP1 19 1100 0 200 L 40 40 1 1 B X RC3/SCK/SCL 20 1100 -100 200 L 40 40 1 1 B X RC4/SDI/SDA 25 1100 -200 200 L 40 40 1 1 B X RC5/SDO 26 1100 -300 200 L 40 40 1 1 B X RC6/TX/CK 27 1100 -400 200 L 40 40 1 1 B X RC7/RX/DT 29 1100 -500 200 L 40 40 1 1 B X RD0/PSP0 21 -1000 -200 200 R 40 40 1 1 B X RD1/PSP1 22 -1000 -300 200 R 40 40 1 1 B X RD2/PSP2 23 -1000 -400 200 R 40 40 1 1 B X RD3/PSP3 24 -1000 -500 200 R 40 40 1 1 B X RD4/PSP4 30 -1000 -600 200 R 40 40 1 1 B X RD5/PSP5 31 -1000 -700 200 R 40 40 1 1 B X RD6/PSP6 32 -1000 -800 200 R 40 40 1 1 B X RD7/PSP7 33 -1000 -900 200 R 40 40 1 1 B X RE0/RD*/AN5 9 -1000 200 200 R 40 40 1 1 B X RE1/WR*/AN6 10 -1000 100 200 R 40 40 1 1 B X RE2/CS*/AN7 11 -1000 0 200 R 40 40 1 1 B X VDD@1 12 200 1500 200 D 40 40 1 1 B X VDD@2 35 300 1500 200 D 40 40 1 1 B X VSS@1 13 700 1500 200 D 40 40 1 1 B X VSS@2 34 800 1500 200 D 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC16F877P # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F877P U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F874 F0 "U" 0 0 50 H V R T F1 "PIC16F877P" -800 1400 50 H V R T F2 "pic16f87x-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1300 900 1300 P 2 1 0 0 900 1300 900 -1000 P 2 1 0 0 900 -1000 -800 -1000 P 2 1 0 0 -800 -1000 -800 1300 T 0 -975 1465 70 0 1 0 >PART T 0 259 1228 56 0 1 0 VDD T 0 759 1228 56 0 1 0 VSS X MCLR*/VPP 1 -1000 1100 200 R 40 40 1 1 I X OSC1/CLKIN 13 1100 -800 200 L 40 40 1 1 I X OSC2/CLKOUT 14 1100 -900 200 L 40 40 1 1 O X RA0/AN0 2 -1000 900 200 R 40 40 1 1 B X RA1/AN1 3 -1000 800 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -1000 700 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -1000 600 200 R 40 40 1 1 B X RA4/T0CKI 6 -1000 500 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -1000 400 200 R 40 40 1 1 B X RB0/INT 33 1100 1100 200 L 40 40 1 1 B X RB1 34 1100 1000 200 L 40 40 1 1 B X RB2 35 1100 900 200 L 40 40 1 1 B X RB3/PGM 36 1100 800 200 L 40 40 1 1 B X RB4 37 1100 700 200 L 40 40 1 1 B X RB5 38 1100 600 200 L 40 40 1 1 B X RB6/PGC 39 1100 500 200 L 40 40 1 1 B X RB7/PGD 40 1100 400 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 15 1100 200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 16 1100 100 200 L 40 40 1 1 B X RC2/CCP1 17 1100 0 200 L 40 40 1 1 B X RC3/SCK/SCL 18 1100 -100 200 L 40 40 1 1 B X RC4/SDI/SDA 23 1100 -200 200 L 40 40 1 1 B X RC5/SDO 24 1100 -300 200 L 40 40 1 1 B X RC6/TX/CK 25 1100 -400 200 L 40 40 1 1 B X RC7/RX/DT 26 1100 -500 200 L 40 40 1 1 B X RD0/PSP0 19 -1000 -200 200 R 40 40 1 1 B X RD1/PSP1 20 -1000 -300 200 R 40 40 1 1 B X RD2/PSP2 21 -1000 -400 200 R 40 40 1 1 B X RD3/PSP3 22 -1000 -500 200 R 40 40 1 1 B X RD4/PSP4 27 -1000 -600 200 R 40 40 1 1 B X RD5/PSP5 28 -1000 -700 200 R 40 40 1 1 B X RD6/PSP6 29 -1000 -800 200 R 40 40 1 1 B X RD7/PSP7 30 -1000 -900 200 R 40 40 1 1 B X RE0/RD*/AN5 8 -1000 200 200 R 40 40 1 1 B X RE1/WR*/AN6 9 -1000 100 200 R 40 40 1 1 B X RE2/CS*/AN7 10 -1000 0 200 R 40 40 1 1 B X VDD@1 11 200 1500 200 D 40 40 1 1 B X VDD@2 32 300 1500 200 D 40 40 1 1 B X VSS@1 12 700 1500 200 D 40 40 1 1 B X VSS@2 31 800 1500 200 D 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC16F877PT # Package Name: TQFP44 # Dev Tech: '' # Dev Prefix: U # Gate count = 1 # DEF PIC16F877PT U 0 40 Y Y 1 L N # Gate Name: P1 # Symbol Name: PIC16F874 F0 "U" 0 0 50 H V R T F1 "PIC16F877PT" -800 1400 50 H V R T F2 "pic16f87x-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -800 1300 900 1300 P 2 1 0 0 900 1300 900 -1000 P 2 1 0 0 900 -1000 -800 -1000 P 2 1 0 0 -800 -1000 -800 1300 T 0 -975 1465 70 0 1 0 >PART T 0 259 1228 56 0 1 0 VDD T 0 759 1228 56 0 1 0 VSS X MCLR*/VPP 18 -1000 1100 200 R 40 40 1 1 I X OSC1/CLKIN 30 1100 -800 200 L 40 40 1 1 I X OSC2/CLKOUT 31 1100 -900 200 L 40 40 1 1 O X RA0/AN0 19 -1000 900 200 R 40 40 1 1 B X RA1/AN1 20 -1000 800 200 R 40 40 1 1 B X RA2/AN2/VREF- 21 -1000 700 200 R 40 40 1 1 B X RA3/AN3/VREF+ 22 -1000 600 200 R 40 40 1 1 B X RA4/T0CKI 23 -1000 500 200 R 40 40 1 1 B X RA5/AN4/SS* 24 -1000 400 200 R 40 40 1 1 B X RB0/INT 8 1100 1100 200 L 40 40 1 1 B X RB1 9 1100 1000 200 L 40 40 1 1 B X RB2 10 1100 900 200 L 40 40 1 1 B X RB3/PGM 11 1100 800 200 L 40 40 1 1 B X RB4 14 1100 700 200 L 40 40 1 1 B X RB5 15 1100 600 200 L 40 40 1 1 B X RB6/PGC 16 1100 500 200 L 40 40 1 1 B X RB7/PGD 17 1100 400 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 32 1100 200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 35 1100 100 200 L 40 40 1 1 B X RC2/CCP1 36 1100 0 200 L 40 40 1 1 B X RC3/SCK/SCL 37 1100 -100 200 L 40 40 1 1 B X RC4/SDI/SDA 42 1100 -200 200 L 40 40 1 1 B X RC5/SDO 43 1100 -300 200 L 40 40 1 1 B X RC6/TX/CK 44 1100 -400 200 L 40 40 1 1 B X RC7/RX/DT 1 1100 -500 200 L 40 40 1 1 B X RD0/PSP0 38 -1000 -200 200 R 40 40 1 1 B X RD1/PSP1 39 -1000 -300 200 R 40 40 1 1 B X RD2/PSP2 40 -1000 -400 200 R 40 40 1 1 B X RD3/PSP3 41 -1000 -500 200 R 40 40 1 1 B X RD4/PSP4 2 -1000 -600 200 R 40 40 1 1 B X RD5/PSP5 3 -1000 -700 200 R 40 40 1 1 B X RD6/PSP6 4 -1000 -800 200 R 40 40 1 1 B X RD7/PSP7 5 -1000 -900 200 R 40 40 1 1 B X RE0/RD*/AN5 25 -1000 200 200 R 40 40 1 1 B X RE1/WR*/AN6 26 -1000 100 200 R 40 40 1 1 B X RE2/CS*/AN7 27 -1000 0 200 R 40 40 1 1 B X VDD@1 7 200 1500 200 D 40 40 1 1 B X VDD@2 28 300 1500 200 D 40 40 1 1 B X VSS@1 6 700 1500 200 D 40 40 1 1 B X VSS@2 29 800 1500 200 D 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC16LF870P # Package Name: DIL28-3 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF870P U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F870 F0 "U" 0 0 50 H V R T F1 "PIC16LF870P" -700 1100 50 H V R T F2 "pic16f87x-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -900 P 2 1 0 0 700 -900 -700 -900 P 2 1 0 0 -700 -900 -700 1000 T 0 -875 1165 70 0 1 0 >PART T 0 115 930 60 0 1 0 VDD T 0 565 930 60 0 1 0 VSS X MCLR*/VPP/THV 1 -900 800 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -700 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -800 200 R 40 40 1 1 O X RA0/AN0 2 -900 600 200 R 40 40 1 1 B X RA1/AN1 3 -900 500 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 400 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 300 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 200 200 R 40 40 1 1 B X RA5/AN4 7 -900 100 200 R 40 40 1 1 B X RB0/INT 21 900 800 200 L 40 40 1 1 B X RB1 22 900 700 200 L 40 40 1 1 B X RB2 23 900 600 200 L 40 40 1 1 B X RB3/PGM 24 900 500 200 L 40 40 1 1 B X RB4 25 900 400 200 L 40 40 1 1 B X RB5 26 900 300 200 L 40 40 1 1 B X RB6/PGC 27 900 200 200 L 40 40 1 1 B X RB7/PGD 28 900 100 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -100 200 L 40 40 1 1 B X RC1/T1OSI 12 900 -200 200 L 40 40 1 1 B X RC2/CCP1 13 900 -300 200 L 40 40 1 1 B X RC3 14 900 -400 200 L 40 40 1 1 B X RC4 15 900 -500 200 L 40 40 1 1 B X RC5 16 900 -600 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -700 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -800 200 L 40 40 1 1 B X VDD 20 100 1200 200 D 40 40 1 1 W X VSS@1 8 600 1200 200 D 40 40 1 1 W X VSS@2 19 500 1200 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF870SO # Package Name: S0-28 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF870SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F870 F0 "U" 0 0 50 H V R T F1 "PIC16LF870SO" -700 1100 50 H V R T F2 "pic16f87x-S0-28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -900 P 2 1 0 0 700 -900 -700 -900 P 2 1 0 0 -700 -900 -700 1000 T 0 -875 1165 70 0 1 0 >PART T 0 115 930 60 0 1 0 VDD T 0 565 930 60 0 1 0 VSS X MCLR*/VPP/THV 1 -900 800 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -700 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -800 200 R 40 40 1 1 O X RA0/AN0 2 -900 600 200 R 40 40 1 1 B X RA1/AN1 3 -900 500 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 400 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 300 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 200 200 R 40 40 1 1 B X RA5/AN4 7 -900 100 200 R 40 40 1 1 B X RB0/INT 21 900 800 200 L 40 40 1 1 B X RB1 22 900 700 200 L 40 40 1 1 B X RB2 23 900 600 200 L 40 40 1 1 B X RB3/PGM 24 900 500 200 L 40 40 1 1 B X RB4 25 900 400 200 L 40 40 1 1 B X RB5 26 900 300 200 L 40 40 1 1 B X RB6/PGC 27 900 200 200 L 40 40 1 1 B X RB7/PGD 28 900 100 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -100 200 L 40 40 1 1 B X RC1/T1OSI 12 900 -200 200 L 40 40 1 1 B X RC2/CCP1 13 900 -300 200 L 40 40 1 1 B X RC3 14 900 -400 200 L 40 40 1 1 B X RC4 15 900 -500 200 L 40 40 1 1 B X RC5 16 900 -600 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -700 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -800 200 L 40 40 1 1 B X VDD 20 100 1200 200 D 40 40 1 1 W X VSS@1 8 600 1200 200 D 40 40 1 1 W X VSS@2 19 500 1200 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF870SS # Package Name: SSOP28 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF870SS U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F870 F0 "U" 0 0 50 H V R T F1 "PIC16LF870SS" -700 1100 50 H V R T F2 "pic16f87x-SSOP28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 1000 700 1000 P 2 1 0 0 700 1000 700 -900 P 2 1 0 0 700 -900 -700 -900 P 2 1 0 0 -700 -900 -700 1000 T 0 -875 1165 70 0 1 0 >PART T 0 115 930 60 0 1 0 VDD T 0 565 930 60 0 1 0 VSS X MCLR*/VPP/THV 1 -900 800 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -700 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -800 200 R 40 40 1 1 O X RA0/AN0 2 -900 600 200 R 40 40 1 1 B X RA1/AN1 3 -900 500 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 400 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 300 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 200 200 R 40 40 1 1 B X RA5/AN4 7 -900 100 200 R 40 40 1 1 B X RB0/INT 21 900 800 200 L 40 40 1 1 B X RB1 22 900 700 200 L 40 40 1 1 B X RB2 23 900 600 200 L 40 40 1 1 B X RB3/PGM 24 900 500 200 L 40 40 1 1 B X RB4 25 900 400 200 L 40 40 1 1 B X RB5 26 900 300 200 L 40 40 1 1 B X RB6/PGC 27 900 200 200 L 40 40 1 1 B X RB7/PGD 28 900 100 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -100 200 L 40 40 1 1 B X RC1/T1OSI 12 900 -200 200 L 40 40 1 1 B X RC2/CCP1 13 900 -300 200 L 40 40 1 1 B X RC3 14 900 -400 200 L 40 40 1 1 B X RC4 15 900 -500 200 L 40 40 1 1 B X RC5 16 900 -600 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -700 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -800 200 L 40 40 1 1 B X VDD 20 100 1200 200 D 40 40 1 1 W X VSS@1 8 600 1200 200 D 40 40 1 1 W X VSS@2 19 500 1200 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF871L # Package Name: PLCC-44 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF871L U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F871 F0 "U" 0 0 50 H V R T F1 "PIC16LF871L" -900 1200 50 H V R T F2 "pic16f87x-PLCC-44" 0 150 50 H I C C DRAW P 2 1 0 0 -900 1100 900 1100 P 2 1 0 0 900 1100 900 -1200 P 2 1 0 0 900 -1200 -900 -1200 P 2 1 0 0 -900 -1200 -900 1100 T 0 -1075 1265 70 0 1 0 >PART T 0 265 1030 60 0 1 0 VDD T 0 765 1030 60 0 1 0 VSS X MCLR*/VPP/THV 2 -1100 900 200 R 40 40 1 1 I X OSC1/CLKIN 14 1100 -1000 200 L 40 40 1 1 I X OSC2/CLKOUT 15 1100 -1100 200 L 40 40 1 1 O X RA0/AN0 3 -1100 700 200 R 40 40 1 1 B X RA1/AN1 4 -1100 600 200 R 40 40 1 1 B X RA2/AN2/VREF- 5 -1100 500 200 R 40 40 1 1 B X RA3/AN3/VREF+ 6 -1100 400 200 R 40 40 1 1 B X RA4/T0CKI 7 -1100 300 200 R 40 40 1 1 B X RA5/AN4 8 -1100 200 200 R 40 40 1 1 B X RB0/INT 36 1100 900 200 L 40 40 1 1 B X RB1 37 1100 800 200 L 40 40 1 1 B X RB2 38 1100 700 200 L 40 40 1 1 B X RB3/PGM 39 1100 600 200 L 40 40 1 1 B X RB4 41 1100 500 200 L 40 40 1 1 B X RB5 42 1100 400 200 L 40 40 1 1 B X RB6/PGC 43 1100 300 200 L 40 40 1 1 B X RB7/PGD 44 1100 200 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 16 1100 0 200 L 40 40 1 1 B X RC1/T1OSI 18 1100 -100 200 L 40 40 1 1 B X RC2/CCP1 19 1100 -200 200 L 40 40 1 1 B X RC3 20 1100 -300 200 L 40 40 1 1 B X RC4 25 1100 -400 200 L 40 40 1 1 B X RC5 26 1100 -500 200 L 40 40 1 1 B X RC6/TX/CK 27 1100 -600 200 L 40 40 1 1 B X RC7/RX/DT 29 1100 -700 200 L 40 40 1 1 B X RD0/PSP0 21 -1100 -400 200 R 40 40 1 1 B X RD1/PSP1 22 -1100 -500 200 R 40 40 1 1 B X RD2/PSP2 23 -1100 -600 200 R 40 40 1 1 B X RD3/PSP3 24 -1100 -700 200 R 40 40 1 1 B X RD4/PSP4 30 -1100 -800 200 R 40 40 1 1 B X RD5/PSP5 31 -1100 -900 200 R 40 40 1 1 B X RD6/PSP6 32 -1100 -1000 200 R 40 40 1 1 B X RD7/PSP7 33 -1100 -1100 200 R 40 40 1 1 B X RE0/RD*/AN5 9 -1100 0 200 R 40 40 1 1 B X RE1/WR*/AN6 10 -1100 -100 200 R 40 40 1 1 B X RE2/CS*/AN7 11 -1100 -200 200 R 40 40 1 1 B X VDD@1 12 300 1300 200 D 40 40 1 1 W X VDD@2 35 200 1300 200 D 40 40 1 1 W X VSS@1 13 800 1300 200 D 40 40 1 1 W X VSS@2 34 700 1300 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF871P # Package Name: DIL40 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF871P U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F871 F0 "U" 0 0 50 H V R T F1 "PIC16LF871P" -900 1200 50 H V R T F2 "pic16f87x-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -900 1100 900 1100 P 2 1 0 0 900 1100 900 -1200 P 2 1 0 0 900 -1200 -900 -1200 P 2 1 0 0 -900 -1200 -900 1100 T 0 -1075 1265 70 0 1 0 >PART T 0 265 1030 60 0 1 0 VDD T 0 765 1030 60 0 1 0 VSS X MCLR*/VPP/THV 1 -1100 900 200 R 40 40 1 1 I X OSC1/CLKIN 13 1100 -1000 200 L 40 40 1 1 I X OSC2/CLKOUT 14 1100 -1100 200 L 40 40 1 1 O X RA0/AN0 2 -1100 700 200 R 40 40 1 1 B X RA1/AN1 3 -1100 600 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -1100 500 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -1100 400 200 R 40 40 1 1 B X RA4/T0CKI 6 -1100 300 200 R 40 40 1 1 B X RA5/AN4 7 -1100 200 200 R 40 40 1 1 B X RB0/INT 33 1100 900 200 L 40 40 1 1 B X RB1 34 1100 800 200 L 40 40 1 1 B X RB2 35 1100 700 200 L 40 40 1 1 B X RB3/PGM 36 1100 600 200 L 40 40 1 1 B X RB4 37 1100 500 200 L 40 40 1 1 B X RB5 38 1100 400 200 L 40 40 1 1 B X RB6/PGC 39 1100 300 200 L 40 40 1 1 B X RB7/PGD 40 1100 200 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 15 1100 0 200 L 40 40 1 1 B X RC1/T1OSI 16 1100 -100 200 L 40 40 1 1 B X RC2/CCP1 17 1100 -200 200 L 40 40 1 1 B X RC3 18 1100 -300 200 L 40 40 1 1 B X RC4 23 1100 -400 200 L 40 40 1 1 B X RC5 24 1100 -500 200 L 40 40 1 1 B X RC6/TX/CK 25 1100 -600 200 L 40 40 1 1 B X RC7/RX/DT 26 1100 -700 200 L 40 40 1 1 B X RD0/PSP0 19 -1100 -400 200 R 40 40 1 1 B X RD1/PSP1 20 -1100 -500 200 R 40 40 1 1 B X RD2/PSP2 21 -1100 -600 200 R 40 40 1 1 B X RD3/PSP3 22 -1100 -700 200 R 40 40 1 1 B X RD4/PSP4 27 -1100 -800 200 R 40 40 1 1 B X RD5/PSP5 28 -1100 -900 200 R 40 40 1 1 B X RD6/PSP6 29 -1100 -1000 200 R 40 40 1 1 B X RD7/PSP7 30 -1100 -1100 200 R 40 40 1 1 B X RE0/RD*/AN5 8 -1100 0 200 R 40 40 1 1 B X RE1/WR*/AN6 9 -1100 -100 200 R 40 40 1 1 B X RE2/CS*/AN7 10 -1100 -200 200 R 40 40 1 1 B X VDD@1 11 300 1300 200 D 40 40 1 1 W X VDD@2 32 200 1300 200 D 40 40 1 1 W X VSS@1 12 800 1300 200 D 40 40 1 1 W X VSS@2 31 700 1300 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF871T # Package Name: TQFP44 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF871T U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F871 F0 "U" 0 0 50 H V R T F1 "PIC16LF871T" -900 1200 50 H V R T F2 "pic16f87x-TQFP44" 0 150 50 H I C C DRAW P 2 1 0 0 -900 1100 900 1100 P 2 1 0 0 900 1100 900 -1200 P 2 1 0 0 900 -1200 -900 -1200 P 2 1 0 0 -900 -1200 -900 1100 T 0 -1075 1265 70 0 1 0 >PART T 0 265 1030 60 0 1 0 VDD T 0 765 1030 60 0 1 0 VSS X MCLR*/VPP/THV 18 -1100 900 200 R 40 40 1 1 I X OSC1/CLKIN 30 1100 -1000 200 L 40 40 1 1 I X OSC2/CLKOUT 31 1100 -1100 200 L 40 40 1 1 O X RA0/AN0 19 -1100 700 200 R 40 40 1 1 B X RA1/AN1 20 -1100 600 200 R 40 40 1 1 B X RA2/AN2/VREF- 21 -1100 500 200 R 40 40 1 1 B X RA3/AN3/VREF+ 22 -1100 400 200 R 40 40 1 1 B X RA4/T0CKI 23 -1100 300 200 R 40 40 1 1 B X RA5/AN4 24 -1100 200 200 R 40 40 1 1 B X RB0/INT 8 1100 900 200 L 40 40 1 1 B X RB1 9 1100 800 200 L 40 40 1 1 B X RB2 10 1100 700 200 L 40 40 1 1 B X RB3/PGM 11 1100 600 200 L 40 40 1 1 B X RB4 14 1100 500 200 L 40 40 1 1 B X RB5 15 1100 400 200 L 40 40 1 1 B X RB6/PGC 16 1100 300 200 L 40 40 1 1 B X RB7/PGD 17 1100 200 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 32 1100 0 200 L 40 40 1 1 B X RC1/T1OSI 35 1100 -100 200 L 40 40 1 1 B X RC2/CCP1 36 1100 -200 200 L 40 40 1 1 B X RC3 37 1100 -300 200 L 40 40 1 1 B X RC4 42 1100 -400 200 L 40 40 1 1 B X RC5 43 1100 -500 200 L 40 40 1 1 B X RC6/TX/CK 44 1100 -600 200 L 40 40 1 1 B X RC7/RX/DT 1 1100 -700 200 L 40 40 1 1 B X RD0/PSP0 38 -1100 -400 200 R 40 40 1 1 B X RD1/PSP1 39 -1100 -500 200 R 40 40 1 1 B X RD2/PSP2 40 -1100 -600 200 R 40 40 1 1 B X RD3/PSP3 41 -1100 -700 200 R 40 40 1 1 B X RD4/PSP4 2 -1100 -800 200 R 40 40 1 1 B X RD5/PSP5 3 -1100 -900 200 R 40 40 1 1 B X RD6/PSP6 4 -1100 -1000 200 R 40 40 1 1 B X RD7/PSP7 5 -1100 -1100 200 R 40 40 1 1 B X RE0/RD*/AN5 25 -1100 0 200 R 40 40 1 1 B X RE1/WR*/AN6 26 -1100 -100 200 R 40 40 1 1 B X RE2/CS*/AN7 27 -1100 -200 200 R 40 40 1 1 B X VDD@1 7 300 1300 200 D 40 40 1 1 W X VDD@2 28 200 1300 200 D 40 40 1 1 W X VSS@1 6 800 1300 200 D 40 40 1 1 W X VSS@2 29 700 1300 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF872P # Package Name: DIL28-3 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF872P U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F872 F0 "U" 0 0 50 H V R T F1 "PIC16LF872P" -700 1000 50 H V R T F2 "pic16f87x-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 115 830 60 0 1 0 VDD T 0 565 830 60 0 1 0 VSS X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 O X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 600 1100 200 D 40 40 1 1 W X VSS@2 19 500 1100 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF872SO # Package Name: S0-28 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF872SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F872 F0 "U" 0 0 50 H V R T F1 "PIC16LF872SO" -700 1000 50 H V R T F2 "pic16f87x-S0-28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 115 830 60 0 1 0 VDD T 0 565 830 60 0 1 0 VSS X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 O X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 600 1100 200 D 40 40 1 1 W X VSS@2 19 500 1100 200 D 40 40 1 1 W ENDDRAW ENDDEF # # Dev Name: PIC16LF872SS # Package Name: SSOP28 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC16LF872SS U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC16F872 F0 "U" 0 0 50 H V R T F1 "PIC16LF872SS" -700 1000 50 H V R T F2 "pic16f87x-SSOP28" 0 150 50 H I C C DRAW P 2 1 0 0 -700 900 700 900 P 2 1 0 0 700 900 700 -1000 P 2 1 0 0 700 -1000 -700 -1000 P 2 1 0 0 -700 -1000 -700 900 T 0 -875 1065 70 0 1 0 >PART T 0 115 830 60 0 1 0 VDD T 0 565 830 60 0 1 0 VSS X MCLR*/VPP 1 -900 700 200 R 40 40 1 1 I X OSC1/CLKIN 9 -900 -800 200 R 40 40 1 1 I X OSC2/CLKOUT 10 -900 -900 200 R 40 40 1 1 O X RA0/AN0 2 -900 500 200 R 40 40 1 1 B X RA1/AN1 3 -900 400 200 R 40 40 1 1 B X RA2/AN2/VREF- 4 -900 300 200 R 40 40 1 1 B X RA3/AN3/VREF+ 5 -900 200 200 R 40 40 1 1 B X RA4/T0CKI 6 -900 100 200 R 40 40 1 1 B X RA5/AN4/SS* 7 -900 0 200 R 40 40 1 1 B X RB0/INT 21 900 700 200 L 40 40 1 1 B X RB1 22 900 600 200 L 40 40 1 1 B X RB2 23 900 500 200 L 40 40 1 1 B X RB3/PGM 24 900 400 200 L 40 40 1 1 B X RB4 25 900 300 200 L 40 40 1 1 B X RB5 26 900 200 200 L 40 40 1 1 B X RB6/PGC 27 900 100 200 L 40 40 1 1 B X RB7/PGD 28 900 0 200 L 40 40 1 1 B X RC0/T1OSO/T1CKI 11 900 -200 200 L 40 40 1 1 B X RC1/T1OSI/CCP2 12 900 -300 200 L 40 40 1 1 B X RC2/CCP1 13 900 -400 200 L 40 40 1 1 B X RC3/SCK/SCL 14 900 -500 200 L 40 40 1 1 B X RC4/SDI/SDA 15 900 -600 200 L 40 40 1 1 B X RC5/SDO 16 900 -700 200 L 40 40 1 1 B X RC6/TX/CK 17 900 -800 200 L 40 40 1 1 B X RC7/RX/DT 18 900 -900 200 L 40 40 1 1 B X VDD 20 100 1100 200 D 40 40 1 1 W X VSS@1 8 600 1100 200 D 40 40 1 1 W X VSS@2 19 500 1100 200 D 40 40 1 1 W ENDDRAW ENDDEF #End Library