EESchema-LIBRARY Version 2.3  29/04/2008-12:23:20
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 5
#
# Dev Name: PIC18F4X2DIL40
# Package Name: DIL40
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PIC18F4X2DIL40 IC 0 40 Y Y 2 L N
# Gate Name: _A
# Symbol Name: PIC18F4X2
F0 "IC" -600 1325 50 H V L B
F1 "PIC18F4X2DIL40" 0 0 50 H V L B
F2 "pic18f4x2-DIL40" 0 150 50 H I C C
DRAW
P 2 1 0 0 -900 -1300 900 -1300
P 2 1 0 0 900 -1300 900 1300
P 2 1 0 0 900 1300 -900 1300
P 2 1 0 0 -900 1300 -900 -1300
P 2 1 0 0 -370 650 -270 650
P 2 1 0 0 470 -50 570 -50
P 2 1 0 0 470 -150 570 -150
P 2 1 0 0 10 1150 220 1150
P 2 1 0 0 470 -250 570 -250
T 0 20 1225 70 0 1 0 PIC~18F4x2
X MCLR/(ICSP_VPP) 1 1100 1100 200 L 40 40 1 1 W 
X OSC1/CLKI 13 1100 600 200 L 40 40 1 1 W 
X OSC2/CLKO/RA6 14 1100 200 200 L 40 40 1 1 W 
X RA0/AN0 2 -1100 1100 200 R 40 40 1 1 B 
X RA1/AN1 3 -1100 1000 200 R 40 40 1 1 B 
X RA2/AN2/VREF- 4 -1100 900 200 R 40 40 1 1 B 
X RA3/AN3/VREF+ 5 -1100 800 200 R 40 40 1 1 B 
X RA4/T0CLK 6 -1100 700 200 R 40 40 1 1 B 
X RA5/AN4/SS/LVDIN 7 -1100 600 200 R 40 40 1 1 B 
X RB0/INT0 33 -1100 400 200 R 40 40 1 1 B 
X RB1/INT1 34 -1100 300 200 R 40 40 1 1 B 
X RB2/INT2 35 -1100 200 200 R 40 40 1 1 B 
X RB3/CCP2* 36 -1100 100 200 R 40 40 1 1 B 
X RB4 37 -1100 0 200 R 40 40 1 1 B 
X RB5/PGM/(ICSP_VLVP) 38 -1100 -100 200 R 40 40 1 1 B 
X RB6/PGC/(ICSP_CLK) 39 -1100 -200 200 R 40 40 1 1 B 
X RB7/PGD/(ICSP_DATA) 40 -1100 -300 200 R 40 40 1 1 B 
X RC0/T1OSO/T1CLK 15 -1100 -500 200 R 40 40 1 1 B 
X RC1/T1OSI/CCP2* 16 -1100 -600 200 R 40 40 1 1 B 
X RC2/CCP1 17 -1100 -700 200 R 40 40 1 1 B 
X RC3/SCK/SCL 18 -1100 -800 200 R 40 40 1 1 B 
X RC4/SDI/SDA 23 -1100 -900 200 R 40 40 1 1 B 
X RC5/SDO 24 -1100 -1000 200 R 40 40 1 1 B 
X RC6/TX/CK 25 -1100 -1100 200 R 40 40 1 1 B 
X RC7/RX/DT 26 -1100 -1200 200 R 40 40 1 1 B 
X RD0/PSP0 19 1100 -500 200 L 40 40 1 1 B 
X RD1/PSP1 20 1100 -600 200 L 40 40 1 1 B 
X RD2/PSP2 21 1100 -700 200 L 40 40 1 1 B 
X RD3/PSP3 22 1100 -800 200 L 40 40 1 1 B 
X RD4/PSP4 27 1100 -900 200 L 40 40 1 1 B 
X RD5/PSP5 28 1100 -1000 200 L 40 40 1 1 B 
X RD6/PSP6 29 1100 -1100 200 L 40 40 1 1 B 
X RD7/PSP7 30 1100 -1200 200 L 40 40 1 1 B 
X RE0/RD/AN5 8 1100 -100 200 L 40 40 1 1 B 
X RE1/WR/AN6 9 1100 -200 200 L 40 40 1 1 B 
X RE2/CS/AN7 10 1100 -300 200 L 40 40 1 1 B 
# Gate Name: _B
# Symbol Name: VCCGND
P 2 2 0 0 -100 300 100 300
P 2 2 0 0 -100 -400 100 -400
X GND1 12 -100 -600 200 U 40 40 2 1 W 
X GND2 31 100 -600 200 U 40 40 2 1 W 
X VDD1 11 -100 500 200 D 40 40 2 1 W 
X VDD2 32 100 500 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: PIC18F4X2PLCC44
# Package Name: PLCC44
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PIC18F4X2PLCC44 IC 0 40 Y Y 2 L N
# Gate Name: _A
# Symbol Name: PIC18F4X2
F0 "IC" -600 1325 50 H V L B
F1 "PIC18F4X2PLCC44" 0 0 50 H V L B
F2 "pic18f4x2-PLCC44" 0 150 50 H I C C
DRAW
P 2 1 0 0 -900 -1300 900 -1300
P 2 1 0 0 900 -1300 900 1300
P 2 1 0 0 900 1300 -900 1300
P 2 1 0 0 -900 1300 -900 -1300
P 2 1 0 0 -370 650 -270 650
P 2 1 0 0 470 -50 570 -50
P 2 1 0 0 470 -150 570 -150
P 2 1 0 0 10 1150 220 1150
P 2 1 0 0 470 -250 570 -250
T 0 20 1225 70 0 1 0 PIC~18F4x2
X MCLR/(ICSP_VPP) 2 1100 1100 200 L 40 40 1 1 W 
X OSC1/CLKI 14 1100 600 200 L 40 40 1 1 W 
X OSC2/CLKO/RA6 15 1100 200 200 L 40 40 1 1 W 
X RA0/AN0 3 -1100 1100 200 R 40 40 1 1 B 
X RA1/AN1 4 -1100 1000 200 R 40 40 1 1 B 
X RA2/AN2/VREF- 5 -1100 900 200 R 40 40 1 1 B 
X RA3/AN3/VREF+ 6 -1100 800 200 R 40 40 1 1 B 
X RA4/T0CLK 7 -1100 700 200 R 40 40 1 1 B 
X RA5/AN4/SS/LVDIN 8 -1100 600 200 R 40 40 1 1 B 
X RB0/INT0 36 -1100 400 200 R 40 40 1 1 B 
X RB1/INT1 37 -1100 300 200 R 40 40 1 1 B 
X RB2/INT2 38 -1100 200 200 R 40 40 1 1 B 
X RB3/CCP2* 39 -1100 100 200 R 40 40 1 1 B 
X RB4 41 -1100 0 200 R 40 40 1 1 B 
X RB5/PGM/(ICSP_VLVP) 42 -1100 -100 200 R 40 40 1 1 B 
X RB6/PGC/(ICSP_CLK) 43 -1100 -200 200 R 40 40 1 1 B 
X RB7/PGD/(ICSP_DATA) 44 -1100 -300 200 R 40 40 1 1 B 
X RC0/T1OSO/T1CLK 16 -1100 -500 200 R 40 40 1 1 B 
X RC1/T1OSI/CCP2* 18 -1100 -600 200 R 40 40 1 1 B 
X RC2/CCP1 19 -1100 -700 200 R 40 40 1 1 B 
X RC3/SCK/SCL 20 -1100 -800 200 R 40 40 1 1 B 
X RC4/SDI/SDA 25 -1100 -900 200 R 40 40 1 1 B 
X RC5/SDO 26 -1100 -1000 200 R 40 40 1 1 B 
X RC6/TX/CK 27 -1100 -1100 200 R 40 40 1 1 B 
X RC7/RX/DT 29 -1100 -1200 200 R 40 40 1 1 B 
X RD0/PSP0 21 1100 -500 200 L 40 40 1 1 B 
X RD1/PSP1 22 1100 -600 200 L 40 40 1 1 B 
X RD2/PSP2 23 1100 -700 200 L 40 40 1 1 B 
X RD3/PSP3 24 1100 -800 200 L 40 40 1 1 B 
X RD4/PSP4 30 1100 -900 200 L 40 40 1 1 B 
X RD5/PSP5 31 1100 -1000 200 L 40 40 1 1 B 
X RD6/PSP6 32 1100 -1100 200 L 40 40 1 1 B 
X RD7/PSP7 33 1100 -1200 200 L 40 40 1 1 B 
X RE0/RD/AN5 9 1100 -100 200 L 40 40 1 1 B 
X RE1/WR/AN6 10 1100 -200 200 L 40 40 1 1 B 
X RE2/CS/AN7 11 1100 -300 200 L 40 40 1 1 B 
# Gate Name: _B
# Symbol Name: VCCGND
P 2 2 0 0 -100 300 100 300
P 2 2 0 0 -100 -400 100 -400
X GND1 13 -100 -600 200 U 40 40 2 1 W 
X GND2 34 100 -600 200 U 40 40 2 1 W 
X VDD1 12 -100 500 200 D 40 40 2 1 W 
X VDD2 35 100 500 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: PIC18F4X2PLCC_SMD-SOCKET
# Package Name: PLCCSM44
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PIC18F4X2PLCC_SMD-SOCKET IC 0 40 Y Y 2 L N
# Gate Name: _A
# Symbol Name: PIC18F4X2
F0 "IC" -600 1325 50 H V L B
F1 "PIC18F4X2PLCC_SMD-SOCKET" 0 0 50 H V L B
F2 "pic18f4x2-PLCCSM44" 0 150 50 H I C C
DRAW
P 2 1 0 0 -900 -1300 900 -1300
P 2 1 0 0 900 -1300 900 1300
P 2 1 0 0 900 1300 -900 1300
P 2 1 0 0 -900 1300 -900 -1300
P 2 1 0 0 -370 650 -270 650
P 2 1 0 0 470 -50 570 -50
P 2 1 0 0 470 -150 570 -150
P 2 1 0 0 10 1150 220 1150
P 2 1 0 0 470 -250 570 -250
T 0 20 1225 70 0 1 0 PIC~18F4x2
X MCLR/(ICSP_VPP) 2 1100 1100 200 L 40 40 1 1 W 
X OSC1/CLKI 14 1100 600 200 L 40 40 1 1 W 
X OSC2/CLKO/RA6 15 1100 200 200 L 40 40 1 1 W 
X RA0/AN0 3 -1100 1100 200 R 40 40 1 1 B 
X RA1/AN1 4 -1100 1000 200 R 40 40 1 1 B 
X RA2/AN2/VREF- 5 -1100 900 200 R 40 40 1 1 B 
X RA3/AN3/VREF+ 6 -1100 800 200 R 40 40 1 1 B 
X RA4/T0CLK 7 -1100 700 200 R 40 40 1 1 B 
X RA5/AN4/SS/LVDIN 8 -1100 600 200 R 40 40 1 1 B 
X RB0/INT0 36 -1100 400 200 R 40 40 1 1 B 
X RB1/INT1 37 -1100 300 200 R 40 40 1 1 B 
X RB2/INT2 38 -1100 200 200 R 40 40 1 1 B 
X RB3/CCP2* 39 -1100 100 200 R 40 40 1 1 B 
X RB4 41 -1100 0 200 R 40 40 1 1 B 
X RB5/PGM/(ICSP_VLVP) 42 -1100 -100 200 R 40 40 1 1 B 
X RB6/PGC/(ICSP_CLK) 43 -1100 -200 200 R 40 40 1 1 B 
X RB7/PGD/(ICSP_DATA) 44 -1100 -300 200 R 40 40 1 1 B 
X RC0/T1OSO/T1CLK 16 -1100 -500 200 R 40 40 1 1 B 
X RC1/T1OSI/CCP2* 18 -1100 -600 200 R 40 40 1 1 B 
X RC2/CCP1 19 -1100 -700 200 R 40 40 1 1 B 
X RC3/SCK/SCL 20 -1100 -800 200 R 40 40 1 1 B 
X RC4/SDI/SDA 25 -1100 -900 200 R 40 40 1 1 B 
X RC5/SDO 26 -1100 -1000 200 R 40 40 1 1 B 
X RC6/TX/CK 27 -1100 -1100 200 R 40 40 1 1 B 
X RC7/RX/DT 29 -1100 -1200 200 R 40 40 1 1 B 
X RD0/PSP0 21 1100 -500 200 L 40 40 1 1 B 
X RD1/PSP1 22 1100 -600 200 L 40 40 1 1 B 
X RD2/PSP2 23 1100 -700 200 L 40 40 1 1 B 
X RD3/PSP3 24 1100 -800 200 L 40 40 1 1 B 
X RD4/PSP4 30 1100 -900 200 L 40 40 1 1 B 
X RD5/PSP5 31 1100 -1000 200 L 40 40 1 1 B 
X RD6/PSP6 32 1100 -1100 200 L 40 40 1 1 B 
X RD7/PSP7 33 1100 -1200 200 L 40 40 1 1 B 
X RE0/RD/AN5 9 1100 -100 200 L 40 40 1 1 B 
X RE1/WR/AN6 10 1100 -200 200 L 40 40 1 1 B 
X RE2/CS/AN7 11 1100 -300 200 L 40 40 1 1 B 
# Gate Name: _B
# Symbol Name: VCCGND
P 2 2 0 0 -100 300 100 300
P 2 2 0 0 -100 -400 100 -400
X GND1 13 -100 -600 200 U 40 40 2 1 W 
X GND2 34 100 -600 200 U 40 40 2 1 W 
X VDD1 12 -100 500 200 D 40 40 2 1 W 
X VDD2 35 100 500 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: PIC18F4X2PLCC_SOCKET
# Package Name: S44
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PIC18F4X2PLCC_SOCKET IC 0 40 Y Y 2 L N
# Gate Name: _A
# Symbol Name: PIC18F4X2
F0 "IC" -600 1325 50 H V L B
F1 "PIC18F4X2PLCC_SOCKET" 0 0 50 H V L B
F2 "pic18f4x2-S44" 0 150 50 H I C C
DRAW
P 2 1 0 0 -900 -1300 900 -1300
P 2 1 0 0 900 -1300 900 1300
P 2 1 0 0 900 1300 -900 1300
P 2 1 0 0 -900 1300 -900 -1300
P 2 1 0 0 -370 650 -270 650
P 2 1 0 0 470 -50 570 -50
P 2 1 0 0 470 -150 570 -150
P 2 1 0 0 10 1150 220 1150
P 2 1 0 0 470 -250 570 -250
T 0 20 1225 70 0 1 0 PIC~18F4x2
X MCLR/(ICSP_VPP) 2 1100 1100 200 L 40 40 1 1 W 
X OSC1/CLKI 14 1100 600 200 L 40 40 1 1 W 
X OSC2/CLKO/RA6 15 1100 200 200 L 40 40 1 1 W 
X RA0/AN0 3 -1100 1100 200 R 40 40 1 1 B 
X RA1/AN1 4 -1100 1000 200 R 40 40 1 1 B 
X RA2/AN2/VREF- 5 -1100 900 200 R 40 40 1 1 B 
X RA3/AN3/VREF+ 6 -1100 800 200 R 40 40 1 1 B 
X RA4/T0CLK 7 -1100 700 200 R 40 40 1 1 B 
X RA5/AN4/SS/LVDIN 8 -1100 600 200 R 40 40 1 1 B 
X RB0/INT0 36 -1100 400 200 R 40 40 1 1 B 
X RB1/INT1 37 -1100 300 200 R 40 40 1 1 B 
X RB2/INT2 38 -1100 200 200 R 40 40 1 1 B 
X RB3/CCP2* 39 -1100 100 200 R 40 40 1 1 B 
X RB4 41 -1100 0 200 R 40 40 1 1 B 
X RB5/PGM/(ICSP_VLVP) 42 -1100 -100 200 R 40 40 1 1 B 
X RB6/PGC/(ICSP_CLK) 43 -1100 -200 200 R 40 40 1 1 B 
X RB7/PGD/(ICSP_DATA) 44 -1100 -300 200 R 40 40 1 1 B 
X RC0/T1OSO/T1CLK 16 -1100 -500 200 R 40 40 1 1 B 
X RC1/T1OSI/CCP2* 18 -1100 -600 200 R 40 40 1 1 B 
X RC2/CCP1 19 -1100 -700 200 R 40 40 1 1 B 
X RC3/SCK/SCL 20 -1100 -800 200 R 40 40 1 1 B 
X RC4/SDI/SDA 25 -1100 -900 200 R 40 40 1 1 B 
X RC5/SDO 26 -1100 -1000 200 R 40 40 1 1 B 
X RC6/TX/CK 27 -1100 -1100 200 R 40 40 1 1 B 
X RC7/RX/DT 29 -1100 -1200 200 R 40 40 1 1 B 
X RD0/PSP0 21 1100 -500 200 L 40 40 1 1 B 
X RD1/PSP1 22 1100 -600 200 L 40 40 1 1 B 
X RD2/PSP2 23 1100 -700 200 L 40 40 1 1 B 
X RD3/PSP3 24 1100 -800 200 L 40 40 1 1 B 
X RD4/PSP4 30 1100 -900 200 L 40 40 1 1 B 
X RD5/PSP5 31 1100 -1000 200 L 40 40 1 1 B 
X RD6/PSP6 32 1100 -1100 200 L 40 40 1 1 B 
X RD7/PSP7 33 1100 -1200 200 L 40 40 1 1 B 
X RE0/RD/AN5 9 1100 -100 200 L 40 40 1 1 B 
X RE1/WR/AN6 10 1100 -200 200 L 40 40 1 1 B 
X RE2/CS/AN7 11 1100 -300 200 L 40 40 1 1 B 
# Gate Name: _B
# Symbol Name: VCCGND
P 2 2 0 0 -100 300 100 300
P 2 2 0 0 -100 -400 100 -400
X GND1 13 -100 -600 200 U 40 40 2 1 W 
X GND2 34 100 -600 200 U 40 40 2 1 W 
X VDD1 12 -100 500 200 D 40 40 2 1 W 
X VDD2 35 100 500 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: PIC18F4X2TQFP44
# Package Name: TQFP44
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PIC18F4X2TQFP44 IC 0 40 Y Y 2 L N
# Gate Name: _A
# Symbol Name: PIC18F4X2
F0 "IC" -600 1325 50 H V L B
F1 "PIC18F4X2TQFP44" 0 0 50 H V L B
F2 "pic18f4x2-TQFP44" 0 150 50 H I C C
DRAW
P 2 1 0 0 -900 -1300 900 -1300
P 2 1 0 0 900 -1300 900 1300
P 2 1 0 0 900 1300 -900 1300
P 2 1 0 0 -900 1300 -900 -1300
P 2 1 0 0 -370 650 -270 650
P 2 1 0 0 470 -50 570 -50
P 2 1 0 0 470 -150 570 -150
P 2 1 0 0 10 1150 220 1150
P 2 1 0 0 470 -250 570 -250
T 0 20 1225 70 0 1 0 PIC~18F4x2
X MCLR/(ICSP_VPP) 18 1100 1100 200 L 40 40 1 1 W 
X OSC1/CLKI 30 1100 600 200 L 40 40 1 1 W 
X OSC2/CLKO/RA6 31 1100 200 200 L 40 40 1 1 W 
X RA0/AN0 19 -1100 1100 200 R 40 40 1 1 B 
X RA1/AN1 20 -1100 1000 200 R 40 40 1 1 B 
X RA2/AN2/VREF- 21 -1100 900 200 R 40 40 1 1 B 
X RA3/AN3/VREF+ 22 -1100 800 200 R 40 40 1 1 B 
X RA4/T0CLK 23 -1100 700 200 R 40 40 1 1 B 
X RA5/AN4/SS/LVDIN 24 -1100 600 200 R 40 40 1 1 B 
X RB0/INT0 8 -1100 400 200 R 40 40 1 1 B 
X RB1/INT1 9 -1100 300 200 R 40 40 1 1 B 
X RB2/INT2 10 -1100 200 200 R 40 40 1 1 B 
X RB3/CCP2* 11 -1100 100 200 R 40 40 1 1 B 
X RB4 14 -1100 0 200 R 40 40 1 1 B 
X RB5/PGM/(ICSP_VLVP) 15 -1100 -100 200 R 40 40 1 1 B 
X RB6/PGC/(ICSP_CLK) 16 -1100 -200 200 R 40 40 1 1 B 
X RB7/PGD/(ICSP_DATA) 17 -1100 -300 200 R 40 40 1 1 B 
X RC0/T1OSO/T1CLK 32 -1100 -500 200 R 40 40 1 1 B 
X RC1/T1OSI/CCP2* 35 -1100 -600 200 R 40 40 1 1 B 
X RC2/CCP1 36 -1100 -700 200 R 40 40 1 1 B 
X RC3/SCK/SCL 37 -1100 -800 200 R 40 40 1 1 B 
X RC4/SDI/SDA 42 -1100 -900 200 R 40 40 1 1 B 
X RC5/SDO 43 -1100 -1000 200 R 40 40 1 1 B 
X RC6/TX/CK 44 -1100 -1100 200 R 40 40 1 1 B 
X RC7/RX/DT 1 -1100 -1200 200 R 40 40 1 1 B 
X RD0/PSP0 38 1100 -500 200 L 40 40 1 1 B 
X RD1/PSP1 39 1100 -600 200 L 40 40 1 1 B 
X RD2/PSP2 40 1100 -700 200 L 40 40 1 1 B 
X RD3/PSP3 41 1100 -800 200 L 40 40 1 1 B 
X RD4/PSP4 2 1100 -900 200 L 40 40 1 1 B 
X RD5/PSP5 3 1100 -1000 200 L 40 40 1 1 B 
X RD6/PSP6 4 1100 -1100 200 L 40 40 1 1 B 
X RD7/PSP7 5 1100 -1200 200 L 40 40 1 1 B 
X RE0/RD/AN5 25 1100 -100 200 L 40 40 1 1 B 
X RE1/WR/AN6 26 1100 -200 200 L 40 40 1 1 B 
X RE2/CS/AN7 27 1100 -300 200 L 40 40 1 1 B 
# Gate Name: _B
# Symbol Name: VCCGND
P 2 2 0 0 -100 300 100 300
P 2 2 0 0 -100 -400 100 -400
X GND1 6 -100 -600 200 U 40 40 2 1 W 
X GND2 29 100 -600 200 U 40 40 2 1 W 
X VDD1 7 -100 500 200 D 40 40 2 1 W 
X VDD2 28 100 500 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#End Library