EESchema-LIBRARY Version 2.3 29/04/2008-12:23:21 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 32 # # Dev Name: PIC18F2420-E/SO # Package Name: SO-28W # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC18F2420-E/SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18F2420-E/SO" -1200 1100 50 H V L B F2 "pic18fxx20-SO-28W" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F2420-E/SP # Package Name: DIL28-3 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC18F2420-E/SP U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18F2420-E/SP" -1200 1100 50 H V L B F2 "pic18fxx20-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F2420-I/SO # Package Name: SO-28W # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC18F2420-I/SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18F2420-I/SO" -1200 1100 50 H V L B F2 "pic18fxx20-SO-28W" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F2420-I/SP # Package Name: DIL28-3 # Dev Tech: F # Dev Prefix: U # Gate count = 1 # DEF PIC18F2420-I/SP U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18F2420-I/SP" -1200 1100 50 H V L B F2 "pic18fxx20-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F2520-E/SO # Package Name: SO-28W # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F2520-E/SO ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F2520-E/SP # Package Name: DIL28-3 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F2520-E/SP ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F2520-I/SO # Package Name: SO-28W # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F2520-I/SO ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F2520-I/SP # Package Name: DIL28-3 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F2520-I/SP ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4420-E/P # Package Name: DIL40 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4420-E/P ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4420-E/PT # Package Name: TQFP44 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4420-E/PT ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4420-I/P # Package Name: DIL40 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4420-I/P ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4420-I/PT # Package Name: TQFP44 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4420-I/PT ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4520-E/P # Package Name: DIL40 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4520-E/P ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4520-E/PT # Package Name: TQFP44 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4520-E/PT ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4520-I/P # Package Name: DIL40 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4520-I/P ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18F4520-I/PT # Package Name: TQFP44 # Dev Tech: F # Dev Prefix: # Gate count = 1 # DEF PIC18F4520-I/PT ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2420-E/SO # Package Name: SO-28W # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC18LF2420-E/SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18LF2420-E/SO" -1200 1100 50 H V L B F2 "pic18fxx20-SO-28W" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2420-E/SP # Package Name: DIL28-3 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC18LF2420-E/SP U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18LF2420-E/SP" -1200 1100 50 H V L B F2 "pic18fxx20-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2420-I/SO # Package Name: SO-28W # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC18LF2420-I/SO U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18LF2420-I/SO" -1200 1100 50 H V L B F2 "pic18fxx20-SO-28W" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2420-I/SP # Package Name: DIL28-3 # Dev Tech: LF # Dev Prefix: U # Gate count = 1 # DEF PIC18LF2420-I/SP U 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 F0 "U" -1200 1300 50 H V L B F1 "PIC18LF2420-I/SP" -1200 1100 50 H V L B F2 "pic18fxx20-DIL28-3" 0 150 50 H I C C DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2520-E/SO # Package Name: SO-28W # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF2520-E/SO ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2520-E/SP # Package Name: DIL28-3 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF2520-E/SP ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2520-I/SO # Package Name: SO-28W # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF2520-I/SO ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF2520-I/SP # Package Name: DIL28-3 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF2520-I/SP ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F2420 DRAW P 2 1 0 0 300 1200 300 -1700 P 2 1 0 0 300 -1700 -1300 -1700 P 2 1 0 0 -1300 -1700 -1300 1200 P 2 1 0 0 -1300 1200 300 1200 X AN0/RA0 2 500 1100 200 L 40 40 1 1 B X AN1/RA1 3 500 1000 200 L 40 40 1 1 B X CCP1/RC2 13 500 -900 200 L 40 40 1 1 B X CCP2/AN9/RB3 24 500 -100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 21 500 200 200 L 40 40 1 1 B X INT1/AN10/RB1 22 500 100 200 L 40 40 1 1 B X INT2/AN8/RB2 23 500 0 200 L 40 40 1 1 B X KBI0/AN11/RB4 25 500 -200 200 L 40 40 1 1 B X KBI1/PGM/RB5 26 500 -300 200 L 40 40 1 1 B X KBI2/PGC/RB6 27 500 -400 200 L 40 40 1 1 B X KBI3/PGD/RB7 28 500 -500 200 L 40 40 1 1 B X OSC1/CLKI/RA7 9 500 400 200 L 40 40 1 1 B X OSC2/CLKO/RA6 10 500 500 200 L 40 40 1 1 B X RX/DT/RC7 18 500 -1400 200 L 40 40 1 1 B X SCK/SCL/RC3 14 500 -1000 200 L 40 40 1 1 B X SDI/SDA/RC4 15 500 -1100 200 L 40 40 1 1 B X SDO/RC5 16 500 -1200 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 500 700 200 L 40 40 1 1 B X T1OSI/CCP2/RC1 12 500 -800 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 11 500 -700 200 L 40 40 1 1 B X TX/CK/RC6 17 500 -1300 200 L 40 40 1 1 B X VDD 20 -1500 -600 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 500 800 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 500 900 200 L 40 40 1 1 B X VSS@0 8 -1500 -200 200 R 40 40 1 1 W X VSS@1 19 -1500 -300 200 R 40 40 1 1 W X _MCLR/VPP/RE3 1 500 -1600 200 L 40 40 1 1 I X _SS/HLVDIN/C2OUT/AN4/RA5 7 500 600 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4420-E/P # Package Name: DIL40 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4420-E/P ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4420-E/PT # Package Name: TQFP44 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4420-E/PT ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4420-I/P # Package Name: DIL40 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4420-I/P ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4420-I/PT # Package Name: TQFP44 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4420-I/PT ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4520-E/P # Package Name: DIL40 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4520-E/P ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4520-E/PT # Package Name: TQFP44 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4520-E/PT ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4520-I/P # Package Name: DIL40 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4520-I/P ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 2 200 2000 200 L 40 40 1 1 B X AN1/RA1 3 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 17 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 36 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 16 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 33 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 34 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 35 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 37 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 38 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 39 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 40 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 13 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 14 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 28 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 29 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 30 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 19 200 -700 200 L 40 40 1 1 B X PSP1/RD1 20 200 -800 200 L 40 40 1 1 B X PSP2/RD2 21 200 -900 200 L 40 40 1 1 B X PSP3/RD3 22 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 27 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 26 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 18 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 23 200 -200 200 L 40 40 1 1 B X SDO/RC5 24 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 6 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 15 200 200 200 L 40 40 1 1 B X TX/CK/RC6 25 200 -400 200 L 40 40 1 1 B X VDD@0 11 -1700 1000 200 R 40 40 1 1 W X VDD@1 32 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 5 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 4 200 1800 200 L 40 40 1 1 B X VSS@0 12 -1700 900 200 R 40 40 1 1 W X VSS@1 31 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 10 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 1 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 8 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 7 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 9 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF # # Dev Name: PIC18LF4520-I/PT # Package Name: TQFP44 # Dev Tech: LF # Dev Prefix: # Gate count = 1 # DEF PIC18LF4520-I/PT ?? 0 40 Y Y 1 L N # Gate Name: G$2 # Symbol Name: PIC18F4420 DRAW P 2 1 0 0 -1500 2100 0 2100 P 2 1 0 0 0 2100 0 -2000 P 2 1 0 0 0 -2000 -1500 -2000 P 2 1 0 0 -1500 -2000 -1500 2100 X AN0/RA0 19 200 2000 200 L 40 40 1 1 B X AN1/RA1 20 200 1900 200 L 40 40 1 1 B X CCP1/P1A/RC2 36 200 0 200 L 40 40 1 1 B X CCP2/AN9/RB3 11 200 800 200 L 40 40 1 1 B X I1OSI/CCP2/RC1 35 200 100 200 L 40 40 1 1 B X INT0/FLT0/AN12/RB0 8 200 1100 200 L 40 40 1 1 B X INT1/AN10/RB1 9 200 1000 200 L 40 40 1 1 B X INT2/AN8/RB2 10 200 900 200 L 40 40 1 1 B X KBI0/AN11/RB4 14 200 700 200 L 40 40 1 1 B X KBI1/PGM/RB5 15 200 600 200 L 40 40 1 1 B X KBI2/PGC/RB6 16 200 500 200 L 40 40 1 1 B X KBI3/PGD/RB7 17 200 400 200 L 40 40 1 1 B X OSC1/CLKI/RA7 30 200 1300 200 L 40 40 1 1 B X OSC2/CLKO/RA6 31 200 1400 200 L 40 40 1 1 B X P1B/PSP5/RD5 3 200 -1200 200 L 40 40 1 1 B X P1C/PSP6/RD6 4 200 -1300 200 L 40 40 1 1 B X P1D/PSP7/RD7 5 200 -1400 200 L 40 40 1 1 B X PSP0/RD0 38 200 -700 200 L 40 40 1 1 B X PSP1/RD1 39 200 -800 200 L 40 40 1 1 B X PSP2/RD2 40 200 -900 200 L 40 40 1 1 B X PSP3/RD3 41 200 -1000 200 L 40 40 1 1 B X PSP4/RD4 2 200 -1100 200 L 40 40 1 1 B X RX/DT/RC7 1 200 -500 200 L 40 40 1 1 B X SCK/SCL/RC3 37 200 -100 200 L 40 40 1 1 B X SDI/SDA/RC4 42 200 -200 200 L 40 40 1 1 B X SDO/RC5 43 200 -300 200 L 40 40 1 1 B X T0CKI/C1OUT/RA4 23 200 1600 200 L 40 40 1 1 B X T1OSO/T13CKI/RC0 32 200 200 200 L 40 40 1 1 B X TX/CK/RC6 44 200 -400 200 L 40 40 1 1 B X VDD@0 7 -1700 1000 200 R 40 40 1 1 W X VDD@1 28 -1700 -1100 200 R 40 40 1 1 W X VREF+/AN3/RA3 22 200 1700 200 L 40 40 1 1 B X VREF-/CVREF/AN2/RA2 21 200 1800 200 L 40 40 1 1 B X VSS@0 6 -1700 900 200 R 40 40 1 1 W X VSS@1 29 -1700 -1000 200 R 40 40 1 1 W X _CS/AN7/RE2 27 200 -1800 200 L 40 40 1 1 B X _MCLR/VPP/RE3 18 200 -1900 200 L 40 40 1 1 I X _RD/AN5/RE0 25 200 -1600 200 L 40 40 1 1 B X _SS/HLVDIN/C2OUT/AN4/RA5 24 200 1500 200 L 40 40 1 1 B X _WR/AN6/RE1 26 200 -1700 200 L 40 40 1 1 B ENDDRAW ENDDEF #End Library