EESchema-LIBRARY Version 2.3  29/04/2008-12:24:03
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 3
#
# Dev Name: PSD813F1
# Package Name: S52
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PSD813F1 IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: PSD813
F0 "IC" -500 1425 50 H V R T
F1 "PSD813F1" 500 -1425 50 H V R T
F2 "st_psd813-S52" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 1400 500 1400
P 2 1 0 0 500 1400 500 -1400
P 2 1 0 0 500 -1400 -500 -1400
P 2 1 0 0 -500 -1400 -500 1400
X /RESET 48 -700 -1300 200 R 40 40 1 1 B I
X ADIO0 30 -700 1300 200 R 40 40 1 1 B 
X ADIO1 31 -700 1200 200 R 40 40 1 1 B 
X ADIO2 32 -700 1100 200 R 40 40 1 1 B 
X ADIO3 33 -700 1000 200 R 40 40 1 1 B 
X ADIO4 34 -700 900 200 R 40 40 1 1 B 
X ADIO5 35 -700 800 200 R 40 40 1 1 B 
X ADIO6 36 -700 700 200 R 40 40 1 1 B 
X ADIO7 37 -700 600 200 R 40 40 1 1 B 
X ADIO8 39 -700 400 200 R 40 40 1 1 B 
X ADIO9 40 -700 300 200 R 40 40 1 1 B 
X ADIO10 41 -700 200 200 R 40 40 1 1 B 
X ADIO11 42 -700 100 200 R 40 40 1 1 B 
X ADIO12 43 -700 0 200 R 40 40 1 1 B 
X ADIO13 44 -700 -100 200 R 40 40 1 1 B 
X ADIO14 45 -700 -200 200 R 40 40 1 1 B 
X ADIO15 46 -700 -300 200 R 40 40 1 1 B 
X CNTL0(/WR) 47 -700 -500 200 R 40 40 1 1 B 
X CNTL1(/RD) 50 -700 -600 200 R 40 40 1 1 B 
X CNTL2(/PSEN) 49 -700 -700 200 R 40 40 1 1 B 
X PA0 29 700 1300 200 L 40 40 1 1 B 
X PA1 28 700 1200 200 L 40 40 1 1 B 
X PA2 27 700 1100 200 L 40 40 1 1 B 
X PA3 25 700 1000 200 L 40 40 1 1 B 
X PA4 24 700 900 200 L 40 40 1 1 B 
X PA5 23 700 800 200 L 40 40 1 1 B 
X PA6 22 700 700 200 L 40 40 1 1 B 
X PA7 21 700 600 200 L 40 40 1 1 B 
X PB0 7 700 400 200 L 40 40 1 1 B 
X PB1 6 700 300 200 L 40 40 1 1 B 
X PB2 5 700 200 200 L 40 40 1 1 B 
X PB3 4 700 100 200 L 40 40 1 1 B 
X PB4 3 700 0 200 L 40 40 1 1 B 
X PB5 2 700 -100 200 L 40 40 1 1 B 
X PB6 52 700 -200 200 L 40 40 1 1 B 
X PB7 51 700 -300 200 L 40 40 1 1 B 
X PC0 20 700 -500 200 L 40 40 1 1 B 
X PC1 19 700 -600 200 L 40 40 1 1 B 
X PC2 18 700 -700 200 L 40 40 1 1 B 
X PC3 17 700 -800 200 L 40 40 1 1 B 
X PC4 14 700 -900 200 L 40 40 1 1 B 
X PC5 13 700 -1000 200 L 40 40 1 1 B 
X PC6 12 700 -1100 200 L 40 40 1 1 B 
X PC7 11 700 -1200 200 L 40 40 1 1 B 
X PD0(ALE) 10 -700 -900 200 R 40 40 1 1 B 
X PD1 9 -700 -1000 200 R 40 40 1 1 B 
X PD2 8 -700 -1100 200 R 40 40 1 1 B 
# Gate Name: P
# Symbol Name: PWR
T 1 -50 175 50 0 2 0 VCC
T 1 150 175 50 0 2 0 VCC
T 1 -150 -155 50 0 2 0 GND
T 1 50 -155 50 0 2 0 GND
T 1 250 -155 50 0 2 0 GND
X GND1 1 -200 -300 200 U 40 40 2 1 W 
X GND2 16 0 -300 200 U 40 40 2 1 W 
X GND3 26 200 -300 200 U 40 40 2 1 W 
X VCC1 15 -100 300 200 D 40 40 2 1 W 
X VCC2 38 100 300 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: PSD813F1J
# Package Name: PLCC52
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PSD813F1J IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: PSD813
F0 "IC" -500 1425 50 H V R T
F1 "PSD813F1J" 500 -1425 50 H V R T
F2 "st_psd813-PLCC52" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 1400 500 1400
P 2 1 0 0 500 1400 500 -1400
P 2 1 0 0 500 -1400 -500 -1400
P 2 1 0 0 -500 -1400 -500 1400
X /RESET 48 -700 -1300 200 R 40 40 1 1 B I
X ADIO0 30 -700 1300 200 R 40 40 1 1 B 
X ADIO1 31 -700 1200 200 R 40 40 1 1 B 
X ADIO2 32 -700 1100 200 R 40 40 1 1 B 
X ADIO3 33 -700 1000 200 R 40 40 1 1 B 
X ADIO4 34 -700 900 200 R 40 40 1 1 B 
X ADIO5 35 -700 800 200 R 40 40 1 1 B 
X ADIO6 36 -700 700 200 R 40 40 1 1 B 
X ADIO7 37 -700 600 200 R 40 40 1 1 B 
X ADIO8 39 -700 400 200 R 40 40 1 1 B 
X ADIO9 40 -700 300 200 R 40 40 1 1 B 
X ADIO10 41 -700 200 200 R 40 40 1 1 B 
X ADIO11 42 -700 100 200 R 40 40 1 1 B 
X ADIO12 43 -700 0 200 R 40 40 1 1 B 
X ADIO13 44 -700 -100 200 R 40 40 1 1 B 
X ADIO14 45 -700 -200 200 R 40 40 1 1 B 
X ADIO15 46 -700 -300 200 R 40 40 1 1 B 
X CNTL0(/WR) 47 -700 -500 200 R 40 40 1 1 B 
X CNTL1(/RD) 50 -700 -600 200 R 40 40 1 1 B 
X CNTL2(/PSEN) 49 -700 -700 200 R 40 40 1 1 B 
X PA0 29 700 1300 200 L 40 40 1 1 B 
X PA1 28 700 1200 200 L 40 40 1 1 B 
X PA2 27 700 1100 200 L 40 40 1 1 B 
X PA3 25 700 1000 200 L 40 40 1 1 B 
X PA4 24 700 900 200 L 40 40 1 1 B 
X PA5 23 700 800 200 L 40 40 1 1 B 
X PA6 22 700 700 200 L 40 40 1 1 B 
X PA7 21 700 600 200 L 40 40 1 1 B 
X PB0 7 700 400 200 L 40 40 1 1 B 
X PB1 6 700 300 200 L 40 40 1 1 B 
X PB2 5 700 200 200 L 40 40 1 1 B 
X PB3 4 700 100 200 L 40 40 1 1 B 
X PB4 3 700 0 200 L 40 40 1 1 B 
X PB5 2 700 -100 200 L 40 40 1 1 B 
X PB6 52 700 -200 200 L 40 40 1 1 B 
X PB7 51 700 -300 200 L 40 40 1 1 B 
X PC0 20 700 -500 200 L 40 40 1 1 B 
X PC1 19 700 -600 200 L 40 40 1 1 B 
X PC2 18 700 -700 200 L 40 40 1 1 B 
X PC3 17 700 -800 200 L 40 40 1 1 B 
X PC4 14 700 -900 200 L 40 40 1 1 B 
X PC5 13 700 -1000 200 L 40 40 1 1 B 
X PC6 12 700 -1100 200 L 40 40 1 1 B 
X PC7 11 700 -1200 200 L 40 40 1 1 B 
X PD0(ALE) 10 -700 -900 200 R 40 40 1 1 B 
X PD1 9 -700 -1000 200 R 40 40 1 1 B 
X PD2 8 -700 -1100 200 R 40 40 1 1 B 
# Gate Name: P
# Symbol Name: PWR
T 1 -50 175 50 0 2 0 VCC
T 1 150 175 50 0 2 0 VCC
T 1 -150 -155 50 0 2 0 GND
T 1 50 -155 50 0 2 0 GND
T 1 250 -155 50 0 2 0 GND
X GND1 1 -200 -300 200 U 40 40 2 1 W 
X GND2 16 0 -300 200 U 40 40 2 1 W 
X GND3 26 200 -300 200 U 40 40 2 1 W 
X VCC1 15 -100 300 200 D 40 40 2 1 W 
X VCC2 38 100 300 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: PSD813F1M
# Package Name: PGFP52
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 2
#
DEF PSD813F1M IC 0 40 Y Y 2 L N
# Gate Name: G$1
# Symbol Name: PSD813
F0 "IC" -500 1425 50 H V R T
F1 "PSD813F1M" 500 -1425 50 H V R T
F2 "st_psd813-PGFP52" 0 150 50 H I C C
DRAW
P 2 1 0 0 -500 1400 500 1400
P 2 1 0 0 500 1400 500 -1400
P 2 1 0 0 500 -1400 -500 -1400
P 2 1 0 0 -500 -1400 -500 1400
X /RESET 41 -700 -1300 200 R 40 40 1 1 B I
X ADIO0 23 -700 1300 200 R 40 40 1 1 B 
X ADIO1 24 -700 1200 200 R 40 40 1 1 B 
X ADIO2 25 -700 1100 200 R 40 40 1 1 B 
X ADIO3 26 -700 1000 200 R 40 40 1 1 B 
X ADIO4 27 -700 900 200 R 40 40 1 1 B 
X ADIO5 28 -700 800 200 R 40 40 1 1 B 
X ADIO6 29 -700 700 200 R 40 40 1 1 B 
X ADIO7 30 -700 600 200 R 40 40 1 1 B 
X ADIO8 32 -700 400 200 R 40 40 1 1 B 
X ADIO9 33 -700 300 200 R 40 40 1 1 B 
X ADIO10 34 -700 200 200 R 40 40 1 1 B 
X ADIO11 35 -700 100 200 R 40 40 1 1 B 
X ADIO12 36 -700 0 200 R 40 40 1 1 B 
X ADIO13 37 -700 -100 200 R 40 40 1 1 B 
X ADIO14 38 -700 -200 200 R 40 40 1 1 B 
X ADIO15 39 -700 -300 200 R 40 40 1 1 B 
X CNTL0(/WR) 40 -700 -500 200 R 40 40 1 1 B 
X CNTL1(/RD) 43 -700 -600 200 R 40 40 1 1 B 
X CNTL2(/PSEN) 42 -700 -700 200 R 40 40 1 1 B 
X PA0 22 700 1300 200 L 40 40 1 1 B 
X PA1 21 700 1200 200 L 40 40 1 1 B 
X PA2 20 700 1100 200 L 40 40 1 1 B 
X PA3 18 700 1000 200 L 40 40 1 1 B 
X PA4 17 700 900 200 L 40 40 1 1 B 
X PA5 16 700 800 200 L 40 40 1 1 B 
X PA6 15 700 700 200 L 40 40 1 1 B 
X PA7 14 700 600 200 L 40 40 1 1 B 
X PB0 52 700 400 200 L 40 40 1 1 B 
X PB1 51 700 300 200 L 40 40 1 1 B 
X PB2 50 700 200 200 L 40 40 1 1 B 
X PB3 49 700 100 200 L 40 40 1 1 B 
X PB4 48 700 0 200 L 40 40 1 1 B 
X PB5 47 700 -100 200 L 40 40 1 1 B 
X PB6 45 700 -200 200 L 40 40 1 1 B 
X PB7 44 700 -300 200 L 40 40 1 1 B 
X PC0 13 700 -500 200 L 40 40 1 1 B 
X PC1 12 700 -600 200 L 40 40 1 1 B 
X PC2 11 700 -700 200 L 40 40 1 1 B 
X PC3 10 700 -800 200 L 40 40 1 1 B 
X PC4 7 700 -900 200 L 40 40 1 1 B 
X PC5 6 700 -1000 200 L 40 40 1 1 B 
X PC6 5 700 -1100 200 L 40 40 1 1 B 
X PC7 4 700 -1200 200 L 40 40 1 1 B 
X PD0(ALE) 3 -700 -900 200 R 40 40 1 1 B 
X PD1 2 -700 -1000 200 R 40 40 1 1 B 
X PD2 1 -700 -1100 200 R 40 40 1 1 B 
# Gate Name: P
# Symbol Name: PWR
T 1 -50 175 50 0 2 0 VCC
T 1 150 175 50 0 2 0 VCC
T 1 -150 -155 50 0 2 0 GND
T 1 50 -155 50 0 2 0 GND
T 1 250 -155 50 0 2 0 GND
X GND1 9 -200 -300 200 U 40 40 2 1 W 
X GND2 19 0 -300 200 U 40 40 2 1 W 
X GND3 46 200 -300 200 U 40 40 2 1 W 
X VCC1 8 -100 300 200 D 40 40 2 1 W 
X VCC2 31 100 300 200 D 40 40 2 1 W 
ENDDRAW
ENDDEF

#End Library