EESchema-LIBRARY Version 2.3 29/04/2008-12:24:03 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 18 # # Dev Name: PSD813F1 # Package Name: S52 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF PSD813F1 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD813F1" 600 -1425 50 H V R T F2 "st_psd8xxfx-S52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD813F1J # Package Name: PLCC52 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF PSD813F1J IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD813F1J" 600 -1425 50 H V R T F2 "st_psd8xxfx-PLCC52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD813F1M # Package Name: PGFP52 # Dev Tech: '' # Dev Prefix: IC # Gate count = 2 # DEF PSD813F1M IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD813F1M" 600 -1425 50 H V R T F2 "st_psd8xxfx-PGFP52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 7 800 -900 200 L 40 40 1 1 B X (/TST)PC3 10 800 -800 200 L 40 40 1 1 B X (TCK)PC1 12 800 -600 200 L 40 40 1 1 B X (TDI)PC5 6 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 5 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 13 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 11 800 -700 200 L 40 40 1 1 B X /RESET 41 -800 -1300 200 R 40 40 1 1 B I X ADIO0 23 -800 1300 200 R 40 40 1 1 B X ADIO1 24 -800 1200 200 R 40 40 1 1 B X ADIO2 25 -800 1100 200 R 40 40 1 1 B X ADIO3 26 -800 1000 200 R 40 40 1 1 B X ADIO4 27 -800 900 200 R 40 40 1 1 B X ADIO5 28 -800 800 200 R 40 40 1 1 B X ADIO6 29 -800 700 200 R 40 40 1 1 B X ADIO7 30 -800 600 200 R 40 40 1 1 B X ADIO8 32 -800 400 200 R 40 40 1 1 B X ADIO9 33 -800 300 200 R 40 40 1 1 B X ADIO10 34 -800 200 200 R 40 40 1 1 B X ADIO11 35 -800 100 200 R 40 40 1 1 B X ADIO12 36 -800 0 200 R 40 40 1 1 B X ADIO13 37 -800 -100 200 R 40 40 1 1 B X ADIO14 38 -800 -200 200 R 40 40 1 1 B X ADIO15 39 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 40 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 43 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 42 -800 -700 200 R 40 40 1 1 B X PA0 22 800 1300 200 L 40 40 1 1 B X PA1 21 800 1200 200 L 40 40 1 1 B X PA2 20 800 1100 200 L 40 40 1 1 B X PA3 18 800 1000 200 L 40 40 1 1 B X PA4 17 800 900 200 L 40 40 1 1 B X PA5 16 800 800 200 L 40 40 1 1 B X PA6 15 800 700 200 L 40 40 1 1 B X PA7 14 800 600 200 L 40 40 1 1 B X PB0 52 800 400 200 L 40 40 1 1 B X PB1 51 800 300 200 L 40 40 1 1 B X PB2 50 800 200 200 L 40 40 1 1 B X PB3 49 800 100 200 L 40 40 1 1 B X PB4 48 800 0 200 L 40 40 1 1 B X PB5 47 800 -100 200 L 40 40 1 1 B X PB6 45 800 -200 200 L 40 40 1 1 B X PB7 44 800 -300 200 L 40 40 1 1 B X PC7 4 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 3 -800 -900 200 R 40 40 1 1 B X PD1 2 -800 -1000 200 R 40 40 1 1 B X PD2 1 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 9 -100 -300 200 U 40 40 2 1 W X GND2 19 0 -300 200 U 40 40 2 1 W X GND3 46 100 -300 200 U 40 40 2 1 W X VCC1 8 -100 300 200 D 40 40 2 1 W X VCC2 31 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD813F2 # Package Name: S52 # Dev Tech: 13 # Dev Prefix: IC # Gate count = 2 # DEF PSD813F2 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD813F2" 600 -1425 50 H V R T F2 "st_psd8xxfx-S52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD813F2J # Package Name: PLCC52 # Dev Tech: 13 # Dev Prefix: IC # Gate count = 2 # DEF PSD813F2J IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD813F2J" 600 -1425 50 H V R T F2 "st_psd8xxfx-PLCC52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD813F2M # Package Name: PGFP52 # Dev Tech: 13 # Dev Prefix: IC # Gate count = 2 # DEF PSD813F2M IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD813F2M" 600 -1425 50 H V R T F2 "st_psd8xxfx-PGFP52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 7 800 -900 200 L 40 40 1 1 B X (/TST)PC3 10 800 -800 200 L 40 40 1 1 B X (TCK)PC1 12 800 -600 200 L 40 40 1 1 B X (TDI)PC5 6 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 5 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 13 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 11 800 -700 200 L 40 40 1 1 B X /RESET 41 -800 -1300 200 R 40 40 1 1 B I X ADIO0 23 -800 1300 200 R 40 40 1 1 B X ADIO1 24 -800 1200 200 R 40 40 1 1 B X ADIO2 25 -800 1100 200 R 40 40 1 1 B X ADIO3 26 -800 1000 200 R 40 40 1 1 B X ADIO4 27 -800 900 200 R 40 40 1 1 B X ADIO5 28 -800 800 200 R 40 40 1 1 B X ADIO6 29 -800 700 200 R 40 40 1 1 B X ADIO7 30 -800 600 200 R 40 40 1 1 B X ADIO8 32 -800 400 200 R 40 40 1 1 B X ADIO9 33 -800 300 200 R 40 40 1 1 B X ADIO10 34 -800 200 200 R 40 40 1 1 B X ADIO11 35 -800 100 200 R 40 40 1 1 B X ADIO12 36 -800 0 200 R 40 40 1 1 B X ADIO13 37 -800 -100 200 R 40 40 1 1 B X ADIO14 38 -800 -200 200 R 40 40 1 1 B X ADIO15 39 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 40 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 43 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 42 -800 -700 200 R 40 40 1 1 B X PA0 22 800 1300 200 L 40 40 1 1 B X PA1 21 800 1200 200 L 40 40 1 1 B X PA2 20 800 1100 200 L 40 40 1 1 B X PA3 18 800 1000 200 L 40 40 1 1 B X PA4 17 800 900 200 L 40 40 1 1 B X PA5 16 800 800 200 L 40 40 1 1 B X PA6 15 800 700 200 L 40 40 1 1 B X PA7 14 800 600 200 L 40 40 1 1 B X PB0 52 800 400 200 L 40 40 1 1 B X PB1 51 800 300 200 L 40 40 1 1 B X PB2 50 800 200 200 L 40 40 1 1 B X PB3 49 800 100 200 L 40 40 1 1 B X PB4 48 800 0 200 L 40 40 1 1 B X PB5 47 800 -100 200 L 40 40 1 1 B X PB6 45 800 -200 200 L 40 40 1 1 B X PB7 44 800 -300 200 L 40 40 1 1 B X PC7 4 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 3 -800 -900 200 R 40 40 1 1 B X PD1 2 -800 -1000 200 R 40 40 1 1 B X PD2 1 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 9 -100 -300 200 U 40 40 2 1 W X GND2 19 0 -300 200 U 40 40 2 1 W X GND3 46 100 -300 200 U 40 40 2 1 W X VCC1 8 -100 300 200 D 40 40 2 1 W X VCC2 31 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD833F2 # Package Name: S52 # Dev Tech: 33 # Dev Prefix: IC # Gate count = 2 # DEF PSD833F2 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD833F2" 600 -1425 50 H V R T F2 "st_psd8xxfx-S52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD833F2J # Package Name: PLCC52 # Dev Tech: 33 # Dev Prefix: IC # Gate count = 2 # DEF PSD833F2J IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD833F2J" 600 -1425 50 H V R T F2 "st_psd8xxfx-PLCC52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD833F2M # Package Name: PGFP52 # Dev Tech: 33 # Dev Prefix: IC # Gate count = 2 # DEF PSD833F2M IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD833F2M" 600 -1425 50 H V R T F2 "st_psd8xxfx-PGFP52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 7 800 -900 200 L 40 40 1 1 B X (/TST)PC3 10 800 -800 200 L 40 40 1 1 B X (TCK)PC1 12 800 -600 200 L 40 40 1 1 B X (TDI)PC5 6 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 5 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 13 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 11 800 -700 200 L 40 40 1 1 B X /RESET 41 -800 -1300 200 R 40 40 1 1 B I X ADIO0 23 -800 1300 200 R 40 40 1 1 B X ADIO1 24 -800 1200 200 R 40 40 1 1 B X ADIO2 25 -800 1100 200 R 40 40 1 1 B X ADIO3 26 -800 1000 200 R 40 40 1 1 B X ADIO4 27 -800 900 200 R 40 40 1 1 B X ADIO5 28 -800 800 200 R 40 40 1 1 B X ADIO6 29 -800 700 200 R 40 40 1 1 B X ADIO7 30 -800 600 200 R 40 40 1 1 B X ADIO8 32 -800 400 200 R 40 40 1 1 B X ADIO9 33 -800 300 200 R 40 40 1 1 B X ADIO10 34 -800 200 200 R 40 40 1 1 B X ADIO11 35 -800 100 200 R 40 40 1 1 B X ADIO12 36 -800 0 200 R 40 40 1 1 B X ADIO13 37 -800 -100 200 R 40 40 1 1 B X ADIO14 38 -800 -200 200 R 40 40 1 1 B X ADIO15 39 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 40 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 43 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 42 -800 -700 200 R 40 40 1 1 B X PA0 22 800 1300 200 L 40 40 1 1 B X PA1 21 800 1200 200 L 40 40 1 1 B X PA2 20 800 1100 200 L 40 40 1 1 B X PA3 18 800 1000 200 L 40 40 1 1 B X PA4 17 800 900 200 L 40 40 1 1 B X PA5 16 800 800 200 L 40 40 1 1 B X PA6 15 800 700 200 L 40 40 1 1 B X PA7 14 800 600 200 L 40 40 1 1 B X PB0 52 800 400 200 L 40 40 1 1 B X PB1 51 800 300 200 L 40 40 1 1 B X PB2 50 800 200 200 L 40 40 1 1 B X PB3 49 800 100 200 L 40 40 1 1 B X PB4 48 800 0 200 L 40 40 1 1 B X PB5 47 800 -100 200 L 40 40 1 1 B X PB6 45 800 -200 200 L 40 40 1 1 B X PB7 44 800 -300 200 L 40 40 1 1 B X PC7 4 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 3 -800 -900 200 R 40 40 1 1 B X PD1 2 -800 -1000 200 R 40 40 1 1 B X PD2 1 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 9 -100 -300 200 U 40 40 2 1 W X GND2 19 0 -300 200 U 40 40 2 1 W X GND3 46 100 -300 200 U 40 40 2 1 W X VCC1 8 -100 300 200 D 40 40 2 1 W X VCC2 31 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD834F2 # Package Name: S52 # Dev Tech: 34 # Dev Prefix: IC # Gate count = 2 # DEF PSD834F2 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD834F2" 600 -1425 50 H V R T F2 "st_psd8xxfx-S52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD834F2J # Package Name: PLCC52 # Dev Tech: 34 # Dev Prefix: IC # Gate count = 2 # DEF PSD834F2J IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD834F2J" 600 -1425 50 H V R T F2 "st_psd8xxfx-PLCC52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD834F2M # Package Name: PGFP52 # Dev Tech: 34 # Dev Prefix: IC # Gate count = 2 # DEF PSD834F2M IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD834F2M" 600 -1425 50 H V R T F2 "st_psd8xxfx-PGFP52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 7 800 -900 200 L 40 40 1 1 B X (/TST)PC3 10 800 -800 200 L 40 40 1 1 B X (TCK)PC1 12 800 -600 200 L 40 40 1 1 B X (TDI)PC5 6 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 5 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 13 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 11 800 -700 200 L 40 40 1 1 B X /RESET 41 -800 -1300 200 R 40 40 1 1 B I X ADIO0 23 -800 1300 200 R 40 40 1 1 B X ADIO1 24 -800 1200 200 R 40 40 1 1 B X ADIO2 25 -800 1100 200 R 40 40 1 1 B X ADIO3 26 -800 1000 200 R 40 40 1 1 B X ADIO4 27 -800 900 200 R 40 40 1 1 B X ADIO5 28 -800 800 200 R 40 40 1 1 B X ADIO6 29 -800 700 200 R 40 40 1 1 B X ADIO7 30 -800 600 200 R 40 40 1 1 B X ADIO8 32 -800 400 200 R 40 40 1 1 B X ADIO9 33 -800 300 200 R 40 40 1 1 B X ADIO10 34 -800 200 200 R 40 40 1 1 B X ADIO11 35 -800 100 200 R 40 40 1 1 B X ADIO12 36 -800 0 200 R 40 40 1 1 B X ADIO13 37 -800 -100 200 R 40 40 1 1 B X ADIO14 38 -800 -200 200 R 40 40 1 1 B X ADIO15 39 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 40 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 43 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 42 -800 -700 200 R 40 40 1 1 B X PA0 22 800 1300 200 L 40 40 1 1 B X PA1 21 800 1200 200 L 40 40 1 1 B X PA2 20 800 1100 200 L 40 40 1 1 B X PA3 18 800 1000 200 L 40 40 1 1 B X PA4 17 800 900 200 L 40 40 1 1 B X PA5 16 800 800 200 L 40 40 1 1 B X PA6 15 800 700 200 L 40 40 1 1 B X PA7 14 800 600 200 L 40 40 1 1 B X PB0 52 800 400 200 L 40 40 1 1 B X PB1 51 800 300 200 L 40 40 1 1 B X PB2 50 800 200 200 L 40 40 1 1 B X PB3 49 800 100 200 L 40 40 1 1 B X PB4 48 800 0 200 L 40 40 1 1 B X PB5 47 800 -100 200 L 40 40 1 1 B X PB6 45 800 -200 200 L 40 40 1 1 B X PB7 44 800 -300 200 L 40 40 1 1 B X PC7 4 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 3 -800 -900 200 R 40 40 1 1 B X PD1 2 -800 -1000 200 R 40 40 1 1 B X PD2 1 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 9 -100 -300 200 U 40 40 2 1 W X GND2 19 0 -300 200 U 40 40 2 1 W X GND3 46 100 -300 200 U 40 40 2 1 W X VCC1 8 -100 300 200 D 40 40 2 1 W X VCC2 31 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD853F2 # Package Name: S52 # Dev Tech: 53 # Dev Prefix: IC # Gate count = 2 # DEF PSD853F2 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD853F2" 600 -1425 50 H V R T F2 "st_psd8xxfx-S52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD853F2J # Package Name: PLCC52 # Dev Tech: 53 # Dev Prefix: IC # Gate count = 2 # DEF PSD853F2J IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD853F2J" 600 -1425 50 H V R T F2 "st_psd8xxfx-PLCC52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD853F2M # Package Name: PGFP52 # Dev Tech: 53 # Dev Prefix: IC # Gate count = 2 # DEF PSD853F2M IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD853F2M" 600 -1425 50 H V R T F2 "st_psd8xxfx-PGFP52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 7 800 -900 200 L 40 40 1 1 B X (/TST)PC3 10 800 -800 200 L 40 40 1 1 B X (TCK)PC1 12 800 -600 200 L 40 40 1 1 B X (TDI)PC5 6 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 5 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 13 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 11 800 -700 200 L 40 40 1 1 B X /RESET 41 -800 -1300 200 R 40 40 1 1 B I X ADIO0 23 -800 1300 200 R 40 40 1 1 B X ADIO1 24 -800 1200 200 R 40 40 1 1 B X ADIO2 25 -800 1100 200 R 40 40 1 1 B X ADIO3 26 -800 1000 200 R 40 40 1 1 B X ADIO4 27 -800 900 200 R 40 40 1 1 B X ADIO5 28 -800 800 200 R 40 40 1 1 B X ADIO6 29 -800 700 200 R 40 40 1 1 B X ADIO7 30 -800 600 200 R 40 40 1 1 B X ADIO8 32 -800 400 200 R 40 40 1 1 B X ADIO9 33 -800 300 200 R 40 40 1 1 B X ADIO10 34 -800 200 200 R 40 40 1 1 B X ADIO11 35 -800 100 200 R 40 40 1 1 B X ADIO12 36 -800 0 200 R 40 40 1 1 B X ADIO13 37 -800 -100 200 R 40 40 1 1 B X ADIO14 38 -800 -200 200 R 40 40 1 1 B X ADIO15 39 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 40 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 43 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 42 -800 -700 200 R 40 40 1 1 B X PA0 22 800 1300 200 L 40 40 1 1 B X PA1 21 800 1200 200 L 40 40 1 1 B X PA2 20 800 1100 200 L 40 40 1 1 B X PA3 18 800 1000 200 L 40 40 1 1 B X PA4 17 800 900 200 L 40 40 1 1 B X PA5 16 800 800 200 L 40 40 1 1 B X PA6 15 800 700 200 L 40 40 1 1 B X PA7 14 800 600 200 L 40 40 1 1 B X PB0 52 800 400 200 L 40 40 1 1 B X PB1 51 800 300 200 L 40 40 1 1 B X PB2 50 800 200 200 L 40 40 1 1 B X PB3 49 800 100 200 L 40 40 1 1 B X PB4 48 800 0 200 L 40 40 1 1 B X PB5 47 800 -100 200 L 40 40 1 1 B X PB6 45 800 -200 200 L 40 40 1 1 B X PB7 44 800 -300 200 L 40 40 1 1 B X PC7 4 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 3 -800 -900 200 R 40 40 1 1 B X PD1 2 -800 -1000 200 R 40 40 1 1 B X PD2 1 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 9 -100 -300 200 U 40 40 2 1 W X GND2 19 0 -300 200 U 40 40 2 1 W X GND3 46 100 -300 200 U 40 40 2 1 W X VCC1 8 -100 300 200 D 40 40 2 1 W X VCC2 31 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD854F2 # Package Name: S52 # Dev Tech: 54 # Dev Prefix: IC # Gate count = 2 # DEF PSD854F2 IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD854F2" 600 -1425 50 H V R T F2 "st_psd8xxfx-S52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD854F2J # Package Name: PLCC52 # Dev Tech: 54 # Dev Prefix: IC # Gate count = 2 # DEF PSD854F2J IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD854F2J" 600 -1425 50 H V R T F2 "st_psd8xxfx-PLCC52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 14 800 -900 200 L 40 40 1 1 B X (/TST)PC3 17 800 -800 200 L 40 40 1 1 B X (TCK)PC1 19 800 -600 200 L 40 40 1 1 B X (TDI)PC5 13 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 12 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 20 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 18 800 -700 200 L 40 40 1 1 B X /RESET 48 -800 -1300 200 R 40 40 1 1 B I X ADIO0 30 -800 1300 200 R 40 40 1 1 B X ADIO1 31 -800 1200 200 R 40 40 1 1 B X ADIO2 32 -800 1100 200 R 40 40 1 1 B X ADIO3 33 -800 1000 200 R 40 40 1 1 B X ADIO4 34 -800 900 200 R 40 40 1 1 B X ADIO5 35 -800 800 200 R 40 40 1 1 B X ADIO6 36 -800 700 200 R 40 40 1 1 B X ADIO7 37 -800 600 200 R 40 40 1 1 B X ADIO8 39 -800 400 200 R 40 40 1 1 B X ADIO9 40 -800 300 200 R 40 40 1 1 B X ADIO10 41 -800 200 200 R 40 40 1 1 B X ADIO11 42 -800 100 200 R 40 40 1 1 B X ADIO12 43 -800 0 200 R 40 40 1 1 B X ADIO13 44 -800 -100 200 R 40 40 1 1 B X ADIO14 45 -800 -200 200 R 40 40 1 1 B X ADIO15 46 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 47 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 50 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 49 -800 -700 200 R 40 40 1 1 B X PA0 29 800 1300 200 L 40 40 1 1 B X PA1 28 800 1200 200 L 40 40 1 1 B X PA2 27 800 1100 200 L 40 40 1 1 B X PA3 25 800 1000 200 L 40 40 1 1 B X PA4 24 800 900 200 L 40 40 1 1 B X PA5 23 800 800 200 L 40 40 1 1 B X PA6 22 800 700 200 L 40 40 1 1 B X PA7 21 800 600 200 L 40 40 1 1 B X PB0 7 800 400 200 L 40 40 1 1 B X PB1 6 800 300 200 L 40 40 1 1 B X PB2 5 800 200 200 L 40 40 1 1 B X PB3 4 800 100 200 L 40 40 1 1 B X PB4 3 800 0 200 L 40 40 1 1 B X PB5 2 800 -100 200 L 40 40 1 1 B X PB6 52 800 -200 200 L 40 40 1 1 B X PB7 51 800 -300 200 L 40 40 1 1 B X PC7 11 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 10 -800 -900 200 R 40 40 1 1 B X PD1 9 -800 -1000 200 R 40 40 1 1 B X PD2 8 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 1 -100 -300 200 U 40 40 2 1 W X GND2 16 0 -300 200 U 40 40 2 1 W X GND3 26 100 -300 200 U 40 40 2 1 W X VCC1 15 -100 300 200 D 40 40 2 1 W X VCC2 38 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: PSD854F2M # Package Name: PGFP52 # Dev Tech: 54 # Dev Prefix: IC # Gate count = 2 # DEF PSD854F2M IC 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: PSD813 F0 "IC" -600 1425 50 H V R T F1 "PSD854F2M" 600 -1425 50 H V R T F2 "st_psd8xxfx-PGFP52" 0 150 50 H I C C DRAW P 2 1 0 0 -600 1400 600 1400 P 2 1 0 0 600 1400 600 -1400 P 2 1 0 0 600 -1400 -600 -1400 P 2 1 0 0 -600 -1400 -600 1400 X (/TER)PC4 7 800 -900 200 L 40 40 1 1 B X (/TST)PC3 10 800 -800 200 L 40 40 1 1 B X (TCK)PC1 12 800 -600 200 L 40 40 1 1 B X (TDI)PC5 6 800 -1000 200 L 40 40 1 1 B X (TDO)PC6 5 800 -1100 200 L 40 40 1 1 B X (TMS)PC0 13 800 -500 200 L 40 40 1 1 B X (VSTB)PC2 11 800 -700 200 L 40 40 1 1 B X /RESET 41 -800 -1300 200 R 40 40 1 1 B I X ADIO0 23 -800 1300 200 R 40 40 1 1 B X ADIO1 24 -800 1200 200 R 40 40 1 1 B X ADIO2 25 -800 1100 200 R 40 40 1 1 B X ADIO3 26 -800 1000 200 R 40 40 1 1 B X ADIO4 27 -800 900 200 R 40 40 1 1 B X ADIO5 28 -800 800 200 R 40 40 1 1 B X ADIO6 29 -800 700 200 R 40 40 1 1 B X ADIO7 30 -800 600 200 R 40 40 1 1 B X ADIO8 32 -800 400 200 R 40 40 1 1 B X ADIO9 33 -800 300 200 R 40 40 1 1 B X ADIO10 34 -800 200 200 R 40 40 1 1 B X ADIO11 35 -800 100 200 R 40 40 1 1 B X ADIO12 36 -800 0 200 R 40 40 1 1 B X ADIO13 37 -800 -100 200 R 40 40 1 1 B X ADIO14 38 -800 -200 200 R 40 40 1 1 B X ADIO15 39 -800 -300 200 R 40 40 1 1 B X CNTL0(/WR) 40 -800 -500 200 R 40 40 1 1 B X CNTL1(/RD) 43 -800 -600 200 R 40 40 1 1 B X CNTL2(/PSEN) 42 -800 -700 200 R 40 40 1 1 B X PA0 22 800 1300 200 L 40 40 1 1 B X PA1 21 800 1200 200 L 40 40 1 1 B X PA2 20 800 1100 200 L 40 40 1 1 B X PA3 18 800 1000 200 L 40 40 1 1 B X PA4 17 800 900 200 L 40 40 1 1 B X PA5 16 800 800 200 L 40 40 1 1 B X PA6 15 800 700 200 L 40 40 1 1 B X PA7 14 800 600 200 L 40 40 1 1 B X PB0 52 800 400 200 L 40 40 1 1 B X PB1 51 800 300 200 L 40 40 1 1 B X PB2 50 800 200 200 L 40 40 1 1 B X PB3 49 800 100 200 L 40 40 1 1 B X PB4 48 800 0 200 L 40 40 1 1 B X PB5 47 800 -100 200 L 40 40 1 1 B X PB6 45 800 -200 200 L 40 40 1 1 B X PB7 44 800 -300 200 L 40 40 1 1 B X PC7 4 800 -1200 200 L 40 40 1 1 B X PD0(ALE) 3 -800 -900 200 R 40 40 1 1 B X PD1 2 -800 -1000 200 R 40 40 1 1 B X PD2 1 -800 -1100 200 R 40 40 1 1 B # Gate Name: P # Symbol Name: PWR-2-3 T 1 50 175 50 0 2 0 VCC T 1 150 -175 50 0 2 0 GND X GND1 9 -100 -300 200 U 40 40 2 1 W X GND2 19 0 -300 200 U 40 40 2 1 W X GND3 46 100 -300 200 U 40 40 2 1 W X VCC1 8 -100 300 200 D 40 40 2 1 W X VCC2 31 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF #End Library