EESchema-LIBRARY Version 2.3  29/04/2008-12:24:08
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 94
#
# Dev Name: 2N3055
# Package Name: TO3A
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF 2N3055 Q 0 40 Y Y 1 L N
# Gate Name: A
# Symbol Name: NPN2
F0 "Q" 200 100 50 H V L B
F1 "2N3055" 200 0 50 H V L B
F2 "transistor-power-TO3A" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C1 100 200 100 D 40 40 1 1 P 
X C@1 C 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BD139
# Package Name: TO126AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BD139 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: NPN
F0 "Q" 200 100 50 H V L B
F1 "BD139" 200 0 50 H V L B
F2 "transistor-power-TO126AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 65 -65
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 65 -65
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BD140
# Package Name: TO126AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BD140 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: PNP
F0 "Q" 200 100 50 H V L B
F1 "BD140" 200 0 50 H V L B
F2 "transistor-power-TO126AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BD437
# Package Name: TO126AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BD437 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: NPN
F0 "Q" 200 100 50 H V L B
F1 "BD437" 200 0 50 H V L B
F2 "transistor-power-TO126AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 65 -65
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 65 -65
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BD438
# Package Name: TO126AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BD438 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: PNP
F0 "Q" 200 100 50 H V L B
F1 "BD438" 200 0 50 H V L B
F2 "transistor-power-TO126AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BD679
# Package Name: TO126AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BD679 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: N-DAR
F0 "Q" 200 100 50 H V L B
F1 "BD679" 200 0 50 H V L B
F2 "transistor-power-TO126AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 80 -80
P 2 1 0 0 80 -80 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 100 125 0 25
P 2 1 0 0 50 -70 70 -50
P 2 1 0 0 70 -50 80 -80
P 2 1 0 0 80 -80 60 -70
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BD680
# Package Name: TO126AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BD680 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: P-DAR
F0 "Q" 200 100 50 H V L B
F1 "BD680" 200 0 50 H V L B
F2 "transistor-power-TO126AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 50 50
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 100 -125 0 -25
P 2 1 0 0 50 50 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 50 50
P 2 1 0 0 50 50 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BD680L
# Package Name: TO126AH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BD680L Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: P-DAR
F0 "Q" 200 100 50 H V L B
F1 "BD680L" 200 0 50 H V L B
F2 "transistor-power-TO126AH" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 50 50
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 100 -125 0 -25
P 2 1 0 0 50 50 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 50 50
P 2 1 0 0 50 50 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BDX63
# Package Name: TO3A
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BDX63 Q 0 40 Y Y 1 L N
# Gate Name: A
# Symbol Name: N-DAR2
F0 "Q" 200 100 50 H V L B
F1 "BDX63" 200 0 50 H V L B
F2 "transistor-power-TO3A" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 100 125 0 25
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C1 100 200 100 D 40 40 1 1 P 
X C@1 C 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BDX64
# Package Name: TO3A
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BDX64 Q 0 40 Y Y 1 L N
# Gate Name: A
# Symbol Name: P-DAR2
F0 "Q" 200 100 50 H V L B
F1 "BDX64" 200 0 50 H V L B
F2 "transistor-power-TO3A" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 70 70 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 100 -125 0 -25
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 70 70
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C1 100 -200 100 U 40 40 1 1 P 
X C@1 C 100 -100 0 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BF871
# Package Name: TO202AH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BF871 Q 0 40 Y Y 1 L N
# Gate Name: P
# Symbol Name: NPN
F0 "Q" 200 100 50 H V L B
F1 "BF871" 200 0 50 H V L B
F2 "transistor-power-TO202AH" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 65 -65
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 65 -65
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B 1 -100 0 100 R 40 40 1 1 P 
X C 2 100 200 100 D 40 40 1 1 P 
X E 3 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BF872
# Package Name: TO202AH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BF872 Q 0 40 Y Y 1 L N
# Gate Name: P
# Symbol Name: PNP
F0 "Q" 200 100 50 H V L B
F1 "BF872" 200 0 50 H V L B
F2 "transistor-power-TO202AH" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B 3 -100 0 100 R 40 40 1 1 P 
X C 2 100 -200 100 U 40 40 1 1 P 
X E 1 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BU208
# Package Name: TO3A
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BU208 Q 0 40 Y Y 1 L N
# Gate Name: A
# Symbol Name: NPN2
F0 "Q" 200 100 50 H V L B
F1 "BU208" 200 0 50 H V L B
F2 "transistor-power-TO3A" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C1 100 200 100 D 40 40 1 1 P 
X C@1 C 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BUZ11BH
# Package Name: TO220BH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BUZ11BH Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: MFN
F0 "Q" 200 100 50 H V L B
F1 "BUZ11BH" 200 0 50 H V L B
F2 "transistor-power-TO220BH" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: BUZ11BV
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF BUZ11BV Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: MFN
F0 "Q" 200 100 50 H V L B
F1 "BUZ11BV" 200 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE150-102N02A
# Package Name: DE275
# Dev Tech: 150-102N02A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE150-102N02A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE150-102N02A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE150-201N09A
# Package Name: DE275
# Dev Tech: 150-201N09A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE150-201N09A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE150-201N09A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE150-501N04A
# Package Name: DE275
# Dev Tech: 150-501N04A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE150-501N04A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE150-501N04A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE275-101N30
# Package Name: DE275
# Dev Tech: 275-101N30
# Dev Prefix: Q
# Gate count = 1
#
DEF DE275-101N30 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE275-101N30" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE275-102N06A
# Package Name: DE275
# Dev Tech: 275-102N06A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE275-102N06A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE275-102N06A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE275-201N25A
# Package Name: DE275
# Dev Tech: 275-201N25A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE275-201N25A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE275-201N25A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE275-501N16A
# Package Name: DE275
# Dev Tech: 275-501N16A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE275-501N16A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE275-501N16A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE275X2-102N06A
# Package Name: DE_X
# Dev Tech: 2-102N06A
# Dev Prefix: Q
# Gate count = 2
#
DEF DE275X2-102N06A Q 0 40 Y Y 2 L N
# Gate Name: A
# Symbol Name: DE_2-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE275X2-102N06A" 200 -50 50 H V L B
F2 "transistor-power-DE_X" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 0 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 0 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D1 100 200 100 D 40 40 1 1 P 
X G G1 -200 -100 100 R 40 40 1 1 P 
X SD SD1 100 -300 100 U 40 40 1 1 P 
X SG SG1 0 -300 100 U 40 40 1 1 P 
# Gate Name: B
# Symbol Name: DE_2-MOSFET
P 6 2 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 2 0 0 -44 95 -44 -100
P 2 2 0 0 -44 -100 -100 -100
P 2 2 0 0 100 75 11 75
P 2 2 0 0 100 0 100 -75
P 2 2 0 0 10 -75 100 -75
P 2 2 0 0 100 100 100 75
P 2 2 0 0 100 -75 100 -150
P 2 2 0 0 65 0 100 0
P 2 2 0 0 0 -150 100 -150
P 2 2 0 0 100 -200 100 -150
P 2 2 0 0 0 -200 0 -150
S -10 -100 10 -50 2 1 0 F
S -10 50 10 100 2 1 0 F
S -10 -35 10 35 2 1 0 F
T 0 66 116 32 0 2 0 D
T 0 66 -109 32 0 2 0 S
T 0 -84 -34 32 0 2 0 G
X D D2 100 200 100 D 40 40 2 1 P 
X G G2 -200 -100 100 R 40 40 2 1 P 
X SD SD2 100 -300 100 U 40 40 2 1 P 
X SG SG2 0 -300 100 U 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE275X2-501N16A
# Package Name: DE_X
# Dev Tech: 2-501N16A
# Dev Prefix: Q
# Gate count = 2
#
DEF DE275X2-501N16A Q 0 40 Y Y 2 L N
# Gate Name: A
# Symbol Name: DE_2-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE275X2-501N16A" 200 -50 50 H V L B
F2 "transistor-power-DE_X" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 0 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 0 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D1 100 200 100 D 40 40 1 1 P 
X G G1 -200 -100 100 R 40 40 1 1 P 
X SD SD1 100 -300 100 U 40 40 1 1 P 
X SG SG1 0 -300 100 U 40 40 1 1 P 
# Gate Name: B
# Symbol Name: DE_2-MOSFET
P 6 2 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 2 0 0 -44 95 -44 -100
P 2 2 0 0 -44 -100 -100 -100
P 2 2 0 0 100 75 11 75
P 2 2 0 0 100 0 100 -75
P 2 2 0 0 10 -75 100 -75
P 2 2 0 0 100 100 100 75
P 2 2 0 0 100 -75 100 -150
P 2 2 0 0 65 0 100 0
P 2 2 0 0 0 -150 100 -150
P 2 2 0 0 100 -200 100 -150
P 2 2 0 0 0 -200 0 -150
S -10 -100 10 -50 2 1 0 F
S -10 50 10 100 2 1 0 F
S -10 -35 10 35 2 1 0 F
T 0 66 116 32 0 2 0 D
T 0 66 -109 32 0 2 0 S
T 0 -84 -34 32 0 2 0 G
X D D2 100 200 100 D 40 40 2 1 P 
X G G2 -200 -100 100 R 40 40 2 1 P 
X SD SD2 100 -300 100 U 40 40 2 1 P 
X SG SG2 0 -300 100 U 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE375-102N10A
# Package Name: DE275
# Dev Tech: 375-102N10A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE375-102N10A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE375-102N10A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE375-102N12A
# Package Name: DE275
# Dev Tech: 375-102N12A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE375-102N12A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE375-102N12A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE375-501N21A
# Package Name: DE275
# Dev Tech: 375-501N21A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE375-501N21A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE375-501N21A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE475-102N20A
# Package Name: DE275
# Dev Tech: 475-102N20A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE475-102N20A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE475-102N20A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE475-501N16A
# Package Name: DE275
# Dev Tech: 475-501N16A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE475-501N16A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE475-501N16A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: DE475-501N44A
# Package Name: DE275
# Dev Tech: 475-501N44A
# Dev Prefix: Q
# Gate count = 1
#
DEF DE475-501N44A Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: DE-MOSFET
F0 "Q" 200 100 50 H V L B
F1 "DE475-501N44A" 200 -50 50 H V L B
F2 "transistor-power-DE275" 0 150 50 H I C C
DRAW
P 6 1 1 0     10 0 70 20 70 20 70 -20 70 -20 10 0 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 11 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 10 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 -75 100 -150
P 2 1 0 0 65 0 100 0
P 2 1 0 0 -100 -150 100 -150
P 2 1 0 0 300 -150 100 -150
P 2 1 0 0 100 -200 100 -150
P 2 1 0 0 0 -200 100 -200
P 2 1 0 0 200 -200 100 -200
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 300 -200 300 -150
S -10 -100 10 -50 1 1 0 F
S -10 50 10 100 1 1 0 F
S -10 -35 10 35 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -200 -100 100 R 40 40 1 1 P 
X SD1 SD1 200 -300 100 U 40 40 1 1 P 
X SD2 SD2 300 -300 100 U 40 40 1 1 P 
X SG1 SG1 -100 -300 100 U 40 40 1 1 P 
X SG2 SG2 0 -300 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRF512
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRF512 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: MFN
F0 "Q" 200 100 50 H V L B
F1 "IRF512" 200 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRF520
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRF520 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IRF520" 300 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRF530
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRF530 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IRF530" 300 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRF540
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRF540 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IRF540" 300 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRF740
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRF740 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IRF740" 300 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRF6648
# Package Name: DIRECTFET
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRF6648 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFN-S2-D4
F0 "Q" 300 100 50 H V L B
F1 "IRF6648" 300 0 50 H V L B
F2 "transistor-power-DIRECTFET" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
X D D@1 100 300 100 D 40 40 1 1 P 
X D@1 D@2 100 250 100 D 40 40 1 1 P 
X D@2 D@3 100 200 100 D 40 40 1 1 P 
X D@3 D@4 100 150 100 U 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S@1 100 -200 100 U 40 40 1 1 P 
X S@1 S@2 100 -150 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRF9530
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRF9530 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFPD
F0 "Q" 200 100 50 H V L B
F1 "IRF9530" 200 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 150 75 100 75
P 2 1 0 0 150 75 150 30
P 2 1 0 0 150 30 150 -75
P 2 1 0 0 150 30 175 -25
P 2 1 0 0 175 -25 125 -25
P 2 1 0 0 125 -25 150 30
P 2 1 0 0 175 30 150 30
P 2 1 0 0 150 30 125 30
P 2 1 0 0 125 30 115 40
P 2 1 0 0 175 30 185 20
P 2 1 0 0 -40 100 -40 -100
P 2 1 0 0 150 -75 100 -75
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 100 -100 100 -75
P 2 1 0 0 88 0 90 0
P 2 1 0 0 90 0 100 0
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 20 75
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 90 0 40 -20
P 2 1 0 0 40 -20 40 20
P 2 1 0 0 40 20 90 0
P 2 1 0 0 45 0 10 0
P 2 1 0 0 45 10 80 0
P 2 1 0 0 80 0 45 -10
P 2 1 0 0 45 -10 45 0
P 2 1 0 0 45 0 55 0
P 2 1 0 0 100 0 100 75
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 76 -114 32 0 1 0 D
T 0 76 116 32 0 1 0 S
T 0 -74 66 32 0 1 0 G
X D D 100 -200 100 U 40 40 1 1 P 
X G G -200 100 100 R 40 40 1 1 P 
X S S 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRFP240
# Package Name: TO247BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRFP240 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: HEXFET_N
F0 "Q" 250 100 50 H V L B
F1 "IRFP240" 250 0 50 H V L B
F2 "transistor-power-TO247BV" 0 150 50 H I C C
DRAW
P 6 1 1 0     20 0 70 -20 70 -20 70 20 70 20 20 0 F
P 6 1 1 0     150 20 130 -10 130 -10 170 -10 170 -10 150 20 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 65 0 100 0
P 2 1 0 0 130 20 150 20
P 2 1 0 0 150 20 170 20
P 2 1 0 0 150 75 100 75
P 2 1 0 0 100 75 21 75
P 2 1 0 0 150 20 150 75
P 2 1 0 0 150 -75 150 -5
P 2 1 0 0 150 -75 100 -75
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRFP240-H
# Package Name: TO247BH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRFP240-H Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: HEXFET_N
F0 "Q" 250 100 50 H V L B
F1 "IRFP240-H" 250 0 50 H V L B
F2 "transistor-power-TO247BH" 0 150 50 H I C C
DRAW
P 6 1 1 0     20 0 70 -20 70 -20 70 20 70 20 20 0 F
P 6 1 1 0     150 20 130 -10 130 -10 170 -10 170 -10 150 20 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 65 0 100 0
P 2 1 0 0 130 20 150 20
P 2 1 0 0 150 20 170 20
P 2 1 0 0 150 75 100 75
P 2 1 0 0 100 75 21 75
P 2 1 0 0 150 20 150 75
P 2 1 0 0 150 -75 150 -5
P 2 1 0 0 150 -75 100 -75
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRFPC40
# Package Name: TO247BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRFPC40 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IRFPC40" 300 0 50 H V L B
F2 "transistor-power-TO247BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRFR5305
# Package Name: D-PAK_TO252AA
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRFR5305 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFPS
F0 "Q" 300 100 50 H V L B
F1 "IRFR5305" 300 0 50 H V L B
F2 "transistor-power-D-PAK_TO252AA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -40 -100 -40 100
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 100 0 100 75
P 2 1 0 0 20 75 100 75
P 2 1 0 0 100 -100 100 -75
P 2 1 0 0 100 -75 200 -75
P 2 1 0 0 200 75 100 75
P 2 1 0 0 100 75 100 100
P 2 1 0 0 88 0 90 0
P 2 1 0 0 90 0 100 0
P 2 1 0 0 90 0 40 -20
P 2 1 0 0 40 -20 40 20
P 2 1 0 0 40 20 90 0
P 2 1 0 0 45 0 10 0
P 2 1 0 0 45 10 80 0
P 2 1 0 0 80 0 45 -10
P 2 1 0 0 45 -10 45 0
P 2 1 0 0 45 0 55 0
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 30 225 -25
P 2 1 0 0 225 -25 175 -25
P 2 1 0 0 175 -25 200 30
P 2 1 0 0 225 30 200 30
P 2 1 0 0 200 30 175 30
P 2 1 0 0 175 30 165 40
P 2 1 0 0 225 30 235 20
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 75 5 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 76 -114 32 0 1 0 D
T 0 76 116 32 0 1 0 S
T 0 -74 66 32 0 1 0 G
X D 4 100 -200 100 U 40 40 1 1 P 
X G 1 -100 100 0 R 40 40 1 1 P 
X S 3 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRFU5305
# Package Name: I-PAK_TO251AA
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRFU5305 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFPS
F0 "Q" 300 100 50 H V L B
F1 "IRFU5305" 300 0 50 H V L B
F2 "transistor-power-I-PAK_TO251AA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -40 -100 -40 100
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 100 0 100 75
P 2 1 0 0 20 75 100 75
P 2 1 0 0 100 -100 100 -75
P 2 1 0 0 100 -75 200 -75
P 2 1 0 0 200 75 100 75
P 2 1 0 0 100 75 100 100
P 2 1 0 0 88 0 90 0
P 2 1 0 0 90 0 100 0
P 2 1 0 0 90 0 40 -20
P 2 1 0 0 40 -20 40 20
P 2 1 0 0 40 20 90 0
P 2 1 0 0 45 0 10 0
P 2 1 0 0 45 10 80 0
P 2 1 0 0 80 0 45 -10
P 2 1 0 0 45 -10 45 0
P 2 1 0 0 45 0 55 0
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 30 225 -25
P 2 1 0 0 225 -25 175 -25
P 2 1 0 0 175 -25 200 30
P 2 1 0 0 225 30 200 30
P 2 1 0 0 200 30 175 30
P 2 1 0 0 175 30 165 40
P 2 1 0 0 225 30 235 20
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 75 5 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 76 -114 32 0 1 0 D
T 0 76 116 32 0 1 0 S
T 0 -74 66 32 0 1 0 G
X D 2 100 -200 100 U 40 40 1 1 P 
X G 1 -100 100 0 R 40 40 1 1 P 
X S 3 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRFV460
# Package Name: TO258AA
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRFV460 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IRFV460" 300 0 50 H V L B
F2 "transistor-power-TO258AA" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D 1-D 100 200 100 D 40 40 1 1 P 
X G 3-G -100 -100 0 R 40 40 1 1 P 
X S 2-S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRFV460-V
# Package Name: TO258AA-V
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRFV460-V Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IRFV460-V" 300 0 50 H V L B
F2 "transistor-power-TO258AA-V" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D 1-D 100 200 100 D 40 40 1 1 P 
X G 3-G -100 -100 0 R 40 40 1 1 P 
X S 2-S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRG4BC15UD--L
# Package Name: TO262-H
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRG4BC15UD--L Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: NCHAN_IGBT
F0 "Q" -360 200 50 H V L B
F1 "IRG4BC15UD--L" -360 115 50 H V L B
F2 "transistor-power-TO262-H" 0 150 50 H I C C
DRAW
P 2 1 0 0 98 -99 20 -70
P 2 1 0 0 58 -66 100 -100
P 2 1 0 0 100 -100 46 -98
P 2 1 0 0 46 -98 58 -66
P 2 1 0 0 -100 -100 -50 -100
P 2 1 0 0 50 -15 20 0
P 2 1 0 0 20 90 20 70
P 2 1 0 0 20 70 20 50
P 2 1 0 0 20 20 20 0
P 2 1 0 0 20 0 20 -20
P 2 1 0 0 20 -50 20 -70
P 2 1 0 0 20 -70 20 -90
P 2 1 0 0 60 -78 78 -92
P 2 1 0 0 78 -92 56 -92
P 2 1 0 0 22 71 100 100
P 2 1 0 0 62 104 20 70
P 2 1 0 0 20 70 74 72
P 2 1 0 0 74 72 62 104
P 2 1 0 0 60 92 42 78
P 2 1 0 0 42 78 64 78
P 2 1 0 0 102 100 142 100
P 2 1 0 0 142 100 142 -100
P 2 1 0 0 142 -100 100 -100
P 2 1 0 0 126 18 158 18
P 2 1 0 0 140 14 126 -18
P 2 1 0 0 126 -18 158 -18
P 2 1 0 0 158 -18 144 14
P 2 1 0 0 136 -12 140 2
P 2 1 0 0 150 -14 144 0
S -56 -104 -28 104 1 1 0 F
X C 2 100 200 100 D 40 40 1 1 P 
X E 3 100 -200 100 U 40 40 1 1 P 
X G 1 -200 -100 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRG4BC15UD-L-V
# Package Name: TO262-V
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRG4BC15UD-L-V Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: NCHAN_IGBT
F0 "Q" -360 200 50 H V L B
F1 "IRG4BC15UD-L-V" -360 115 50 H V L B
F2 "transistor-power-TO262-V" 0 150 50 H I C C
DRAW
P 2 1 0 0 98 -99 20 -70
P 2 1 0 0 58 -66 100 -100
P 2 1 0 0 100 -100 46 -98
P 2 1 0 0 46 -98 58 -66
P 2 1 0 0 -100 -100 -50 -100
P 2 1 0 0 50 -15 20 0
P 2 1 0 0 20 90 20 70
P 2 1 0 0 20 70 20 50
P 2 1 0 0 20 20 20 0
P 2 1 0 0 20 0 20 -20
P 2 1 0 0 20 -50 20 -70
P 2 1 0 0 20 -70 20 -90
P 2 1 0 0 60 -78 78 -92
P 2 1 0 0 78 -92 56 -92
P 2 1 0 0 22 71 100 100
P 2 1 0 0 62 104 20 70
P 2 1 0 0 20 70 74 72
P 2 1 0 0 74 72 62 104
P 2 1 0 0 60 92 42 78
P 2 1 0 0 42 78 64 78
P 2 1 0 0 102 100 142 100
P 2 1 0 0 142 100 142 -100
P 2 1 0 0 142 -100 100 -100
P 2 1 0 0 126 18 158 18
P 2 1 0 0 140 14 126 -18
P 2 1 0 0 126 -18 158 -18
P 2 1 0 0 158 -18 144 14
P 2 1 0 0 136 -12 140 2
P 2 1 0 0 150 -14 144 0
S -56 -104 -28 104 1 1 0 F
X C 2 100 200 100 D 40 40 1 1 P 
X E 3 100 -200 100 U 40 40 1 1 P 
X G 1 -200 -100 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRG4BC15UD-S
# Package Name: D2PACK
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRG4BC15UD-S Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: NCHAN_IGBT
F0 "Q" -360 200 50 H V L B
F1 "IRG4BC15UD-S" -360 115 50 H V L B
F2 "transistor-power-D2PACK" 0 150 50 H I C C
DRAW
P 2 1 0 0 98 -99 20 -70
P 2 1 0 0 58 -66 100 -100
P 2 1 0 0 100 -100 46 -98
P 2 1 0 0 46 -98 58 -66
P 2 1 0 0 -100 -100 -50 -100
P 2 1 0 0 50 -15 20 0
P 2 1 0 0 20 90 20 70
P 2 1 0 0 20 70 20 50
P 2 1 0 0 20 20 20 0
P 2 1 0 0 20 0 20 -20
P 2 1 0 0 20 -50 20 -70
P 2 1 0 0 20 -70 20 -90
P 2 1 0 0 60 -78 78 -92
P 2 1 0 0 78 -92 56 -92
P 2 1 0 0 22 71 100 100
P 2 1 0 0 62 104 20 70
P 2 1 0 0 20 70 74 72
P 2 1 0 0 74 72 62 104
P 2 1 0 0 60 92 42 78
P 2 1 0 0 42 78 64 78
P 2 1 0 0 102 100 142 100
P 2 1 0 0 142 100 142 -100
P 2 1 0 0 142 -100 100 -100
P 2 1 0 0 126 18 158 18
P 2 1 0 0 140 14 126 -18
P 2 1 0 0 126 -18 158 -18
P 2 1 0 0 158 -18 144 14
P 2 1 0 0 136 -12 140 2
P 2 1 0 0 150 -14 144 0
S -56 -104 -28 104 1 1 0 F
X C 2 100 200 100 D 40 40 1 1 P 
X E 3 100 -200 100 U 40 40 1 1 P 
X G 1 -200 -100 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IRLML5203
# Package Name: MICRO3
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IRLML5203 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFPS
F0 "Q" 300 100 50 H V L B
F1 "IRLML5203" 300 0 50 H V L B
F2 "transistor-power-MICRO3" 0 150 50 H I C C
DRAW
P 2 1 0 0 -40 -100 -40 100
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 100 0 100 75
P 2 1 0 0 20 75 100 75
P 2 1 0 0 100 -100 100 -75
P 2 1 0 0 100 -75 200 -75
P 2 1 0 0 200 75 100 75
P 2 1 0 0 100 75 100 100
P 2 1 0 0 88 0 90 0
P 2 1 0 0 90 0 100 0
P 2 1 0 0 90 0 40 -20
P 2 1 0 0 40 -20 40 20
P 2 1 0 0 40 20 90 0
P 2 1 0 0 45 0 10 0
P 2 1 0 0 45 10 80 0
P 2 1 0 0 80 0 45 -10
P 2 1 0 0 45 -10 45 0
P 2 1 0 0 45 0 55 0
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 30 225 -25
P 2 1 0 0 225 -25 175 -25
P 2 1 0 0 175 -25 200 30
P 2 1 0 0 225 30 200 30
P 2 1 0 0 200 30 175 30
P 2 1 0 0 175 30 165 40
P 2 1 0 0 225 30 235 20
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 75 5 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 76 -114 32 0 1 0 D
T 0 76 116 32 0 1 0 S
T 0 -74 66 32 0 1 0 G
X D 3 100 -200 100 U 40 40 1 1 P 
X G 1 -100 100 0 R 40 40 1 1 P 
X S 2 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXFH6N90
# Package Name: TO-247AD-V
# Dev Tech: 90
# Dev Prefix: Q
# Gate count = 1
#
DEF IXFH6N90 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IXFH6N90" 300 0 50 H V L B
F2 "transistor-power-TO-247AD-V" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXFH6N100
# Package Name: TO-247AD-V
# Dev Tech: 100
# Dev Prefix: Q
# Gate count = 1
#
DEF IXFH6N100 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IXFH6N100" 300 0 50 H V L B
F2 "transistor-power-TO-247AD-V" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXFH_6N90
# Package Name: TO-247AD-H
# Dev Tech: 90
# Dev Prefix: Q
# Gate count = 1
#
DEF IXFH_6N90 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IXFH_6N90" 300 0 50 H V L B
F2 "transistor-power-TO-247AD-H" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXFH_6N100
# Package Name: TO-247AD-H
# Dev Tech: 100
# Dev Prefix: Q
# Gate count = 1
#
DEF IXFH_6N100 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IXFH_6N100" 300 0 50 H V L B
F2 "transistor-power-TO-247AD-H" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXFM6N90
# Package Name: TO204
# Dev Tech: 90
# Dev Prefix: Q
# Gate count = 1
#
DEF IXFM6N90 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IXFM6N90" 300 0 50 H V L B
F2 "transistor-power-TO204" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXFM6N100
# Package Name: TO204
# Dev Tech: 100
# Dev Prefix: Q
# Gate count = 1
#
DEF IXFM6N100 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "IXFM6N100" 300 0 50 H V L B
F2 "transistor-power-TO204" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXGT6N170
# Package Name: TO268
# Dev Tech: 6
# Dev Prefix: Q
# Gate count = 1
#
DEF IXGT6N170 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: IXIS-IGBT-NPN2
F0 "Q" 200 100 50 H V L B
F1 "IXGT6N170" 200 0 50 H V L B
F2 "transistor-power-TO268" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
P 2 1 0 0 -100 0 -50 0
P 2 1 0 0 -50 0 -50 50
S 0 -100 15 100 1 1 0 F
X C C@1 100 200 100 D 40 40 1 1 P 
X C@1 C@2 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
X G G -200 0 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXGT10N170
# Package Name: TO268
# Dev Tech: 10
# Dev Prefix: Q
# Gate count = 1
#
DEF IXGT10N170 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: IXIS-IGBT-NPN2
F0 "Q" 200 100 50 H V L B
F1 "IXGT10N170" 200 0 50 H V L B
F2 "transistor-power-TO268" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
P 2 1 0 0 -100 0 -50 0
P 2 1 0 0 -50 0 -50 50
S 0 -100 15 100 1 1 0 F
X C C@1 100 200 100 D 40 40 1 1 P 
X C@1 C@2 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
X G G -200 0 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXGT16N170
# Package Name: TO268
# Dev Tech: 16
# Dev Prefix: Q
# Gate count = 1
#
DEF IXGT16N170 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: IXIS-IGBT-NPN2
F0 "Q" 200 100 50 H V L B
F1 "IXGT16N170" 200 0 50 H V L B
F2 "transistor-power-TO268" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
P 2 1 0 0 -100 0 -50 0
P 2 1 0 0 -50 0 -50 50
S 0 -100 15 100 1 1 0 F
X C C@1 100 200 100 D 40 40 1 1 P 
X C@1 C@2 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
X G G -200 0 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXGT24N170
# Package Name: TO268
# Dev Tech: 24
# Dev Prefix: Q
# Gate count = 1
#
DEF IXGT24N170 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: IXIS-IGBT-NPN2
F0 "Q" 200 100 50 H V L B
F1 "IXGT24N170" 200 0 50 H V L B
F2 "transistor-power-TO268" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
P 2 1 0 0 -100 0 -50 0
P 2 1 0 0 -50 0 -50 50
S 0 -100 15 100 1 1 0 F
X C C@1 100 200 100 D 40 40 1 1 P 
X C@1 C@2 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
X G G -200 0 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXGT32N170
# Package Name: TO268
# Dev Tech: 32
# Dev Prefix: Q
# Gate count = 1
#
DEF IXGT32N170 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: IXIS-IGBT-NPN2
F0 "Q" 200 100 50 H V L B
F1 "IXGT32N170" 200 0 50 H V L B
F2 "transistor-power-TO268" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
P 2 1 0 0 -100 0 -50 0
P 2 1 0 0 -50 0 -50 50
S 0 -100 15 100 1 1 0 F
X C C@1 100 200 100 D 40 40 1 1 P 
X C@1 C@2 100 100 0 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
X G G -200 0 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: IXLF_19N250
# Package Name: ISOPLUS_I4
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF IXLF_19N250 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: IXIS-IGBT-NPN
F0 "Q" 200 100 50 H V L B
F1 "IXLF_19N250" 200 0 50 H V L B
F2 "transistor-power-ISOPLUS_I4" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 60 -60
P 2 1 0 0 60 -60 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 60 -60
P 2 1 0 0 60 -70 70 -60
P 2 1 0 0 -100 0 -50 0
P 2 1 0 0 -50 0 -50 50
S 0 -100 15 100 1 1 0 F
X C 5 100 200 100 D 40 40 1 1 P 
X E 2 100 -200 100 U 40 40 1 1 P 
X G 1 -200 0 100 R 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: MIC4420M
# Package Name: SO-08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF MIC4420M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MIC4420
F0 "IC" 50 150 50 H V L B
F1 "MIC4420M" 50 -200 50 H V L B
F2 "transistor-power-SO-08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -200 200 -100 150
P 2 1 0 0 -100 150 0 100
P 2 1 0 0 0 100 200 0
P 2 1 0 0 200 0 0 -100
P 2 1 0 0 0 -100 -100 -150
P 2 1 0 0 -100 -150 -200 -200
P 2 1 0 0 -200 -200 -200 200
P 2 1 0 0 -100 200 -100 150
P 2 1 0 0 0 200 0 100
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 0 -200 0 -100
X GND 4 -100 -300 100 U 40 40 1 1 W 
X GND1 5 0 -300 100 U 40 40 1 1 W 
X IN 2 -300 0 100 R 40 40 1 1 I 
X OUT@1 6 400 0 100 L 40 40 1 1 P 
X OUT@2 7 300 0 100 L 40 40 1 1 P 
X VS 1 -100 300 100 D 40 40 1 1 W 
X VS1 8 0 300 100 D 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: MIC4420MM
# Package Name: MSOP8
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF MIC4420MM IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MIC4420
F0 "IC" 50 150 50 H V L B
F1 "MIC4420MM" 50 -200 50 H V L B
F2 "transistor-power-MSOP8" 0 150 50 H I C C
DRAW
P 2 1 0 0 -200 200 -100 150
P 2 1 0 0 -100 150 0 100
P 2 1 0 0 0 100 200 0
P 2 1 0 0 200 0 0 -100
P 2 1 0 0 0 -100 -100 -150
P 2 1 0 0 -100 -150 -200 -200
P 2 1 0 0 -200 -200 -200 200
P 2 1 0 0 -100 200 -100 150
P 2 1 0 0 0 200 0 100
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 0 -200 0 -100
X GND 4 -100 -300 100 U 40 40 1 1 W 
X GND1 5 0 -300 100 U 40 40 1 1 W 
X IN 2 -300 0 100 R 40 40 1 1 I 
X OUT@1 6 400 0 100 L 40 40 1 1 P 
X OUT@2 7 300 0 100 L 40 40 1 1 P 
X VS 1 -100 300 100 D 40 40 1 1 W 
X VS1 8 0 300 100 D 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: MIC4420N
# Package Name: DIL08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF MIC4420N IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MIC4420
F0 "IC" 50 150 50 H V L B
F1 "MIC4420N" 50 -200 50 H V L B
F2 "transistor-power-DIL08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -200 200 -100 150
P 2 1 0 0 -100 150 0 100
P 2 1 0 0 0 100 200 0
P 2 1 0 0 200 0 0 -100
P 2 1 0 0 0 -100 -100 -150
P 2 1 0 0 -100 -150 -200 -200
P 2 1 0 0 -200 -200 -200 200
P 2 1 0 0 -100 200 -100 150
P 2 1 0 0 0 200 0 100
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 0 -200 0 -100
X GND 4 -100 -300 100 U 40 40 1 1 W 
X GND1 5 0 -300 100 U 40 40 1 1 W 
X IN 2 -300 0 100 R 40 40 1 1 I 
X OUT@1 6 400 0 100 L 40 40 1 1 P 
X OUT@2 7 300 0 100 L 40 40 1 1 P 
X VS 1 -100 300 100 D 40 40 1 1 W 
X VS1 8 0 300 100 D 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: MIC4429M
# Package Name: SO-08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF MIC4429M IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MIC4429
F0 "IC" 50 150 50 H V L B
F1 "MIC4429M" 50 -200 50 H V L B
F2 "transistor-power-SO-08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -200 200 -100 150
P 2 1 0 0 -100 150 0 100
P 2 1 0 0 0 100 200 0
P 2 1 0 0 200 0 0 -100
P 2 1 0 0 0 -100 -100 -150
P 2 1 0 0 -100 -150 -200 -200
P 2 1 0 0 -200 -200 -200 200
P 2 1 0 0 -100 200 -100 150
P 2 1 0 0 0 200 0 100
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 0 -200 0 -100
X GND 4 -100 -300 100 U 40 40 1 1 W 
X GND1 5 0 -300 100 U 40 40 1 1 W 
X IN 2 -300 0 100 R 40 40 1 1 I 
X OUT@1 6 400 0 100 L 40 40 1 1 P 
X OUT@2 7 300 0 100 L 40 40 1 1 P I
X VS 1 -100 300 100 D 40 40 1 1 W 
X VS1 8 0 300 100 D 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: MIC4429MM
# Package Name: MSOP8
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF MIC4429MM IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MIC4429
F0 "IC" 50 150 50 H V L B
F1 "MIC4429MM" 50 -200 50 H V L B
F2 "transistor-power-MSOP8" 0 150 50 H I C C
DRAW
P 2 1 0 0 -200 200 -100 150
P 2 1 0 0 -100 150 0 100
P 2 1 0 0 0 100 200 0
P 2 1 0 0 200 0 0 -100
P 2 1 0 0 0 -100 -100 -150
P 2 1 0 0 -100 -150 -200 -200
P 2 1 0 0 -200 -200 -200 200
P 2 1 0 0 -100 200 -100 150
P 2 1 0 0 0 200 0 100
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 0 -200 0 -100
X GND 4 -100 -300 100 U 40 40 1 1 W 
X GND1 5 0 -300 100 U 40 40 1 1 W 
X IN 2 -300 0 100 R 40 40 1 1 I 
X OUT@1 6 400 0 100 L 40 40 1 1 P 
X OUT@2 7 300 0 100 L 40 40 1 1 P I
X VS 1 -100 300 100 D 40 40 1 1 W 
X VS1 8 0 300 100 D 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: MIC4429N
# Package Name: DIL08
# Dev Tech: ''
# Dev Prefix: IC
# Gate count = 1
#
DEF MIC4429N IC 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MIC4429
F0 "IC" 50 150 50 H V L B
F1 "MIC4429N" 50 -200 50 H V L B
F2 "transistor-power-DIL08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -200 200 -100 150
P 2 1 0 0 -100 150 0 100
P 2 1 0 0 0 100 200 0
P 2 1 0 0 200 0 0 -100
P 2 1 0 0 0 -100 -100 -150
P 2 1 0 0 -100 -150 -200 -200
P 2 1 0 0 -200 -200 -200 200
P 2 1 0 0 -100 200 -100 150
P 2 1 0 0 0 200 0 100
P 2 1 0 0 -100 -200 -100 -150
P 2 1 0 0 0 -200 0 -100
X GND 4 -100 -300 100 U 40 40 1 1 W 
X GND1 5 0 -300 100 U 40 40 1 1 W 
X IN 2 -300 0 100 R 40 40 1 1 I 
X OUT@1 6 400 0 100 L 40 40 1 1 P 
X OUT@2 7 300 0 100 L 40 40 1 1 P I
X VS 1 -100 300 100 D 40 40 1 1 W 
X VS1 8 0 300 100 D 40 40 1 1 W 
ENDDRAW
ENDDEF

#
# Dev Name: MJ2955
# Package Name: TO3A
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF MJ2955 Q 0 40 Y Y 1 L N
# Gate Name: A
# Symbol Name: PNP2
F0 "Q" 200 100 50 H V L B
F1 "MJ2955" 200 0 50 H V L B
F2 "transistor-power-TO3A" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 85 65
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -100 0 U 40 40 1 1 P 
X C1 C1 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: MJE2955
# Package Name: TO220AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF MJE2955 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: PNP
F0 "Q" 200 100 50 H V L B
F1 "MJE2955" 200 0 50 H V L B
F2 "transistor-power-TO220AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: MJE3055
# Package Name: TO220AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF MJE3055 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: NPN
F0 "Q" 200 100 50 H V L B
F1 "MJE3055" 200 0 50 H V L B
F2 "transistor-power-TO220AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 65 -65
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 65 -65
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: N-MOSFET-SO8S
# Package Name: SO-08
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF N-MOSFET-SO8S Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFN-S3-D4
F0 "Q" 300 100 50 H V L B
F1 "N-MOSFET-SO8S" 300 0 50 H V L B
F2 "transistor-power-SO-08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D 5 100 300 100 D 40 40 1 1 P 
X D@1 6 100 250 100 D 40 40 1 1 P 
X D@2 7 100 200 100 D 40 40 1 1 P 
X D@3 8 100 150 100 U 40 40 1 1 P 
X G 4 -100 -100 0 R 40 40 1 1 P 
X S 1 100 -200 100 U 40 40 1 1 P 
X S@1 2 100 -150 100 U 40 40 1 1 P 
X S@2 3 100 -100 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: N-MOSFET_SYMBOL
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF N-MOSFET_SYMBOL Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFN-D
F0 "Q" 200 100 50 H V L B
F1 "N-MOSFET_SYMBOL" 200 0 50 H V L B
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -200 100 -75
P 2 1 0 0 -100 -100 -44 -100
P 2 1 0 0 100 200 100 75
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -59 32 0 1 0 G
ENDDRAW
ENDDEF

#
# Dev Name: NPN-DARL_SYMBOL
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF NPN-DARL_SYMBOL Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: N-DAR-D
F0 "Q" 200 100 50 H V L B
F1 "NPN-DARL_SYMBOL" 200 0 50 H V L B
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 100 125 0 25
P 2 1 0 0 100 -200 100 -100
P 2 1 0 0 -100 0 0 0
P 2 1 0 0 100 200 100 100
P 2 1 0 0 65 -50 85 -85
P 2 1 0 0 85 -85 50 -65
P 2 1 0 0 50 -65 65 -50
P 2 1 0 0 85 -85 60 -60
S -15 -100 15 100 1 1 0 F
ENDDRAW
ENDDEF

#
# Dev Name: NPN_SYMBOL
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF NPN_SYMBOL Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: NPN-D
F0 "Q" 200 100 50 H V L B
F1 "NPN_SYMBOL" 200 0 50 H V L B
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 60 -60
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 100 -200 100 -100
P 2 1 0 0 -100 0 0 0
P 2 1 0 0 100 200 100 100
P 2 1 0 0 85 -85 65 -50
P 2 1 0 0 65 -50 50 -65
P 2 1 0 0 50 -65 85 -85
P 2 1 0 0 85 -85 60 -60
S -15 -100 15 100 1 1 0 F
ENDDRAW
ENDDEF

#
# Dev Name: NTHD3101F
# Package Name: CHIPFET-1206A
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 2
#
DEF NTHD3101F Q 0 40 Y Y 2 L N
# Gate Name: -1
# Symbol Name: MOSFET_P-2D
F0 "Q" 250 50 50 H V L B
F1 "NTHD3101F" 250 -50 50 H V L B
F2 "transistor-power-CHIPFET-1206A" 0 150 50 H I C C
DRAW
P 6 1 1 0     100 0 50 20 50 20 50 -20 50 -20 100 0 F
P 6 1 1 0     150 20 130 -10 130 -10 170 -10 170 -10 150 20 F
P 2 1 0 0 -40 -100 -40 100
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 100 100 100 85
P 2 1 0 0 20 -85 100 -85
P 2 1 0 0 100 -85 100 -100
P 2 1 0 0 15 0 100 0
P 2 1 0 0 130 20 150 20
P 2 1 0 0 150 20 170 20
P 2 1 0 0 150 85 100 85
P 2 1 0 0 100 85 21 85
P 2 1 0 0 150 20 150 85
P 2 1 0 0 150 -85 150 -5
P 2 1 0 0 150 -85 100 -85
P 2 1 0 0 100 0 100 85
S -10 -110 20 -50 1 1 0 F
S -10 50 20 110 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 85 5 1 1 0 F
C 100 -85 5 1 1 0 F
X D 5 100 -200 100 U 40 40 1 1 P 
X D@2 6 100 -100 100 D 40 40 1 1 P 
X G 4 -100 100 0 R 40 40 1 1 P 
X S 3 100 200 100 D 40 40 1 1 P 
# Gate Name: -2
# Symbol Name: SCHOTTKY-DIODE-2A2C
P 6 2 1 0     0 -30 40 40 40 40 -40 40 -40 40 0 -30 F
P 2 2 0 0 40 -10 60 -10
P 2 2 0 0 60 -10 60 -30
P 2 2 0 0 60 -30 -60 -30
P 2 2 0 0 -60 -30 -60 -50
P 2 2 0 0 -60 -50 -40 -50
X A 1 0 100 100 D 40 40 2 1 P 
X A@1 2 0 200 100 D 40 40 2 1 P 
X C 7 0 -100 100 U 40 40 2 1 P 
X C@1 8 0 -200 100 U 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: P-MOSFET-SO8
# Package Name: SO-08
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF P-MOSFET-SO8 Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFP-S3-D4
F0 "Q" 300 100 50 H V L B
F1 "P-MOSFET-SO8" 300 0 50 H V L B
F2 "transistor-power-SO-08" 0 150 50 H I C C
DRAW
P 2 1 0 0 -40 -100 -40 100
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 100 0 100 75
P 2 1 0 0 20 75 100 75
P 2 1 0 0 100 -100 100 -75
P 2 1 0 0 100 -75 200 -75
P 2 1 0 0 200 75 100 75
P 2 1 0 0 100 75 100 150
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 30 225 -25
P 2 1 0 0 225 -25 175 -25
P 2 1 0 0 175 -25 200 30
P 2 1 0 0 225 30 200 30
P 2 1 0 0 200 30 175 30
P 2 1 0 0 175 30 165 40
P 2 1 0 0 225 30 235 20
P 2 1 0 0 100 0 50 -20
P 2 1 0 0 50 -20 50 20
P 2 1 0 0 50 20 100 0
P 2 1 0 0 55 0 20 0
P 2 1 0 0 55 10 90 0
P 2 1 0 0 90 0 55 -10
P 2 1 0 0 55 -10 55 0
P 2 1 0 0 55 0 65 0
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 75 5 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 156 -114 32 0 1 0 D
T 0 146 121 32 0 1 0 S
T 0 -84 66 32 0 1 0 G
X D 5 100 -300 100 U 40 40 1 1 P 
X D@1 6 100 -250 100 U 40 40 1 1 P 
X D@2 7 100 -200 100 U 40 40 1 1 P 
X D@3 8 100 -150 100 D 40 40 1 1 P 
X G 4 -100 100 0 R 40 40 1 1 P 
X S 1 100 300 100 D 40 40 1 1 P 
X S@1 2 100 250 100 D 40 40 1 1 P 
X S@2 3 100 200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: P-MOSFET_SYMBOL
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF P-MOSFET_SYMBOL Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFP-D
F0 "Q" 200 100 50 H V L B
F1 "P-MOSFET_SYMBOL" 200 0 50 H V L B
DRAW
P 2 1 0 0 -40 -100 -40 100
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 88 0 90 0
P 2 1 0 0 90 0 100 0
P 2 1 0 0 20 75 100 75
P 2 1 0 0 100 200 100 75
P 2 1 0 0 -100 100 -40 100
P 2 1 0 0 100 -200 100 -75
P 2 1 0 0 90 0 40 -20
P 2 1 0 0 40 -20 40 20
P 2 1 0 0 40 20 90 0
P 2 1 0 0 45 0 10 0
P 2 1 0 0 45 10 80 0
P 2 1 0 0 80 0 45 -10
P 2 1 0 0 45 -10 45 0
P 2 1 0 0 45 0 55 0
P 2 1 0 0 100 75 100 0
P 2 1 0 0 100 -75 150 -75
P 2 1 0 0 150 75 100 75
P 2 1 0 0 150 75 150 30
P 2 1 0 0 150 30 150 -75
P 2 1 0 0 150 30 175 -25
P 2 1 0 0 175 -25 125 -25
P 2 1 0 0 125 -25 150 30
P 2 1 0 0 175 30 150 30
P 2 1 0 0 150 30 125 30
P 2 1 0 0 125 30 115 40
P 2 1 0 0 175 30 185 20
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 75 5 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 61 -119 32 0 1 0 D
T 0 61 111 32 0 1 0 S
T 0 -84 71 32 0 1 0 G
ENDDRAW
ENDDEF

#
# Dev Name: P3N100FI
# Package Name: IW220B
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF P3N100FI Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: MFN
F0 "Q" 200 100 50 H V L B
F1 "P3N100FI" 200 0 50 H V L B
F2 "transistor-power-IW220B" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: P3N100XI
# Package Name: IW221
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF P3N100XI Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: MFN
F0 "Q" 200 100 50 H V L B
F1 "P3N100XI" 200 0 50 H V L B
F2 "transistor-power-IW221" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: PH7030L
# Package Name: SOT669
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF PH7030L Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: PH7030
F0 "Q" 250 100 50 H V L B
F1 "PH7030L" 250 0 50 H V L B
F2 "transistor-power-SOT669" 0 150 50 H I C C
DRAW
P 6 1 1 0     20 0 70 -20 70 -20 70 20 70 20 20 0 F
P 6 1 1 0     150 20 130 -10 130 -10 170 -10 170 -10 150 20 F
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 65 0 100 0
P 2 1 0 0 130 20 150 20
P 2 1 0 0 150 20 170 20
P 2 1 0 0 150 75 100 75
P 2 1 0 0 100 75 21 75
P 2 1 0 0 150 20 150 75
P 2 1 0 0 150 -75 150 -5
P 2 1 0 0 150 -75 100 -75
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
X D MB 100 200 100 D 40 40 1 1 P 
X G 4 -100 -100 0 R 40 40 1 1 P 
X S 1 100 -300 100 U 40 40 1 1 P 
X S@1 2 100 -200 100 U 40 40 1 1 P 
X S@2 3 100 -100 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: PMOSFET_NTO220BH
# Package Name: TO220BH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF PMOSFET_NTO220BH Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFN
F0 "Q" 200 100 50 H V L B
F1 "PMOSFET_NTO220BH" 200 0 50 H V L B
F2 "transistor-power-TO220BH" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: PMOSFET_NTO220BV
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF PMOSFET_NTO220BV Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFN
F0 "Q" 200 100 50 H V L B
F1 "PMOSFET_NTO220BV" 200 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: PMOSFET_PTO220BH
# Package Name: TO220BH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF PMOSFET_PTO220BH Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFP
F0 "Q" 200 100 50 H V L B
F1 "PMOSFET_PTO220BH" 200 0 50 H V L B
F2 "transistor-power-TO220BH" 0 150 50 H I C C
DRAW
P 2 1 0 0 -40 100 -40 -100
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 100 -100 100 -75
P 2 1 0 0 88 0 90 0
P 2 1 0 0 90 0 100 0
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 20 75
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 90 0 40 -20
P 2 1 0 0 40 -20 40 20
P 2 1 0 0 40 20 90 0
P 2 1 0 0 45 0 10 0
P 2 1 0 0 45 10 80 0
P 2 1 0 0 80 0 45 -10
P 2 1 0 0 45 -10 45 0
P 2 1 0 0 45 0 55 0
P 2 1 0 0 100 0 100 75
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 75 5 1 1 0 F
T 0 71 -109 32 0 1 0 D
T 0 71 111 32 0 1 0 S
T 0 -84 71 32 0 1 0 G
X D D 100 -200 100 U 40 40 1 1 P 
X G G -200 100 100 R 40 40 1 1 P 
X S S 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: PMOSFET_PTO220BV
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF PMOSFET_PTO220BV Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: MFP
F0 "Q" 200 100 50 H V L B
F1 "PMOSFET_PTO220BV" 200 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -40 100 -40 -100
P 2 1 0 0 100 -75 21 -75
P 2 1 0 0 100 -100 100 -75
P 2 1 0 0 88 0 90 0
P 2 1 0 0 90 0 100 0
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 20 75
P 2 1 0 0 -40 100 -100 100
P 2 1 0 0 90 0 40 -20
P 2 1 0 0 40 -20 40 20
P 2 1 0 0 40 20 90 0
P 2 1 0 0 45 0 10 0
P 2 1 0 0 45 10 80 0
P 2 1 0 0 80 0 45 -10
P 2 1 0 0 45 -10 45 0
P 2 1 0 0 45 0 55 0
P 2 1 0 0 100 0 100 75
S -10 50 20 100 1 1 0 F
S -10 -100 20 -50 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 75 5 1 1 0 F
T 0 71 -109 32 0 1 0 D
T 0 71 111 32 0 1 0 S
T 0 -84 71 32 0 1 0 G
X D D 100 -200 100 U 40 40 1 1 P 
X G G -200 100 100 R 40 40 1 1 P 
X S S 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: PNP-DARL_SYMBOL
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF PNP-DARL_SYMBOL Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: P-DAR-D
F0 "Q" 200 100 50 H V L B
F1 "PNP-DARL_SYMBOL" 200 0 50 H V L B
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 70 70 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 100 -125 0 -25
P 2 1 0 0 100 -200 100 -100
P 2 1 0 0 -100 0 0 0
P 2 1 0 0 100 200 100 100
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 70 70
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
ENDDRAW
ENDDEF

#
# Dev Name: PNP_SYMBOL
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF PNP_SYMBOL Q 0 40 Y Y 1 L N
# Gate Name: G$1
# Symbol Name: PNP-D
F0 "Q" 200 100 50 H V L B
F1 "PNP_SYMBOL" 200 0 50 H V L B
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 100 -200 100 -100
P 2 1 0 0 -100 0 0 0
P 2 1 0 0 100 200 100 100
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
ENDDRAW
ENDDEF

#
# Dev Name: STP5NA50
# Package Name: TO220BV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF STP5NA50 Q 0 40 Y Y 1 L N
# Gate Name: T
# Symbol Name: MFNS
F0 "Q" 300 100 50 H V L B
F1 "STP5NA50" 300 0 50 H V L B
F2 "transistor-power-TO220BV" 0 150 50 H I C C
DRAW
P 2 1 0 0 -44 95 -44 -100
P 2 1 0 0 -44 -100 -100 -100
P 2 1 0 0 100 75 21 75
P 2 1 0 0 100 0 100 -75
P 2 1 0 0 20 -75 100 -75
P 2 1 0 0 100 100 100 75
P 2 1 0 0 100 75 200 75
P 2 1 0 0 200 75 200 30
P 2 1 0 0 200 30 200 -75
P 2 1 0 0 200 -75 100 -75
P 2 1 0 0 100 -75 100 -100
P 2 1 0 0 200 30 175 -25
P 2 1 0 0 175 -25 225 -25
P 2 1 0 0 225 -25 200 30
P 2 1 0 0 175 30 200 30
P 2 1 0 0 200 30 225 30
P 2 1 0 0 225 30 235 40
P 2 1 0 0 175 30 165 20
P 2 1 0 0 20 0 70 -20
P 2 1 0 0 70 -20 70 20
P 2 1 0 0 70 20 20 0
P 2 1 0 0 65 0 100 0
P 2 1 0 0 65 10 30 0
P 2 1 0 0 30 0 65 -10
P 2 1 0 0 65 -10 65 0
P 2 1 0 0 65 0 55 0
S -10 -100 20 -50 1 1 0 F
S -10 50 20 100 1 1 0 F
S -10 -35 20 35 1 1 0 F
C 100 -75 5 1 1 0 F
C 100 75 5 1 1 0 F
T 0 66 116 32 0 1 0 D
T 0 66 -109 32 0 1 0 S
T 0 -84 -34 32 0 1 0 G
X D D 100 200 100 D 40 40 1 1 P 
X G G -100 -100 0 R 40 40 1 1 P 
X S S 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP41C
# Package Name: TO220AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP41C Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: NPN
F0 "Q" 200 100 50 H V L B
F1 "TIP41C" 200 0 50 H V L B
F2 "transistor-power-TO220AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 65 -65
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 65 -65
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP42C
# Package Name: TO220AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP42C Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: PNP
F0 "Q" 200 100 50 H V L B
F1 "TIP42C" 200 0 50 H V L B
F2 "transistor-power-TO220AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP120
# Package Name: TO220AH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP120 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: N-DAR
F0 "Q" 200 100 50 H V L B
F1 "TIP120" 200 0 50 H V L B
F2 "transistor-power-TO220AH" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 80 -80
P 2 1 0 0 80 -80 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 100 125 0 25
P 2 1 0 0 50 -70 70 -50
P 2 1 0 0 70 -50 80 -80
P 2 1 0 0 80 -80 60 -70
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP125
# Package Name: TO220AH
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP125 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: P-DAR
F0 "Q" 200 100 50 H V L B
F1 "TIP125" 200 0 50 H V L B
F2 "transistor-power-TO220AH" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 50 50
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 100 -125 0 -25
P 2 1 0 0 50 50 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 50 50
P 2 1 0 0 50 50 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP142
# Package Name: SOT93
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP142 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: N-DAR
F0 "Q" 200 100 50 H V L B
F1 "TIP142" 200 0 50 H V L B
F2 "transistor-power-SOT93" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 80 -80
P 2 1 0 0 80 -80 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 100 125 0 25
P 2 1 0 0 50 -70 70 -50
P 2 1 0 0 70 -50 80 -80
P 2 1 0 0 80 -80 60 -70
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP147
# Package Name: SOT93
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP147 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: P-DAR
F0 "Q" 200 100 50 H V L B
F1 "TIP147" 200 0 50 H V L B
F2 "transistor-power-SOT93" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 50 50
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 100 -125 0 -25
P 2 1 0 0 50 50 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 50 50
P 2 1 0 0 50 50 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP2955
# Package Name: TOP3AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP2955 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: PNP
F0 "Q" 200 100 50 H V L B
F1 "TIP2955" 200 0 50 H V L B
F2 "transistor-power-TOP3AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 -100 0 0
P 2 1 0 0 0 0 40 40
P 2 1 0 0 95 65 40 40
P 2 1 0 0 40 40 45 45
P 2 1 0 0 75 75 100 100
P 2 1 0 0 40 40 65 95
P 2 1 0 0 65 95 95 65
P 2 1 0 0 45 45 85 65
P 2 1 0 0 85 65 75 75
P 2 1 0 0 75 75 65 85
P 2 1 0 0 65 85 45 45
P 2 1 0 0 45 45 75 75
P 2 1 0 0 65 75 75 65
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 -200 100 U 40 40 1 1 P 
X E E 100 200 100 D 40 40 1 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: TIP3055
# Package Name: TOP3AV
# Dev Tech: ''
# Dev Prefix: Q
# Gate count = 1
#
DEF TIP3055 Q 0 40 Y Y 1 L N
# Gate Name: 1
# Symbol Name: NPN
F0 "Q" 200 100 50 H V L B
F1 "TIP3055" 200 0 50 H V L B
F2 "transistor-power-TOP3AV" 0 150 50 H I C C
DRAW
P 2 1 0 0 100 100 0 0
P 2 1 0 0 0 0 65 -65
P 2 1 0 0 85 -85 90 -90
P 2 1 0 0 70 -40 90 -90
P 2 1 0 0 90 -90 100 -100
P 2 1 0 0 90 -90 40 -70
P 2 1 0 0 40 -70 70 -40
P 2 1 0 0 85 -85 70 -50
P 2 1 0 0 70 -50 50 -70
P 2 1 0 0 50 -70 85 -85
P 2 1 0 0 85 -85 65 -65
P 2 1 0 0 60 -70 70 -60
S -15 -100 15 100 1 1 0 F
X B B -100 0 100 R 40 40 1 1 P 
X C C 100 200 100 D 40 40 1 1 P 
X E E 100 -200 100 U 40 40 1 1 P 
ENDDRAW
ENDDEF

#End Library