EESchema-LIBRARY Version 2.3 29/04/2008-12:24:07 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 521 # # Dev Name: -NPN-2C-BCE # Package Name: SOT89-BCE # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-2C-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN2C F0 "T" -400 300 50 H V L B F1 "-NPN-2C-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -95 P 2 1 0 0 60 -95 80 -95 P 2 1 0 0 80 -95 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C@1 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-2C-ECB # Package Name: SOT89-ECB # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-2C-ECB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN2C F0 "T" -400 300 50 H V L B F1 "-NPN-2C-ECB" -400 200 50 H V L B F2 "transistor-SOT89-ECB" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -95 P 2 1 0 0 60 -95 80 -95 P 2 1 0 0 80 -95 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C@1 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-SOT23-EBC # Package Name: SOT23-EBC # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-SOT23-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-SOT23-EBC" -400 200 50 H V L B F2 "transistor-SOT23-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-SOT89-BCE # Package Name: SOT89-BCE # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-SOT89-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-SOT89-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-SOT93 # Package Name: SOT93 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-SOT93 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-SOT93" -400 200 50 H V L B F2 "transistor-SOT93" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-SOT93V # Package Name: SOT93V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-SOT93V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-SOT93V" -400 200 50 H V L B F2 "transistor-SOT93V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO3/ # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO3/ T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO3/" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO5 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO5 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO5" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO18- # Package Name: TO18- # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO18- T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO18-" -400 200 50 H V L B F2 "transistor-TO18-" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO66 # Package Name: TO66 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO66 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO66" -400 200 50 H V L B F2 "transistor-TO66" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO92 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO92 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO92" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO92-E1 # Package Name: TO92-E1 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO92-E1 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO92-E1" -400 200 50 H V L B F2 "transistor-TO92-E1" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO92-ECB # Package Name: TO92-ECB # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO92-ECB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO92-ECB" -400 200 50 H V L B F2 "transistor-TO92-ECB" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO92L # Package Name: TO92L # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO92L T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO92L" -400 200 50 H V L B F2 "transistor-TO92L" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO126 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO126 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO126" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO126V # Package Name: TO126V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO126V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO126V" -400 200 50 H V L B F2 "transistor-TO126V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO202 # Package Name: TO202 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO202 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO202" -400 200 50 H V L B F2 "transistor-TO202" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO202V # Package Name: TO202V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO202V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO202V" -400 200 50 H V L B F2 "transistor-TO202V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO218 # Package Name: TO218 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO218 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO218" -400 200 50 H V L B F2 "transistor-TO218" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO218V # Package Name: TO218V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO218V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO218V" -400 200 50 H V L B F2 "transistor-TO218V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO220 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO220 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO220" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO220V # Package Name: TO220V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO220V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO220V" -400 200 50 H V L B F2 "transistor-TO220V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TO225AA # Package Name: TO225AA # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TO225AA T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TO225AA" -400 200 50 H V L B F2 "transistor-TO225AA" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TOP3 # Package Name: TOP3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TOP3 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TOP3" -400 200 50 H V L B F2 "transistor-TOP3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -NPN-TOP3V # Package Name: TOP3V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -NPN-TOP3V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "-NPN-TOP3V" -400 200 50 H V L B F2 "transistor-TOP3V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-2C-BCE # Package Name: SOT89-BCE # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-2C-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP2C F0 "T" -400 300 50 H V L B F1 "-PNP-2C-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 106 P 2 1 0 0 62 106 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 75 87 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 60 100 30 65 P 2 1 0 0 30 65 75 70 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 45 70 P 2 1 0 0 45 70 65 75 P 2 1 0 0 65 75 60 80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X C@1 C@1 100 -100 100 D 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-2C-ECB # Package Name: SOT89-ECB # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-2C-ECB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP2C F0 "T" -400 300 50 H V L B F1 "-PNP-2C-ECB" -400 200 50 H V L B F2 "transistor-SOT89-ECB" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 106 P 2 1 0 0 62 106 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 75 87 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 60 100 30 65 P 2 1 0 0 30 65 75 70 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 45 70 P 2 1 0 0 45 70 65 75 P 2 1 0 0 65 75 60 80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X C@1 C@1 100 -100 100 D 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-SOT23-BCE # Package Name: SOT23-BCE # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-SOT23-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-SOT23-BCE" -400 200 50 H V L B F2 "transistor-SOT23-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-SOT23-EBC # Package Name: SOT23-EBC # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-SOT23-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-SOT23-EBC" -400 200 50 H V L B F2 "transistor-SOT23-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-SOT89-ECB # Package Name: SOT89-ECB # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-SOT89-ECB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-SOT89-ECB" -400 200 50 H V L B F2 "transistor-SOT89-ECB" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-SOT93 # Package Name: SOT93 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-SOT93 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-SOT93" -400 200 50 H V L B F2 "transistor-SOT93" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-SOT93V # Package Name: SOT93V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-SOT93V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-SOT93V" -400 200 50 H V L B F2 "transistor-SOT93V" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO3 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO3 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO3" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO5 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO5 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO5" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO18- # Package Name: TO18- # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO18- T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO18-" -400 200 50 H V L B F2 "transistor-TO18-" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO18V # Package Name: TO18V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO18V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO18V" -400 200 50 H V L B F2 "transistor-TO18V" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO66 # Package Name: TO66 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO66 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO66" -400 200 50 H V L B F2 "transistor-TO66" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO92 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO92 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO92" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO92-BEC # Package Name: TO92-BEC # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO92-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO92-BEC" -400 200 50 H V L B F2 "transistor-TO92-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO92-CEB # Package Name: TO92-CEB # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO92-CEB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO92-CEB" -400 200 50 H V L B F2 "transistor-TO92-CEB" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO92-E1 # Package Name: TO92-E1 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO92-E1 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO92-E1" -400 200 50 H V L B F2 "transistor-TO92-E1" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 1 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO92/ # Package Name: TO92/ # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO92/ T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO92/" -400 200 50 H V L B F2 "transistor-TO92/" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO92L # Package Name: TO92L # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO92L T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO92L" -400 200 50 H V L B F2 "transistor-TO92L" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO126 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO126 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO126" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO126V # Package Name: TO126V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO126V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO126V" -400 200 50 H V L B F2 "transistor-TO126V" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO202 # Package Name: TO202 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO202 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO202" -400 200 50 H V L B F2 "transistor-TO202" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO202V # Package Name: TO202V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO202V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO202V" -400 200 50 H V L B F2 "transistor-TO202V" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO218 # Package Name: TO218 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO218 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO218" -400 200 50 H V L B F2 "transistor-TO218" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO218V # Package Name: TO218V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO218V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO218V" -400 200 50 H V L B F2 "transistor-TO218V" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO220 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO220 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO220" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO220V # Package Name: TO220V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO220V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO220V" -400 200 50 H V L B F2 "transistor-TO220V" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TO225AA # Package Name: TO225AA # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TO225AA T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TO225AA" -400 200 50 H V L B F2 "transistor-TO225AA" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TOP3 # Package Name: TOP3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TOP3 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TOP3" -400 200 50 H V L B F2 "transistor-TOP3" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: -PNP-TOP3V # Package Name: TOP3V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF -PNP-TOP3V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "-PNP-TOP3V" -400 200 50 H V L B F2 "transistor-TOP3V" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N706 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N706 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N706" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N930-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N930 # Dev Prefix: T # Gate count = 1 # DEF 2N930-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N930-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N1613 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N1613 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N1613" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N1613-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N1613 # Dev Prefix: T # Gate count = 1 # DEF 2N1613-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N1613-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N1711-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N1711 # Dev Prefix: T # Gate count = 1 # DEF 2N1711-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N1711-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N1893 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N1893 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N1893" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N1893-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N1893 # Dev Prefix: T # Gate count = 1 # DEF 2N1893-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N1893-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2102 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N2102 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2102" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2102-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2102 # Dev Prefix: T # Gate count = 1 # DEF 2N2102-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2102-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2218-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2218 # Dev Prefix: T # Gate count = 1 # DEF 2N2218-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2218-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2218-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2218 # Dev Prefix: T # Gate count = 1 # DEF 2N2218-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2218-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2219 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N2219 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2219" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2219-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2219 # Dev Prefix: T # Gate count = 1 # DEF 2N2219-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2219-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2219A-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2219A # Dev Prefix: T # Gate count = 1 # DEF 2N2219A-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2219A-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2222 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N2222 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2222" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2222-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2222 # Dev Prefix: T # Gate count = 1 # DEF 2N2222-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2222-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2222A-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2222A # Dev Prefix: T # Gate count = 1 # DEF 2N2222A-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2222A-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2369 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N2369 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2369" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2369-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2369 # Dev Prefix: T # Gate count = 1 # DEF 2N2369-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2369-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2369A-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2369A # Dev Prefix: T # Gate count = 1 # DEF 2N2369A-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2369A-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2405 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N2405 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2405" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2484 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N2484 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2484" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2484-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2484 # Dev Prefix: T # Gate count = 1 # DEF 2N2484-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2484-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2646 # Package Name: TO72 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N2646 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: UJP-N F0 "T" -400 100 50 H V L B F1 "2N2646" -400 200 50 H V L B F2 "transistor-TO72" 0 150 50 H I C C DRAW P 2 1 0 0 100 75 31 75 P 2 1 0 0 100 -75 31 -75 P 2 1 0 0 100 -100 100 -75 P 2 1 0 0 100 100 100 75 P 2 1 0 0 -30 -60 -60 -30 P 2 1 0 0 0 0 -30 -60 P 2 1 0 0 -60 -30 0 0 P 2 1 0 0 -100 -100 -15 -15 P 2 1 0 0 -15 -15 0 0 P 2 1 0 0 -50 -30 -30 -50 P 2 1 0 0 -30 -50 -15 -15 P 2 1 0 0 -15 -15 -45 -30 P 2 1 0 0 -45 -30 -30 -40 P 2 1 0 0 -30 -40 -30 -25 S 0 -100 30 100 1 1 0 F T 0 185 80 60 0 1 0 B2 T 0 185 -70 60 0 1 0 B1 T 0 -85 -170 60 0 1 0 E X B1 2 100 -200 100 U 40 40 1 1 P X B2 4 100 200 100 D 40 40 1 1 P X E 1 -200 -100 100 R 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2896-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2896 # Dev Prefix: T # Gate count = 1 # DEF 2N2896-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N2896-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2904-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2904 # Dev Prefix: T # Gate count = 1 # DEF 2N2904-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2904-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2904A-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2904A # Dev Prefix: T # Gate count = 1 # DEF 2N2904A-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2904A-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2905-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2905 # Dev Prefix: T # Gate count = 1 # DEF 2N2905-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2905-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2905A-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N2905A # Dev Prefix: T # Gate count = 1 # DEF 2N2905A-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2905A-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2906-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2906 # Dev Prefix: T # Gate count = 1 # DEF 2N2906-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2906-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2906A-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2906A # Dev Prefix: T # Gate count = 1 # DEF 2N2906A-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2906A-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2907-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2907 # Dev Prefix: T # Gate count = 1 # DEF 2N2907-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2907-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N2907A-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: 2N2907A # Dev Prefix: T # Gate count = 1 # DEF 2N2907A-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N2907A-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3019-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N3019 # Dev Prefix: T # Gate count = 1 # DEF 2N3019-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3019-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3020-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N3020 # Dev Prefix: T # Gate count = 1 # DEF 2N3020-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3020-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3054 # Package Name: TO66 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3054 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3054" -400 200 50 H V L B F2 "transistor-TO66" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X C@1 TO66 100 100 100 U 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3055 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3055 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3055" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3251-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: 2N3251 # Dev Prefix: T # Gate count = 1 # DEF 2N3251-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N3251-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3439 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3439 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3439" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3439-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N3439 # Dev Prefix: T # Gate count = 1 # DEF 2N3439-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3439-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3440 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3440 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3440" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3440-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: 2N3440 # Dev Prefix: T # Gate count = 1 # DEF 2N3440-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3440-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3441 # Package Name: TO66 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3441 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3441" -400 200 50 H V L B F2 "transistor-TO66" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X C@1 TO66 100 100 100 U 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3442 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3442 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3442" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3467-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N3467 # Dev Prefix: T # Gate count = 1 # DEF 2N3467-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N3467-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3565 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3565 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3565" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3583 # Package Name: TO66 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3583 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3583" -400 200 50 H V L B F2 "transistor-TO66" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X C@1 TO66 100 100 100 U 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3585 # Package Name: TO66 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3585 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3585" -400 200 50 H V L B F2 "transistor-TO66" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X C@1 TO66 100 100 100 U 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3635-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N3635 # Dev Prefix: T # Gate count = 1 # DEF 2N3635-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N3635-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3637-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N3637 # Dev Prefix: T # Gate count = 1 # DEF 2N3637-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N3637-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3700-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: 2N3700 # Dev Prefix: T # Gate count = 1 # DEF 2N3700-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3700-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3704 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3704 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3704" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3739 # Package Name: TO66 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3739 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3739" -400 200 50 H V L B F2 "transistor-TO66" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X C@1 TO66 100 100 100 U 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3772 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3772 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N3772" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3904 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N3904 T 0 40 Y Y 1 L N # Gate Name: G1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N3904" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N3963-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: 2N3963 # Dev Prefix: T # Gate count = 1 # DEF 2N3963-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N3963-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4013 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N4013 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N4013" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4033-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N4033 # Dev Prefix: T # Gate count = 1 # DEF 2N4033-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N4033-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4104 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N4104 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N4104" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4124-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N4124 # Dev Prefix: T # Gate count = 1 # DEF 2N4124-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N4124-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4126-PNP-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N4126 # Dev Prefix: T # Gate count = 1 # DEF 2N4126-PNP-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N4126-PNP-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4347 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N4347 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N4347" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4348 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N4348 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N4348" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4416 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N4416 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N4416" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N4923 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N4923 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N4923" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5038 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5038 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N5038" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5088 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5088 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5088" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5089 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5089 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5089" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5302 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5302 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N5302" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5400-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N5400 # Dev Prefix: T # Gate count = 1 # DEF 2N5400-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5400-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5401-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N5401 # Dev Prefix: T # Gate count = 1 # DEF 2N5401-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5401-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5415-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N5415 # Dev Prefix: T # Gate count = 1 # DEF 2N5415-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N5415-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5416-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: 2N5416 # Dev Prefix: T # Gate count = 1 # DEF 2N5416-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2N5416-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5496 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5496 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5496" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5550-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N5550 # Dev Prefix: T # Gate count = 1 # DEF 2N5550-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5550-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5551-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N5551 # Dev Prefix: T # Gate count = 1 # DEF 2N5551-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5551-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5631 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5631 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N5631" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5681 # Package Name: TO5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5681 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N5681" -400 200 50 H V L B F2 "transistor-TO5" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5686 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5686 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N5686" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N5878 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N5878 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "2N5878" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N6101 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N6101 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N6101" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N6292 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2N6292 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N6292" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N6427-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N6427 # Dev Prefix: T # Gate count = 1 # DEF 2N6427-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N6427-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N6517-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N6517 # Dev Prefix: T # Gate count = 1 # DEF 2N6517-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N6517-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2N6520-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: 2N6520 # Dev Prefix: T # Gate count = 1 # DEF 2N6520-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2N6520-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SA798 # Package Name: SIP-5 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SA798 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP-DIF2 F0 "T" -100 200 50 H V L B F1 "2SA798" 100 130 50 H V L B F2 "transistor-SIP-5" 0 150 50 H I C C DRAW P 2 1 0 0 -117 66 -137 102 P 2 1 0 0 -137 102 -179 58 P 2 1 0 0 -179 58 -117 66 P 2 1 0 0 -100 100 -128 83 P 2 1 0 0 -100 -100 -180 -60 P 2 1 0 0 -125 70 -140 95 P 2 1 0 0 -140 95 -170 65 P 2 1 0 0 -170 65 -130 70 P 2 1 0 0 -130 70 -140 85 P 2 1 0 0 -140 85 -155 75 P 2 1 0 0 -155 75 -140 75 P 2 1 0 0 117 66 137 102 P 2 1 0 0 137 102 179 58 P 2 1 0 0 179 58 117 66 P 2 1 0 0 100 100 128 83 P 2 1 0 0 100 -100 180 -60 P 2 1 0 0 125 70 140 95 P 2 1 0 0 140 95 170 65 P 2 1 0 0 170 65 130 70 P 2 1 0 0 130 70 140 85 P 2 1 0 0 140 85 155 75 P 2 1 0 0 155 75 140 75 P 2 1 0 0 100 100 -100 100 S -210 -100 -180 100 1 1 0 F S 180 -100 210 100 1 1 0 F C 0 100 14 1 1 0 N X B1 2 -300 0 100 R 40 40 1 1 P X B2 4 300 0 100 L 40 40 1 1 P X C1 1 -100 -200 100 U 40 40 1 1 P X C2 5 100 -200 100 U 40 40 1 1 P X E 3 0 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1306 # Package Name: TO220BV # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC1306 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1306" -400 200 50 H V L B F2 "transistor-TO220BV" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1307 # Package Name: TO220AV # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC1307 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1307" -400 200 50 H V L B F2 "transistor-TO220AV" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1815-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: 2SC1815 # Dev Prefix: T # Gate count = 1 # DEF 2SC1815-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "2SC1815-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1944 # Package Name: T-30_V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC1944 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1944" -400 200 50 H V L B F2 "transistor-T-30_V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1944H # Package Name: T-30 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC1944H T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1944H" -400 200 50 H V L B F2 "transistor-T-30" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969H # Package Name: T-30 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC1969H T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969H" -400 200 50 H V L B F2 "transistor-T-30" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969V # Package Name: T-30_V # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC1969V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969V" -400 200 50 H V L B F2 "transistor-T-30_V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969AH # Package Name: T-30 # Dev Tech: A # Dev Prefix: T # Gate count = 1 # DEF 2SC1969AH T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969AH" -400 200 50 H V L B F2 "transistor-T-30" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969AV # Package Name: T-30_V # Dev Tech: A # Dev Prefix: T # Gate count = 1 # DEF 2SC1969AV T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969AV" -400 200 50 H V L B F2 "transistor-T-30_V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969CH # Package Name: T-30 # Dev Tech: C # Dev Prefix: T # Gate count = 1 # DEF 2SC1969CH T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969CH" -400 200 50 H V L B F2 "transistor-T-30" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969CV # Package Name: T-30_V # Dev Tech: C # Dev Prefix: T # Gate count = 1 # DEF 2SC1969CV T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969CV" -400 200 50 H V L B F2 "transistor-T-30_V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969XH # Package Name: T-30 # Dev Tech: X # Dev Prefix: T # Gate count = 1 # DEF 2SC1969XH T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969XH" -400 200 50 H V L B F2 "transistor-T-30" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC1969XV # Package Name: T-30_V # Dev Tech: X # Dev Prefix: T # Gate count = 1 # DEF 2SC1969XV T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC1969XV" -400 200 50 H V L B F2 "transistor-T-30_V" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC2098H # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC2098H T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC2098H" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC2098V # Package Name: TO220AV # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC2098V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC2098V" -400 200 50 H V L B F2 "transistor-TO220AV" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC2395 # Package Name: 2-10H1A # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC2395 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN2E F0 "T" -400 300 50 H V L B F1 "2SC2395" -400 200 50 H V L B F2 "transistor-2-10H1A" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -95 P 2 1 0 0 60 -95 80 -95 P 2 1 0 0 80 -95 70 -85 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 4 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P X E@1 3 100 -100 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC2509H # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC2509H T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC2509H" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC2509V # Package Name: TO220AV # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC2509V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC2509V" -400 200 50 H V L B F2 "transistor-TO220AV" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC3212H # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC3212H T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC3212H" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 2SC3212V # Package Name: TO220AV # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 2SC3212V T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "2SC3212V" -400 200 50 H V L B F2 "transistor-TO220AV" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 3SK59 # Package Name: TO72 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 3SK59 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: DUAL-GATE-FET+D F0 "T" 150 50 50 H V L B F1 "3SK59" 150 -100 50 H V L B F2 "transistor-TO72" 0 150 50 H I C C DRAW P 6 1 1 0 10 0 60 20 60 20 60 -20 60 -20 10 0 F P 6 1 1 0 -80 -120 -60 -120 -60 -120 -70 -130 -70 -130 -80 -120 F P 6 1 1 0 -60 -140 -80 -140 -80 -140 -70 -130 -70 -130 -60 -140 F P 6 1 1 0 -120 -120 -100 -120 -100 -120 -110 -130 -110 -130 -120 -120 F P 6 1 1 0 -100 -140 -120 -140 -120 -140 -110 -130 -110 -130 -100 -140 F P 2 1 0 0 -40 100 -40 130 P 2 1 0 0 -40 -100 -40 -70 P 2 1 0 0 10 130 10 100 P 2 1 0 0 10 100 10 -100 P 2 1 0 0 10 -100 10 -130 P 2 1 0 0 10 100 100 100 P 2 1 0 0 10 -100 100 -100 P 2 1 0 0 100 -100 100 -170 P 2 1 0 0 100 -170 100 -180 P 2 1 0 0 100 -100 100 0 P 2 1 0 0 100 0 20 0 P 2 1 0 0 -100 100 -40 100 P 2 1 0 0 -100 -100 -70 -100 P 2 1 0 0 -70 -100 -40 -100 P 2 1 0 0 -70 -100 -70 -170 P 2 1 0 0 -70 -170 100 -170 P 2 1 0 0 -80 -130 -60 -130 P 2 1 0 0 -110 100 -110 -170 P 2 1 0 0 -110 -170 -70 -170 P 2 1 0 0 -120 -130 -100 -130 C -110 100 10 1 1 0 N C -70 -100 10 1 1 0 N C -70 -170 10 1 1 0 N C 100 -170 10 1 1 0 N C 100 -100 10 1 1 0 N T 0 -140 160 40 0 1 0 G1 T 0 -150 -160 40 0 1 0 G2 X DRAIN 1 100 200 100 D 40 40 1 1 P X G1 3 -200 100 100 R 40 40 1 1 P X G2 2 -200 -100 100 R 40 40 1 1 P X SOURCE 4 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: 3SK63 # Package Name: TO72 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF 3SK63 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: DUAL-GATE-FET+D F0 "T" 150 50 50 H V L B F1 "3SK63" 150 -100 50 H V L B F2 "transistor-TO72" 0 150 50 H I C C DRAW P 6 1 1 0 10 0 60 20 60 20 60 -20 60 -20 10 0 F P 6 1 1 0 -80 -120 -60 -120 -60 -120 -70 -130 -70 -130 -80 -120 F P 6 1 1 0 -60 -140 -80 -140 -80 -140 -70 -130 -70 -130 -60 -140 F P 6 1 1 0 -120 -120 -100 -120 -100 -120 -110 -130 -110 -130 -120 -120 F P 6 1 1 0 -100 -140 -120 -140 -120 -140 -110 -130 -110 -130 -100 -140 F P 2 1 0 0 -40 100 -40 130 P 2 1 0 0 -40 -100 -40 -70 P 2 1 0 0 10 130 10 100 P 2 1 0 0 10 100 10 -100 P 2 1 0 0 10 -100 10 -130 P 2 1 0 0 10 100 100 100 P 2 1 0 0 10 -100 100 -100 P 2 1 0 0 100 -100 100 -170 P 2 1 0 0 100 -170 100 -180 P 2 1 0 0 100 -100 100 0 P 2 1 0 0 100 0 20 0 P 2 1 0 0 -100 100 -40 100 P 2 1 0 0 -100 -100 -70 -100 P 2 1 0 0 -70 -100 -40 -100 P 2 1 0 0 -70 -100 -70 -170 P 2 1 0 0 -70 -170 100 -170 P 2 1 0 0 -80 -130 -60 -130 P 2 1 0 0 -110 100 -110 -170 P 2 1 0 0 -110 -170 -70 -170 P 2 1 0 0 -120 -130 -100 -130 C -110 100 10 1 1 0 N C -70 -100 10 1 1 0 N C -70 -170 10 1 1 0 N C 100 -170 10 1 1 0 N C 100 -100 10 1 1 0 N T 0 -140 160 40 0 1 0 G1 T 0 -150 -160 40 0 1 0 G2 X DRAIN 1 100 200 100 D 40 40 1 1 P X G1 3 -200 100 100 R 40 40 1 1 P X G2 2 -200 -100 100 R 40 40 1 1 P X SOURCE 4 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC107 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC107 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC107" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC107A-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BC107A # Dev Prefix: T # Gate count = 1 # DEF BC107A-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC107A-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC107B-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BC107B # Dev Prefix: T # Gate count = 1 # DEF BC107B-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC107B-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC108B-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BC108B # Dev Prefix: T # Gate count = 1 # DEF BC108B-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC108B-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC108C-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BC108C # Dev Prefix: T # Gate count = 1 # DEF BC108C-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC108C-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC140-10-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BC140-10 # Dev Prefix: T # Gate count = 1 # DEF BC140-10-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC140-10-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC140-16-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BC140-16 # Dev Prefix: T # Gate count = 1 # DEF BC140-16-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC140-16-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC141-10-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BC141-10 # Dev Prefix: T # Gate count = 1 # DEF BC141-10-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC141-10-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC141-16-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BC141-16 # Dev Prefix: T # Gate count = 1 # DEF BC141-16-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC141-16-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC160-16-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: BC160-16 # Dev Prefix: T # Gate count = 1 # DEF BC160-16-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC160-16-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC161-16-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: BC161-16 # Dev Prefix: T # Gate count = 1 # DEF BC161-16-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC161-16-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC177B-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BC177B # Dev Prefix: T # Gate count = 1 # DEF BC177B-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC177B-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC237 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC237 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC237" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC238 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC238 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC238" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC327-16-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC327-16 # Dev Prefix: T # Gate count = 1 # DEF BC327-16-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC327-16-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC327-25-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC327-25 # Dev Prefix: T # Gate count = 1 # DEF BC327-25-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC327-25-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC327-40-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC327-40 # Dev Prefix: T # Gate count = 1 # DEF BC327-40-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC327-40-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC327-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC327 # Dev Prefix: T # Gate count = 1 # DEF BC327-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC327-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC328-16-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC328-16 # Dev Prefix: T # Gate count = 1 # DEF BC328-16-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC328-16-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC328-25-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC328-25 # Dev Prefix: T # Gate count = 1 # DEF BC328-25-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC328-25-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC328-40-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC328-40 # Dev Prefix: T # Gate count = 1 # DEF BC328-40-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC328-40-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC328-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC328 # Dev Prefix: T # Gate count = 1 # DEF BC328-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC328-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC337 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC337 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC337" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC337-16-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC337-16 # Dev Prefix: T # Gate count = 1 # DEF BC337-16-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC337-16-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC337-25-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC337-25 # Dev Prefix: T # Gate count = 1 # DEF BC337-25-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC337-25-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC337-40-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC337-40 # Dev Prefix: T # Gate count = 1 # DEF BC337-40-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC337-40-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC337-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC337 # Dev Prefix: T # Gate count = 1 # DEF BC337-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC337-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC338-16-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC338-16 # Dev Prefix: T # Gate count = 1 # DEF BC338-16-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC338-16-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC338-25-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC338-25 # Dev Prefix: T # Gate count = 1 # DEF BC338-25-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC338-25-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC338-40-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC338-40 # Dev Prefix: T # Gate count = 1 # DEF BC338-40-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC338-40-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC338-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC338 # Dev Prefix: T # Gate count = 1 # DEF BC338-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC338-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC368-NPN-TO92-ECB # Package Name: TO92-ECB # Dev Tech: BC368 # Dev Prefix: T # Gate count = 1 # DEF BC368-NPN-TO92-ECB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC368-NPN-TO92-ECB" -400 200 50 H V L B F2 "transistor-TO92-ECB" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC369-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BC369 # Dev Prefix: T # Gate count = 1 # DEF BC369-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC369-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC372-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: BC372 # Dev Prefix: T # Gate count = 1 # DEF BC372-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC372-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC373-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: BC373 # Dev Prefix: T # Gate count = 1 # DEF BC373-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC373-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC393-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BC393 # Dev Prefix: T # Gate count = 1 # DEF BC393-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC393-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC447-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC447 # Dev Prefix: T # Gate count = 1 # DEF BC447-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC447-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC448-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC448 # Dev Prefix: T # Gate count = 1 # DEF BC448-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC448-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC449-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC449 # Dev Prefix: T # Gate count = 1 # DEF BC449-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC449-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC450-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC450 # Dev Prefix: T # Gate count = 1 # DEF BC450-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC450-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC487-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC487 # Dev Prefix: T # Gate count = 1 # DEF BC487-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC487-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC488-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC488 # Dev Prefix: T # Gate count = 1 # DEF BC488-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC488-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC489-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC489 # Dev Prefix: T # Gate count = 1 # DEF BC489-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC489-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC490-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC490 # Dev Prefix: T # Gate count = 1 # DEF BC490-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC490-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC516-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC516 # Dev Prefix: T # Gate count = 1 # DEF BC516-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC516-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC517 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC517 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BC517" -160 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 2 -100 0 100 R 40 40 1 1 P X C 3 200 100 100 D 40 40 1 1 P X E 1 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC517-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC517 # Dev Prefix: T # Gate count = 1 # DEF BC517-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC517-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC546A-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC546A # Dev Prefix: T # Gate count = 1 # DEF BC546A-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC546A-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC546B-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC546B # Dev Prefix: T # Gate count = 1 # DEF BC546B-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC546B-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC547 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC547 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC547" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC547A-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC547A # Dev Prefix: T # Gate count = 1 # DEF BC547A-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC547A-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC547B-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC547B # Dev Prefix: T # Gate count = 1 # DEF BC547B-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC547B-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC548A-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC548A # Dev Prefix: T # Gate count = 1 # DEF BC548A-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC548A-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC548B-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC548B # Dev Prefix: T # Gate count = 1 # DEF BC548B-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC548B-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC548C-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC548C # Dev Prefix: T # Gate count = 1 # DEF BC548C-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC548C-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC549B-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC549B # Dev Prefix: T # Gate count = 1 # DEF BC549B-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC549B-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC549C-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC549C # Dev Prefix: T # Gate count = 1 # DEF BC549C-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC549C-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC550B-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC550B # Dev Prefix: T # Gate count = 1 # DEF BC550B-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC550B-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC550C-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC550C # Dev Prefix: T # Gate count = 1 # DEF BC550C-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC550C-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC556A-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC556A # Dev Prefix: T # Gate count = 1 # DEF BC556A-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC556A-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC556B-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC556B # Dev Prefix: T # Gate count = 1 # DEF BC556B-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC556B-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC557A-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC557A # Dev Prefix: T # Gate count = 1 # DEF BC557A-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC557A-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC557B-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC557B # Dev Prefix: T # Gate count = 1 # DEF BC557B-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC557B-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC557C-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC557C # Dev Prefix: T # Gate count = 1 # DEF BC557C-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC557C-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC558A-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC558A # Dev Prefix: T # Gate count = 1 # DEF BC558A-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC558A-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC558B-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC558B # Dev Prefix: T # Gate count = 1 # DEF BC558B-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC558B-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC558C-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC558C # Dev Prefix: T # Gate count = 1 # DEF BC558C-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC558C-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC559A-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC559A # Dev Prefix: T # Gate count = 1 # DEF BC559A-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC559A-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC559B-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC559B # Dev Prefix: T # Gate count = 1 # DEF BC559B-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC559B-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC559C-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC559C # Dev Prefix: T # Gate count = 1 # DEF BC559C-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC559C-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC560C-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC560C # Dev Prefix: T # Gate count = 1 # DEF BC560C-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC560C-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC618-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BC618 # Dev Prefix: T # Gate count = 1 # DEF BC618-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC618-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC635-NPN-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BC635 # Dev Prefix: T # Gate count = 1 # DEF BC635-NPN-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC635-NPN-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC636-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BC636 # Dev Prefix: T # Gate count = 1 # DEF BC636-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC636-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC637-NPN-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BC637 # Dev Prefix: T # Gate count = 1 # DEF BC637-NPN-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC637-NPN-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC638-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BC638 # Dev Prefix: T # Gate count = 1 # DEF BC638-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC638-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC639-NPN-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BC639 # Dev Prefix: T # Gate count = 1 # DEF BC639-NPN-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC639-NPN-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC640-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BC640 # Dev Prefix: T # Gate count = 1 # DEF BC640-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC640-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC807-16-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC807-16 # Dev Prefix: T # Gate count = 1 # DEF BC807-16-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC807-16-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC807-16LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC807-16LT1 # Dev Prefix: T # Gate count = 1 # DEF BC807-16LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC807-16LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC807-25-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC807-25 # Dev Prefix: T # Gate count = 1 # DEF BC807-25-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC807-25-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC807-25LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC807-25LT1 # Dev Prefix: T # Gate count = 1 # DEF BC807-25LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC807-25LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC807-40-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC807-40 # Dev Prefix: T # Gate count = 1 # DEF BC807-40-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC807-40-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC807-40LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC807-40LT1 # Dev Prefix: T # Gate count = 1 # DEF BC807-40LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC807-40LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC808-16-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC808-16 # Dev Prefix: T # Gate count = 1 # DEF BC808-16-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC808-16-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC808-25-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC808-25 # Dev Prefix: T # Gate count = 1 # DEF BC808-25-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC808-25-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC808-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC808 # Dev Prefix: T # Gate count = 1 # DEF BC808-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC808-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC817-16-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC817-16 # Dev Prefix: T # Gate count = 1 # DEF BC817-16-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC817-16-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC817-16LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC817-16LT1 # Dev Prefix: T # Gate count = 1 # DEF BC817-16LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC817-16LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC817-25-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC817-25 # Dev Prefix: T # Gate count = 1 # DEF BC817-25-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC817-25-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC817-25LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC817-25LT1 # Dev Prefix: T # Gate count = 1 # DEF BC817-25LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC817-25LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC817-40-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC817-40 # Dev Prefix: T # Gate count = 1 # DEF BC817-40-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC817-40-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC817-40LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC817-40LT1 # Dev Prefix: T # Gate count = 1 # DEF BC817-40LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC817-40LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC817-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC817 # Dev Prefix: T # Gate count = 1 # DEF BC817-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC817-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC818-16-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC818-16 # Dev Prefix: T # Gate count = 1 # DEF BC818-16-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC818-16-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC818-25-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC818-25 # Dev Prefix: T # Gate count = 1 # DEF BC818-25-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC818-25-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC818-40-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC818-40 # Dev Prefix: T # Gate count = 1 # DEF BC818-40-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC818-40-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC818-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC818 # Dev Prefix: T # Gate count = 1 # DEF BC818-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC818-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC846 # Package Name: SOT23 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC846 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC846" -400 200 50 H V L B F2 "transistor-SOT23" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC846-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC846 # Dev Prefix: T # Gate count = 1 # DEF BC846-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC846-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC846A-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC846A # Dev Prefix: T # Gate count = 1 # DEF BC846A-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC846A-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC846ALT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC846ALT1 # Dev Prefix: T # Gate count = 1 # DEF BC846ALT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC846ALT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC846B-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC846B # Dev Prefix: T # Gate count = 1 # DEF BC846B-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC846B-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC846BLT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC846BLT1 # Dev Prefix: T # Gate count = 1 # DEF BC846BLT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC846BLT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847 # Package Name: SOT23 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC847 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847" -400 200 50 H V L B F2 "transistor-SOT23" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC847 # Dev Prefix: T # Gate count = 1 # DEF BC847-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847A-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC847A # Dev Prefix: T # Gate count = 1 # DEF BC847A-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847A-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847ALT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC847ALT1 # Dev Prefix: T # Gate count = 1 # DEF BC847ALT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847ALT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847B-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC847B # Dev Prefix: T # Gate count = 1 # DEF BC847B-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847B-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847BLT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC847BLT1 # Dev Prefix: T # Gate count = 1 # DEF BC847BLT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847BLT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847C-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC847C # Dev Prefix: T # Gate count = 1 # DEF BC847C-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847C-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC847CLT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC847CLT1 # Dev Prefix: T # Gate count = 1 # DEF BC847CLT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC847CLT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848 # Package Name: SOT23 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC848 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848" -400 200 50 H V L B F2 "transistor-SOT23" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC848 # Dev Prefix: T # Gate count = 1 # DEF BC848-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848A-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC848A # Dev Prefix: T # Gate count = 1 # DEF BC848A-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848A-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848ALT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC848ALT1 # Dev Prefix: T # Gate count = 1 # DEF BC848ALT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848ALT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848B-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC848B # Dev Prefix: T # Gate count = 1 # DEF BC848B-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848B-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848BLT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC848BLT1 # Dev Prefix: T # Gate count = 1 # DEF BC848BLT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848BLT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848C-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC848C # Dev Prefix: T # Gate count = 1 # DEF BC848C-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848C-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC848CLT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC848CLT1 # Dev Prefix: T # Gate count = 1 # DEF BC848CLT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC848CLT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC849 # Package Name: SOT23 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC849 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC849" -400 200 50 H V L B F2 "transistor-SOT23" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC849-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC849 # Dev Prefix: T # Gate count = 1 # DEF BC849-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC849-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC850 # Package Name: SOT23 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BC850 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC850" -400 200 50 H V L B F2 "transistor-SOT23" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC850-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC850 # Dev Prefix: T # Gate count = 1 # DEF BC850-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC850-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC856A-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC856A # Dev Prefix: T # Gate count = 1 # DEF BC856A-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC856A-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC856ALT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC856ALT1 # Dev Prefix: T # Gate count = 1 # DEF BC856ALT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC856ALT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC856B-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC856B # Dev Prefix: T # Gate count = 1 # DEF BC856B-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC856B-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC856BLT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC856BLT1 # Dev Prefix: T # Gate count = 1 # DEF BC856BLT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC856BLT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC857A-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC857A # Dev Prefix: T # Gate count = 1 # DEF BC857A-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC857A-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC857ALT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC857ALT1 # Dev Prefix: T # Gate count = 1 # DEF BC857ALT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC857ALT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC857B-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC857B # Dev Prefix: T # Gate count = 1 # DEF BC857B-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC857B-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC857BLT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC857BLT1 # Dev Prefix: T # Gate count = 1 # DEF BC857BLT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC857BLT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC857C-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC857C # Dev Prefix: T # Gate count = 1 # DEF BC857C-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC857C-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC858A-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC858A # Dev Prefix: T # Gate count = 1 # DEF BC858A-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC858A-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC858ALT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC858ALT1 # Dev Prefix: T # Gate count = 1 # DEF BC858ALT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC858ALT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC858B-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC858B # Dev Prefix: T # Gate count = 1 # DEF BC858B-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC858B-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC858BLT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC858BLT1 # Dev Prefix: T # Gate count = 1 # DEF BC858BLT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC858BLT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC858C-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC858C # Dev Prefix: T # Gate count = 1 # DEF BC858C-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC858C-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC858CLT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BC858CLT1 # Dev Prefix: T # Gate count = 1 # DEF BC858CLT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BC858CLT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BC868-NPN-SOT89-BCE # Package Name: SOT89-BCE # Dev Tech: BC868 # Dev Prefix: T # Gate count = 1 # DEF BC868-NPN-SOT89-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BC868-NPN-SOT89-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCF29-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCF29 # Dev Prefix: T # Gate count = 1 # DEF BCF29-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCF29-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCF30-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCF30 # Dev Prefix: T # Gate count = 1 # DEF BCF30-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCF30-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCF32-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCF32 # Dev Prefix: T # Gate count = 1 # DEF BCF32-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCF32-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCF33-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCF33 # Dev Prefix: T # Gate count = 1 # DEF BCF33-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCF33-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCF81-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCF81 # Dev Prefix: T # Gate count = 1 # DEF BCF81-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCF81-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCV71-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCV71 # Dev Prefix: T # Gate count = 1 # DEF BCV71-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCV71-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCV72-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCV72 # Dev Prefix: T # Gate count = 1 # DEF BCV72-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCV72-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCW31-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCW31 # Dev Prefix: T # Gate count = 1 # DEF BCW31-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCW31-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCW32-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCW32 # Dev Prefix: T # Gate count = 1 # DEF BCW32-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCW32-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCW33-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCW33 # Dev Prefix: T # Gate count = 1 # DEF BCW33-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCW33-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCW60-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCW60 # Dev Prefix: T # Gate count = 1 # DEF BCW60-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCW60-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCW71-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCW71 # Dev Prefix: T # Gate count = 1 # DEF BCW71-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCW71-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCW72-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCW72 # Dev Prefix: T # Gate count = 1 # DEF BCW72-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCW72-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCW81-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCW81 # Dev Prefix: T # Gate count = 1 # DEF BCW81-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCW81-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX19-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCX19 # Dev Prefix: T # Gate count = 1 # DEF BCX19-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX19-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX20-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCX20 # Dev Prefix: T # Gate count = 1 # DEF BCX20-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX20-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX54-NPN-SOT89-BCE # Package Name: SOT89-BCE # Dev Tech: BCX54 # Dev Prefix: T # Gate count = 1 # DEF BCX54-NPN-SOT89-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX54-NPN-SOT89-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX55-NPN-SOT89-BCE # Package Name: SOT89-BCE # Dev Tech: BCX55 # Dev Prefix: T # Gate count = 1 # DEF BCX55-NPN-SOT89-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX55-NPN-SOT89-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX56-NPN-SOT89-BCE # Package Name: SOT89-BCE # Dev Tech: BCX56 # Dev Prefix: T # Gate count = 1 # DEF BCX56-NPN-SOT89-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX56-NPN-SOT89-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX59-NPN-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BCX59 # Dev Prefix: T # Gate count = 1 # DEF BCX59-NPN-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX59-NPN-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX70-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BCX70 # Dev Prefix: T # Gate count = 1 # DEF BCX70-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX70-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX70SMD # Package Name: SOT23 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BCX70SMD T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCX70SMD" -400 200 50 H V L B F2 "transistor-SOT23" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCX79-PNP-TO92-EBC # Package Name: TO92-EBC # Dev Tech: BCX79 # Dev Prefix: T # Gate count = 1 # DEF BCX79-PNP-TO92-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BCX79-PNP-TO92-EBC" -400 200 50 H V L B F2 "transistor-TO92-EBC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY58-IX-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BCY58-IX # Dev Prefix: T # Gate count = 1 # DEF BCY58-IX-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCY58-IX-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY58-VIII-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BCY58-VIII # Dev Prefix: T # Gate count = 1 # DEF BCY58-VIII-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCY58-VIII-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY59 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BCY59 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCY59" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY59-VII-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BCY59-VII # Dev Prefix: T # Gate count = 1 # DEF BCY59-VII-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCY59-VII-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY59-VIII-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BCY59-VIII # Dev Prefix: T # Gate count = 1 # DEF BCY59-VIII-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCY59-VIII-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY59-X-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BCY59-X # Dev Prefix: T # Gate count = 1 # DEF BCY59-X-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCY59-X-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY66 # Package Name: TO18 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BCY66 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BCY66" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY70-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BCY70 # Dev Prefix: T # Gate count = 1 # DEF BCY70-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BCY70-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY79-IX-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BCY79-IX # Dev Prefix: T # Gate count = 1 # DEF BCY79-IX-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BCY79-IX-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY79-VII-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BCY79-VII # Dev Prefix: T # Gate count = 1 # DEF BCY79-VII-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BCY79-VII-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BCY79-VIII-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BCY79-VIII # Dev Prefix: T # Gate count = 1 # DEF BCY79-VIII-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BCY79-VIII-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD127 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD127 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD127" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD139 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD139 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD139" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD235 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD235 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD235" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD239 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD239 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD239" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD243 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD243 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD243" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD244 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD244 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BD244" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD249 # Package Name: TOP3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD249 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD249" -400 200 50 H V L B F2 "transistor-TOP3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD303 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD303 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD303" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD535 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD535 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD535" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD647 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD647 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BD647" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD649 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD649 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BD649" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD677 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD677 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BD677" -160 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 3 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 1 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD705 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD705 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD705" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD787 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD787 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD787" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD795 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD795 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD795" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BD865 # Package Name: TO202 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BD865 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BD865" -400 200 50 H V L B F2 "transistor-TO202" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDV65 # Package Name: SOT93 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDV65 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BDV65" -160 200 50 H V L B F2 "transistor-SOT93" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDW73 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDW73 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BDW73" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDX53 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDX53 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BDX53" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDX54 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDX54 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BDX54" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDX67 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDX67 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN-DAR2 F0 "T" -250 300 50 H V L B F1 "BDX67" -260 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 133 -142 P 2 1 0 0 190 -190 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 190 -190 P 2 1 0 0 190 -190 175 -180 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 70 -90 P 2 1 0 0 70 -90 55 -75 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 200 100 D 40 40 1 1 P X C@1 C/ 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDX87 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDX87 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN-DAR2 F0 "T" -250 300 50 H V L B F1 "BDX87" -260 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 133 -142 P 2 1 0 0 190 -190 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 190 -190 P 2 1 0 0 190 -190 175 -180 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 70 -90 P 2 1 0 0 70 -90 55 -75 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 200 100 D 40 40 1 1 P X C@1 C/ 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDY56 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDY56 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BDY56" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDY58 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDY58 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BDY58" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDY92 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDY92 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BDY92" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BDY93 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BDY93 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BDY93" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF199 # Package Name: TO92 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BF199 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF199" -400 200 50 H V L B F2 "transistor-TO92" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF199-NPN-TO92-BEC # Package Name: TO92-BEC # Dev Tech: BF199 # Dev Prefix: T # Gate count = 1 # DEF BF199-NPN-TO92-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF199-NPN-TO92-BEC" -400 200 50 H V L B F2 "transistor-TO92-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF224-NPN-TO92-BEC # Package Name: TO92-BEC # Dev Tech: BF224 # Dev Prefix: T # Gate count = 1 # DEF BF224-NPN-TO92-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF224-NPN-TO92-BEC" -400 200 50 H V L B F2 "transistor-TO92-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF240-NPN-TO92-BEC # Package Name: TO92-BEC # Dev Tech: BF240 # Dev Prefix: T # Gate count = 1 # DEF BF240-NPN-TO92-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF240-NPN-TO92-BEC" -400 200 50 H V L B F2 "transistor-TO92-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF259 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BF259 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF259" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF374-NPN-TO92-CEB # Package Name: TO92-CEB # Dev Tech: BF374 # Dev Prefix: T # Gate count = 1 # DEF BF374-NPN-TO92-CEB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF374-NPN-TO92-CEB" -400 200 50 H V L B F2 "transistor-TO92-CEB" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF391-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: BF391 # Dev Prefix: T # Gate count = 1 # DEF BF391-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF391-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF393-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: BF393 # Dev Prefix: T # Gate count = 1 # DEF BF393-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF393-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF420-NPN-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BF420 # Dev Prefix: T # Gate count = 1 # DEF BF420-NPN-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF420-NPN-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF421-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BF421 # Dev Prefix: T # Gate count = 1 # DEF BF421-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF421-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF422-NPN-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BF422 # Dev Prefix: T # Gate count = 1 # DEF BF422-NPN-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF422-NPN-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF423-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: BF423 # Dev Prefix: T # Gate count = 1 # DEF BF423-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF423-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF459 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BF459 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF459" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF493S-PNP-TO92-CBE # Package Name: TO92-CBE # Dev Tech: BF493S # Dev Prefix: T # Gate count = 1 # DEF BF493S-PNP-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF493S-PNP-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF494-PNP-TO92-CEB # Package Name: TO92-CEB # Dev Tech: BF494 # Dev Prefix: T # Gate count = 1 # DEF BF494-PNP-TO92-CEB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF494-PNP-TO92-CEB" -400 200 50 H V L B F2 "transistor-TO92-CEB" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF495-PNP-TO92-CEB # Package Name: TO92-CEB # Dev Tech: BF495 # Dev Prefix: T # Gate count = 1 # DEF BF495-PNP-TO92-CEB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF495-PNP-TO92-CEB" -400 200 50 H V L B F2 "transistor-TO92-CEB" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF621-PNP-SOT98-BCE # Package Name: SOT89-BCE # Dev Tech: BF621 # Dev Prefix: T # Gate count = 1 # DEF BF621-PNP-SOT98-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF621-PNP-SOT98-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF622-NPN-SOT89-BCE # Package Name: SOT89-BCE # Dev Tech: BF622 # Dev Prefix: T # Gate count = 1 # DEF BF622-NPN-SOT89-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF622-NPN-SOT89-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF623-PNP-SOT98-BCE # Package Name: SOT89-BCE # Dev Tech: BF623 # Dev Prefix: T # Gate count = 1 # DEF BF623-PNP-SOT98-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF623-PNP-SOT98-BCE" -400 200 50 H V L B F2 "transistor-SOT89-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF820-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BF820 # Dev Prefix: T # Gate count = 1 # DEF BF820-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF820-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF821-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BF821 # Dev Prefix: T # Gate count = 1 # DEF BF821-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF821-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF822-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BF822 # Dev Prefix: T # Gate count = 1 # DEF BF822-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF822-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF823-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BF823 # Dev Prefix: T # Gate count = 1 # DEF BF823-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BF823-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF844-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: BF844 # Dev Prefix: T # Gate count = 1 # DEF BF844-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF844-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF859 # Package Name: TO202 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BF859 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF859" -400 200 50 H V L B F2 "transistor-TO202" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BF959-NPN-TO92-CEB # Package Name: TO92-CEB # Dev Tech: BF959 # Dev Prefix: T # Gate count = 1 # DEF BF959-NPN-TO92-CEB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BF959-NPN-TO92-CEB" -400 200 50 H V L B F2 "transistor-TO92-CEB" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFR53-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFR53 # Dev Prefix: T # Gate count = 1 # DEF BFR53-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFR53-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFR92-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFR92 # Dev Prefix: T # Gate count = 1 # DEF BFR92-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFR92-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFR92A-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFR92A # Dev Prefix: T # Gate count = 1 # DEF BFR92A-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFR92A-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFR93-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFR93 # Dev Prefix: T # Gate count = 1 # DEF BFR93-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFR93-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFR93A-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFR93A # Dev Prefix: T # Gate count = 1 # DEF BFR93A-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFR93A-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFR96-NPN-SOT-37 # Package Name: SOT37 # Dev Tech: BFR96 # Dev Prefix: T # Gate count = 1 # DEF BFR96-NPN-SOT-37 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFR96-NPN-SOT-37" -400 200 50 H V L B F2 "transistor-SOT37" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 2 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFS17-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFS17 # Dev Prefix: T # Gate count = 1 # DEF BFS17-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFS17-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFS19-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFS19 # Dev Prefix: T # Gate count = 1 # DEF BFS19-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFS19-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFS20-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFS20 # Dev Prefix: T # Gate count = 1 # DEF BFS20-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFS20-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFT25-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BFT25 # Dev Prefix: T # Gate count = 1 # DEF BFT25-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFT25-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFX59 # Package Name: TO72 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BFX59 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFX59" -400 200 50 H V L B F2 "transistor-TO72" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BFY50-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BFY50 # Dev Prefix: T # Gate count = 1 # DEF BFY50-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BFY50-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSR12-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BSR12 # Dev Prefix: T # Gate count = 1 # DEF BSR12-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSR12-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSR13-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BSR13 # Dev Prefix: T # Gate count = 1 # DEF BSR13-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSR13-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSR14-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BSR14 # Dev Prefix: T # Gate count = 1 # DEF BSR14-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSR14-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS51 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BSS51 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BSS51" -160 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 2 -100 0 100 R 40 40 1 1 P X C 3 200 100 100 D 40 40 1 1 P X E 1 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS52 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BSS52 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BSS52" -160 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 2 -100 0 100 R 40 40 1 1 P X C 3 200 100 100 D 40 40 1 1 P X E 1 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS71-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BSS71 # Dev Prefix: T # Gate count = 1 # DEF BSS71-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSS71-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS72-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BSS72 # Dev Prefix: T # Gate count = 1 # DEF BSS72-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSS72-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS73-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BSS73 # Dev Prefix: T # Gate count = 1 # DEF BSS73-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSS73-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS74-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BSS74 # Dev Prefix: T # Gate count = 1 # DEF BSS74-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BSS74-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS75-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BSS75 # Dev Prefix: T # Gate count = 1 # DEF BSS75-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BSS75-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSS76-PNP-TO18-EBC # Package Name: TO18 # Dev Tech: BSS76 # Dev Prefix: T # Gate count = 1 # DEF BSS76-PNP-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "BSS76-PNP-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSV52LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: BSV52LT1 # Dev Prefix: T # Gate count = 1 # DEF BSV52LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSV52LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX20-NPN-TO18-EBC # Package Name: TO18 # Dev Tech: BSX20 # Dev Prefix: T # Gate count = 1 # DEF BSX20-NPN-TO18-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX20-NPN-TO18-EBC" -400 200 50 H V L B F2 "transistor-TO18" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX45-16-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BSX45-16 # Dev Prefix: T # Gate count = 1 # DEF BSX45-16-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX45-16-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX46-10 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BSX46-10 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX46-10" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX46-10-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BSX46-10 # Dev Prefix: T # Gate count = 1 # DEF BSX46-10-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX46-10-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX46-16-NPN-TO39-EBC # Package Name: TO39 # Dev Tech: BSX46-16 # Dev Prefix: T # Gate count = 1 # DEF BSX46-16-NPN-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX46-16-NPN-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX47 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BSX47 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX47" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX62 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BSX62 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX62" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSX63 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BSX63 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSX63" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BSY34 # Package Name: TO39 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BSY34 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BSY34" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BU111 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BU111 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BU111" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BU205 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BU205 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BU205" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BU208 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BU208 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BU208" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BU807 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BU807 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "BU807" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUW74 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUW74 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BUW74" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUW75 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUW75 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BUW75" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUX24 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUX24 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BUX24" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUX37 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUX37 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN-DAR2 F0 "T" -250 300 50 H V L B F1 "BUX37" -260 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 133 -142 P 2 1 0 0 190 -190 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 190 -190 P 2 1 0 0 190 -190 175 -180 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 70 -90 P 2 1 0 0 70 -90 55 -75 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 200 100 D 40 40 1 1 P X C@1 C/ 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUX40 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUX40 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BUX40" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUX80 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUX80 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "BUX80" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUX84 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUX84 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BUX84" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: BUX85 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF BUX85 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "BUX85" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: CA3081 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: T # Gate count = 7 # DEF CA3081 T 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: NPN-PAD F0 "T" -400 300 50 H V L B F1 "CA3081" -400 200 50 H V L B F2 "transistor-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 16 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 15 100 -200 100 U 40 40 1 1 P # Gate Name: B # Symbol Name: NPN-C P 2 2 0 0 100 100 20 60 P 2 2 0 0 60 -80 12 -56 P 2 2 0 0 100 -120 100 -100 P 2 2 0 0 70 -60 100 -100 P 2 2 0 0 100 -100 50 -100 P 2 2 0 0 50 -100 70 -60 P 2 2 0 0 60 -95 90 -95 P 2 2 0 0 90 -95 70 -70 P 2 2 0 0 70 -70 60 -90 P 2 2 0 0 60 -90 75 -90 P 2 2 0 0 75 -90 70 -80 S -10 -100 20 100 2 1 0 F X B 3 -100 0 100 R 40 40 2 1 P X C 2 100 200 100 D 40 40 2 1 P # Gate Name: C # Symbol Name: NPN-C P 2 3 0 0 100 100 20 60 P 2 3 0 0 60 -80 12 -56 P 2 3 0 0 100 -120 100 -100 P 2 3 0 0 70 -60 100 -100 P 2 3 0 0 100 -100 50 -100 P 2 3 0 0 50 -100 70 -60 P 2 3 0 0 60 -95 90 -95 P 2 3 0 0 90 -95 70 -70 P 2 3 0 0 70 -70 60 -90 P 2 3 0 0 60 -90 75 -90 P 2 3 0 0 75 -90 70 -80 S -10 -100 20 100 3 1 0 F X B 13 -100 0 100 R 40 40 3 1 P X C 14 100 200 100 D 40 40 3 1 P # Gate Name: D # Symbol Name: NPN-C P 2 4 0 0 100 100 20 60 P 2 4 0 0 60 -80 12 -56 P 2 4 0 0 100 -120 100 -100 P 2 4 0 0 70 -60 100 -100 P 2 4 0 0 100 -100 50 -100 P 2 4 0 0 50 -100 70 -60 P 2 4 0 0 60 -95 90 -95 P 2 4 0 0 90 -95 70 -70 P 2 4 0 0 70 -70 60 -90 P 2 4 0 0 60 -90 75 -90 P 2 4 0 0 75 -90 70 -80 S -10 -100 20 100 4 1 0 F X B 11 -100 0 100 R 40 40 4 1 P X C 12 100 200 100 D 40 40 4 1 P # Gate Name: E # Symbol Name: NPN-C P 2 5 0 0 100 100 20 60 P 2 5 0 0 60 -80 12 -56 P 2 5 0 0 100 -120 100 -100 P 2 5 0 0 70 -60 100 -100 P 2 5 0 0 100 -100 50 -100 P 2 5 0 0 50 -100 70 -60 P 2 5 0 0 60 -95 90 -95 P 2 5 0 0 90 -95 70 -70 P 2 5 0 0 70 -70 60 -90 P 2 5 0 0 60 -90 75 -90 P 2 5 0 0 75 -90 70 -80 S -10 -100 20 100 5 1 0 F X B 6 -100 0 100 R 40 40 5 1 P X C 4 100 200 100 D 40 40 5 1 P # Gate Name: F # Symbol Name: NPN-C P 2 6 0 0 100 100 20 60 P 2 6 0 0 60 -80 12 -56 P 2 6 0 0 100 -120 100 -100 P 2 6 0 0 70 -60 100 -100 P 2 6 0 0 100 -100 50 -100 P 2 6 0 0 50 -100 70 -60 P 2 6 0 0 60 -95 90 -95 P 2 6 0 0 90 -95 70 -70 P 2 6 0 0 70 -70 60 -90 P 2 6 0 0 60 -90 75 -90 P 2 6 0 0 75 -90 70 -80 S -10 -100 20 100 6 1 0 F X B 10 -100 0 100 R 40 40 6 1 P X C 9 100 200 100 D 40 40 6 1 P # Gate Name: G # Symbol Name: NPN-C P 2 7 0 0 100 100 20 60 P 2 7 0 0 60 -80 12 -56 P 2 7 0 0 100 -120 100 -100 P 2 7 0 0 70 -60 100 -100 P 2 7 0 0 100 -100 50 -100 P 2 7 0 0 50 -100 70 -60 P 2 7 0 0 60 -95 90 -95 P 2 7 0 0 90 -95 70 -70 P 2 7 0 0 70 -70 60 -90 P 2 7 0 0 60 -90 75 -90 P 2 7 0 0 75 -90 70 -80 S -10 -100 20 100 7 1 0 F X B 8 -100 0 100 R 40 40 7 1 P X C 7 100 200 100 D 40 40 7 1 P ENDDRAW ENDDEF # # Dev Name: CA3081M # Package Name: SO16 # Dev Tech: '' # Dev Prefix: T # Gate count = 7 # DEF CA3081M T 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: NPN-PAD F0 "T" -400 300 50 H V L B F1 "CA3081M" -400 200 50 H V L B F2 "transistor-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 16 -100 0 100 R 40 40 1 1 P X C 1 100 200 100 D 40 40 1 1 P X E 15 100 -200 100 U 40 40 1 1 P # Gate Name: B # Symbol Name: NPN-C P 2 2 0 0 100 100 20 60 P 2 2 0 0 60 -80 12 -56 P 2 2 0 0 100 -120 100 -100 P 2 2 0 0 70 -60 100 -100 P 2 2 0 0 100 -100 50 -100 P 2 2 0 0 50 -100 70 -60 P 2 2 0 0 60 -95 90 -95 P 2 2 0 0 90 -95 70 -70 P 2 2 0 0 70 -70 60 -90 P 2 2 0 0 60 -90 75 -90 P 2 2 0 0 75 -90 70 -80 S -10 -100 20 100 2 1 0 F X B 3 -100 0 100 R 40 40 2 1 P X C 2 100 200 100 D 40 40 2 1 P # Gate Name: C # Symbol Name: NPN-C P 2 3 0 0 100 100 20 60 P 2 3 0 0 60 -80 12 -56 P 2 3 0 0 100 -120 100 -100 P 2 3 0 0 70 -60 100 -100 P 2 3 0 0 100 -100 50 -100 P 2 3 0 0 50 -100 70 -60 P 2 3 0 0 60 -95 90 -95 P 2 3 0 0 90 -95 70 -70 P 2 3 0 0 70 -70 60 -90 P 2 3 0 0 60 -90 75 -90 P 2 3 0 0 75 -90 70 -80 S -10 -100 20 100 3 1 0 F X B 13 -100 0 100 R 40 40 3 1 P X C 14 100 200 100 D 40 40 3 1 P # Gate Name: D # Symbol Name: NPN-C P 2 4 0 0 100 100 20 60 P 2 4 0 0 60 -80 12 -56 P 2 4 0 0 100 -120 100 -100 P 2 4 0 0 70 -60 100 -100 P 2 4 0 0 100 -100 50 -100 P 2 4 0 0 50 -100 70 -60 P 2 4 0 0 60 -95 90 -95 P 2 4 0 0 90 -95 70 -70 P 2 4 0 0 70 -70 60 -90 P 2 4 0 0 60 -90 75 -90 P 2 4 0 0 75 -90 70 -80 S -10 -100 20 100 4 1 0 F X B 11 -100 0 100 R 40 40 4 1 P X C 12 100 200 100 D 40 40 4 1 P # Gate Name: E # Symbol Name: NPN-C P 2 5 0 0 100 100 20 60 P 2 5 0 0 60 -80 12 -56 P 2 5 0 0 100 -120 100 -100 P 2 5 0 0 70 -60 100 -100 P 2 5 0 0 100 -100 50 -100 P 2 5 0 0 50 -100 70 -60 P 2 5 0 0 60 -95 90 -95 P 2 5 0 0 90 -95 70 -70 P 2 5 0 0 70 -70 60 -90 P 2 5 0 0 60 -90 75 -90 P 2 5 0 0 75 -90 70 -80 S -10 -100 20 100 5 1 0 F X B 6 -100 0 100 R 40 40 5 1 P X C 4 100 200 100 D 40 40 5 1 P # Gate Name: F # Symbol Name: NPN-C P 2 6 0 0 100 100 20 60 P 2 6 0 0 60 -80 12 -56 P 2 6 0 0 100 -120 100 -100 P 2 6 0 0 70 -60 100 -100 P 2 6 0 0 100 -100 50 -100 P 2 6 0 0 50 -100 70 -60 P 2 6 0 0 60 -95 90 -95 P 2 6 0 0 90 -95 70 -70 P 2 6 0 0 70 -70 60 -90 P 2 6 0 0 60 -90 75 -90 P 2 6 0 0 75 -90 70 -80 S -10 -100 20 100 6 1 0 F X B 10 -100 0 100 R 40 40 6 1 P X C 9 100 200 100 D 40 40 6 1 P # Gate Name: G # Symbol Name: NPN-C P 2 7 0 0 100 100 20 60 P 2 7 0 0 60 -80 12 -56 P 2 7 0 0 100 -120 100 -100 P 2 7 0 0 70 -60 100 -100 P 2 7 0 0 100 -100 50 -100 P 2 7 0 0 50 -100 70 -60 P 2 7 0 0 60 -95 90 -95 P 2 7 0 0 90 -95 70 -70 P 2 7 0 0 70 -70 60 -90 P 2 7 0 0 60 -90 75 -90 P 2 7 0 0 75 -90 70 -80 S -10 -100 20 100 7 1 0 F X B 8 -100 0 100 R 40 40 7 1 P X C 7 100 200 100 D 40 40 7 1 P ENDDRAW ENDDEF # # Dev Name: CA3082 # Package Name: DIL16 # Dev Tech: '' # Dev Prefix: T # Gate count = 7 # DEF CA3082 T 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: NPN-PAD F0 "T" -400 300 50 H V L B F1 "CA3082" -400 200 50 H V L B F2 "transistor-DIL16" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 16 -100 0 100 R 40 40 1 1 P X C 15 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P # Gate Name: B # Symbol Name: NPN-E P 2 2 0 0 100 100 20 60 P 2 2 0 0 60 -80 12 -56 P 2 2 0 0 100 100 100 130 P 2 2 0 0 70 -60 100 -100 P 2 2 0 0 100 -100 50 -100 P 2 2 0 0 50 -100 70 -60 P 2 2 0 0 60 -95 90 -95 P 2 2 0 0 90 -95 70 -70 P 2 2 0 0 70 -70 60 -90 P 2 2 0 0 60 -90 75 -90 P 2 2 0 0 75 -90 70 -80 S -10 -100 20 100 2 1 0 F X B 3 -100 0 100 R 40 40 2 1 P X E 2 100 -200 100 U 40 40 2 1 P # Gate Name: C # Symbol Name: NPN-E P 2 3 0 0 100 100 20 60 P 2 3 0 0 60 -80 12 -56 P 2 3 0 0 100 100 100 130 P 2 3 0 0 70 -60 100 -100 P 2 3 0 0 100 -100 50 -100 P 2 3 0 0 50 -100 70 -60 P 2 3 0 0 60 -95 90 -95 P 2 3 0 0 90 -95 70 -70 P 2 3 0 0 70 -70 60 -90 P 2 3 0 0 60 -90 75 -90 P 2 3 0 0 75 -90 70 -80 S -10 -100 20 100 3 1 0 F X B 13 -100 0 100 R 40 40 3 1 P X E 14 100 -200 100 U 40 40 3 1 P # Gate Name: D # Symbol Name: NPN-E P 2 4 0 0 100 100 20 60 P 2 4 0 0 60 -80 12 -56 P 2 4 0 0 100 100 100 130 P 2 4 0 0 70 -60 100 -100 P 2 4 0 0 100 -100 50 -100 P 2 4 0 0 50 -100 70 -60 P 2 4 0 0 60 -95 90 -95 P 2 4 0 0 90 -95 70 -70 P 2 4 0 0 70 -70 60 -90 P 2 4 0 0 60 -90 75 -90 P 2 4 0 0 75 -90 70 -80 S -10 -100 20 100 4 1 0 F X B 11 -100 0 100 R 40 40 4 1 P X E 12 100 -200 100 U 40 40 4 1 P # Gate Name: E # Symbol Name: NPN-E P 2 5 0 0 100 100 20 60 P 2 5 0 0 60 -80 12 -56 P 2 5 0 0 100 100 100 130 P 2 5 0 0 70 -60 100 -100 P 2 5 0 0 100 -100 50 -100 P 2 5 0 0 50 -100 70 -60 P 2 5 0 0 60 -95 90 -95 P 2 5 0 0 90 -95 70 -70 P 2 5 0 0 70 -70 60 -90 P 2 5 0 0 60 -90 75 -90 P 2 5 0 0 75 -90 70 -80 S -10 -100 20 100 5 1 0 F X B 6 -100 0 100 R 40 40 5 1 P X E 4 100 -200 100 U 40 40 5 1 P # Gate Name: F # Symbol Name: NPN-E P 2 6 0 0 100 100 20 60 P 2 6 0 0 60 -80 12 -56 P 2 6 0 0 100 100 100 130 P 2 6 0 0 70 -60 100 -100 P 2 6 0 0 100 -100 50 -100 P 2 6 0 0 50 -100 70 -60 P 2 6 0 0 60 -95 90 -95 P 2 6 0 0 90 -95 70 -70 P 2 6 0 0 70 -70 60 -90 P 2 6 0 0 60 -90 75 -90 P 2 6 0 0 75 -90 70 -80 S -10 -100 20 100 6 1 0 F X B 8 -100 0 100 R 40 40 6 1 P X E 7 100 -200 100 U 40 40 6 1 P # Gate Name: G # Symbol Name: NPN-E P 2 7 0 0 100 100 20 60 P 2 7 0 0 60 -80 12 -56 P 2 7 0 0 100 100 100 130 P 2 7 0 0 70 -60 100 -100 P 2 7 0 0 100 -100 50 -100 P 2 7 0 0 50 -100 70 -60 P 2 7 0 0 60 -95 90 -95 P 2 7 0 0 90 -95 70 -70 P 2 7 0 0 70 -70 60 -90 P 2 7 0 0 60 -90 75 -90 P 2 7 0 0 75 -90 70 -80 S -10 -100 20 100 7 1 0 F X B 10 -100 0 100 R 40 40 7 1 P X E 9 100 -200 100 U 40 40 7 1 P ENDDRAW ENDDEF # # Dev Name: CA3082M # Package Name: SO16 # Dev Tech: '' # Dev Prefix: T # Gate count = 7 # DEF CA3082M T 0 40 Y Y 7 L N # Gate Name: A # Symbol Name: NPN-PAD F0 "T" -400 300 50 H V L B F1 "CA3082M" -400 200 50 H V L B F2 "transistor-SO16" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 16 -100 0 100 R 40 40 1 1 P X C 15 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P # Gate Name: B # Symbol Name: NPN-E P 2 2 0 0 100 100 20 60 P 2 2 0 0 60 -80 12 -56 P 2 2 0 0 100 100 100 130 P 2 2 0 0 70 -60 100 -100 P 2 2 0 0 100 -100 50 -100 P 2 2 0 0 50 -100 70 -60 P 2 2 0 0 60 -95 90 -95 P 2 2 0 0 90 -95 70 -70 P 2 2 0 0 70 -70 60 -90 P 2 2 0 0 60 -90 75 -90 P 2 2 0 0 75 -90 70 -80 S -10 -100 20 100 2 1 0 F X B 3 -100 0 100 R 40 40 2 1 P X E 2 100 -200 100 U 40 40 2 1 P # Gate Name: C # Symbol Name: NPN-E P 2 3 0 0 100 100 20 60 P 2 3 0 0 60 -80 12 -56 P 2 3 0 0 100 100 100 130 P 2 3 0 0 70 -60 100 -100 P 2 3 0 0 100 -100 50 -100 P 2 3 0 0 50 -100 70 -60 P 2 3 0 0 60 -95 90 -95 P 2 3 0 0 90 -95 70 -70 P 2 3 0 0 70 -70 60 -90 P 2 3 0 0 60 -90 75 -90 P 2 3 0 0 75 -90 70 -80 S -10 -100 20 100 3 1 0 F X B 13 -100 0 100 R 40 40 3 1 P X E 14 100 -200 100 U 40 40 3 1 P # Gate Name: D # Symbol Name: NPN-E P 2 4 0 0 100 100 20 60 P 2 4 0 0 60 -80 12 -56 P 2 4 0 0 100 100 100 130 P 2 4 0 0 70 -60 100 -100 P 2 4 0 0 100 -100 50 -100 P 2 4 0 0 50 -100 70 -60 P 2 4 0 0 60 -95 90 -95 P 2 4 0 0 90 -95 70 -70 P 2 4 0 0 70 -70 60 -90 P 2 4 0 0 60 -90 75 -90 P 2 4 0 0 75 -90 70 -80 S -10 -100 20 100 4 1 0 F X B 11 -100 0 100 R 40 40 4 1 P X E 12 100 -200 100 U 40 40 4 1 P # Gate Name: E # Symbol Name: NPN-E P 2 5 0 0 100 100 20 60 P 2 5 0 0 60 -80 12 -56 P 2 5 0 0 100 100 100 130 P 2 5 0 0 70 -60 100 -100 P 2 5 0 0 100 -100 50 -100 P 2 5 0 0 50 -100 70 -60 P 2 5 0 0 60 -95 90 -95 P 2 5 0 0 90 -95 70 -70 P 2 5 0 0 70 -70 60 -90 P 2 5 0 0 60 -90 75 -90 P 2 5 0 0 75 -90 70 -80 S -10 -100 20 100 5 1 0 F X B 6 -100 0 100 R 40 40 5 1 P X E 4 100 -200 100 U 40 40 5 1 P # Gate Name: F # Symbol Name: NPN-E P 2 6 0 0 100 100 20 60 P 2 6 0 0 60 -80 12 -56 P 2 6 0 0 100 100 100 130 P 2 6 0 0 70 -60 100 -100 P 2 6 0 0 100 -100 50 -100 P 2 6 0 0 50 -100 70 -60 P 2 6 0 0 60 -95 90 -95 P 2 6 0 0 90 -95 70 -70 P 2 6 0 0 70 -70 60 -90 P 2 6 0 0 60 -90 75 -90 P 2 6 0 0 75 -90 70 -80 S -10 -100 20 100 6 1 0 F X B 8 -100 0 100 R 40 40 6 1 P X E 7 100 -200 100 U 40 40 6 1 P # Gate Name: G # Symbol Name: NPN-E P 2 7 0 0 100 100 20 60 P 2 7 0 0 60 -80 12 -56 P 2 7 0 0 100 100 100 130 P 2 7 0 0 70 -60 100 -100 P 2 7 0 0 100 -100 50 -100 P 2 7 0 0 50 -100 70 -60 P 2 7 0 0 60 -95 90 -95 P 2 7 0 0 90 -95 70 -70 P 2 7 0 0 70 -70 60 -90 P 2 7 0 0 60 -90 75 -90 P 2 7 0 0 75 -90 70 -80 S -10 -100 20 100 7 1 0 F X B 10 -100 0 100 R 40 40 7 1 P X E 9 100 -200 100 U 40 40 7 1 P ENDDRAW ENDDEF # # Dev Name: CMLT5078E # Package Name: SOT563 # Dev Tech: '' # Dev Prefix: T # Gate count = 2 # DEF CMLT5078E T 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "CMLT5078E" -400 200 50 H V L B F2 "transistor-SOT563" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 6 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P # Gate Name: B # Symbol Name: PNP P 2 2 0 0 82 66 62 102 P 2 2 0 0 62 102 20 58 P 2 2 0 0 20 58 82 66 P 2 2 0 0 100 100 71 83 P 2 2 0 0 100 -100 20 -60 P 2 2 0 0 75 70 60 95 P 2 2 0 0 60 95 30 65 P 2 2 0 0 30 65 70 70 P 2 2 0 0 70 70 60 85 P 2 2 0 0 60 85 45 75 P 2 2 0 0 45 75 60 75 S -10 -100 20 100 2 1 0 F X B 5 -100 0 100 R 40 40 2 1 P X C 3 100 -200 100 U 40 40 2 1 P X E 4 100 200 100 D 40 40 2 1 P ENDDRAW ENDDEF # # Dev Name: CMLT5087E # Package Name: SOT563 # Dev Tech: '' # Dev Prefix: T # Gate count = 2 # DEF CMLT5087E T 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "CMLT5087E" -400 200 50 H V L B F2 "transistor-SOT563" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 6 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P # Gate Name: B # Symbol Name: PNP P 2 2 0 0 82 66 62 102 P 2 2 0 0 62 102 20 58 P 2 2 0 0 20 58 82 66 P 2 2 0 0 100 100 71 83 P 2 2 0 0 100 -100 20 -60 P 2 2 0 0 75 70 60 95 P 2 2 0 0 60 95 30 65 P 2 2 0 0 30 65 70 70 P 2 2 0 0 70 70 60 85 P 2 2 0 0 60 85 45 75 P 2 2 0 0 45 75 60 75 S -10 -100 20 100 2 1 0 F X B 5 -100 0 100 R 40 40 2 1 P X C 3 100 -200 100 U 40 40 2 1 P X E 4 100 200 100 D 40 40 2 1 P ENDDRAW ENDDEF # # Dev Name: CMLT5088E # Package Name: SOT563 # Dev Tech: '' # Dev Prefix: T # Gate count = 2 # DEF CMLT5088E T 0 40 Y Y 2 L N # Gate Name: A # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "CMLT5088E" -400 200 50 H V L B F2 "transistor-SOT563" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 6 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P # Gate Name: B # Symbol Name: NPN P 2 2 0 0 100 100 20 60 P 2 2 0 0 70 -60 100 -100 P 2 2 0 0 100 -100 50 -100 P 2 2 0 0 50 -100 70 -60 P 2 2 0 0 60 -80 12 -56 P 2 2 0 0 60 -95 90 -95 P 2 2 0 0 90 -95 70 -70 P 2 2 0 0 70 -70 60 -90 P 2 2 0 0 60 -90 75 -90 P 2 2 0 0 75 -90 70 -80 S -10 -100 20 100 2 1 0 F X B 5 -100 0 100 R 40 40 2 1 P X C 3 100 200 100 D 40 40 2 1 P X E 4 100 -200 100 U 40 40 2 1 P ENDDRAW ENDDEF # # Dev Name: MJ413 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJ413 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN2 F0 "T" -400 100 50 H V L B F1 "MJ413" -400 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 62 -56 100 -100 P 2 1 0 0 100 -100 42 -96 P 2 1 0 0 42 -96 62 -56 P 2 1 0 0 52 -76 4 -52 P 2 1 0 0 90 -95 65 -65 P 2 1 0 0 65 -65 50 -90 P 2 1 0 0 50 -90 85 -95 P 2 1 0 0 85 -95 65 -75 P 2 1 0 0 65 -75 60 -85 P 2 1 0 0 60 -85 70 -85 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X C@1 C/ 100 100 100 U 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJ1001 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJ1001 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN-DAR2 F0 "T" -250 300 50 H V L B F1 "MJ1001" -260 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 133 -142 P 2 1 0 0 190 -190 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 190 -190 P 2 1 0 0 190 -190 175 -180 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 70 -90 P 2 1 0 0 70 -90 55 -75 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 200 100 D 40 40 1 1 P X C@1 C/ 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJ3001 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJ3001 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN-DAR2 F0 "T" -250 300 50 H V L B F1 "MJ3001" -260 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 133 -142 P 2 1 0 0 190 -190 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 190 -190 P 2 1 0 0 190 -190 175 -180 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 70 -90 P 2 1 0 0 70 -90 55 -75 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 200 100 D 40 40 1 1 P X C@1 C/ 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJ10007 # Package Name: TO3 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJ10007 T 0 40 Y Y 1 L N # Gate Name: A # Symbol Name: NPN-DAR2 F0 "T" -250 300 50 H V L B F1 "MJ10007" -260 200 50 H V L B F2 "transistor-TO3" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 133 -142 P 2 1 0 0 190 -190 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 190 -190 P 2 1 0 0 190 -190 175 -180 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 70 -90 P 2 1 0 0 70 -90 55 -75 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 200 100 D 40 40 1 1 P X C@1 C/ 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJD31 # Package Name: DPAK # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJD31 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MJD31" -400 200 50 H V L B F2 "transistor-DPAK" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 4 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJD31C # Package Name: DPAK # Dev Tech: C # Dev Prefix: T # Gate count = 1 # DEF MJD31C T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MJD31C" -400 200 50 H V L B F2 "transistor-DPAK" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 4 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJD32 # Package Name: DPAK # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJD32 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MJD32" -400 200 50 H V L B F2 "transistor-DPAK" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 4 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJD32C # Package Name: DPAK # Dev Tech: C # Dev Prefix: T # Gate count = 1 # DEF MJD32C T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MJD32C" -400 200 50 H V L B F2 "transistor-DPAK" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 4 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJE181 # Package Name: TO225AA # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJE181 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MJE181" -400 200 50 H V L B F2 "transistor-TO225AA" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJE182 # Package Name: TO225AA # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJE182 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MJE182" -400 200 50 H V L B F2 "transistor-TO225AA" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJE340 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJE340 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MJE340" -400 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 3 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MJE801 # Package Name: TO126 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF MJE801 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "MJE801" -160 200 50 H V L B F2 "transistor-TO126" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 3 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 1 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MM4001-PNP-TO39-EBC # Package Name: TO39 # Dev Tech: MM4001 # Dev Prefix: T # Gate count = 1 # DEF MM4001-PNP-TO39-EBC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MM4001-PNP-TO39-EBC" -400 200 50 H V L B F2 "transistor-TO39" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 -200 100 U 40 40 1 1 P X E 1 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT540LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT540LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT540LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBT540LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT918LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT918LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT918LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT918LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT2222ALT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT2222ALT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT2222ALT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT2222ALT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT2369LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT2369LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT2369LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT2369LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT2484LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT2484LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT2484LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT2484LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT2907ALT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT2907ALT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT2907ALT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBT2907ALT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT3640LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT3640LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT3640LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBT3640LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT3904LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT3904LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT3904LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT3904LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT3906LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT3906LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT3906LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBT3906LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT4401LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT4401LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT4401LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT4401LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT4403LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT4403LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT4403LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBT4403LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT5551LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT5551LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT5551LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT5551LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT6429LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT6429LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT6429LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT6429LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT6517LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT6517LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT6517LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBT6517LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBT6520LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBT6520LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBT6520LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBT6520LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTA13LT1-NPN_DARL-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTA13LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTA13LT1-NPN_DARL-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "MMBTA13LT1-NPN_DARL-SOT23-BEC" -160 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTA14LT1-NPN_DARL-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTA14LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTA14LT1-NPN_DARL-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "MMBTA14LT1-NPN_DARL-SOT23-BEC" -160 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 100 100 D 40 40 1 1 P X E E 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTA42LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTA42LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTA42LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBTA42LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTA64LT1-PNP_DARL-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTA64LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTA64LT1-PNP_DARL-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP-DAR F0 "T" -300 300 50 H V L B F1 "MMBTA64LT1-PNP_DARL-SOT23-BEC" -300 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 200 -100 80 -100 P 2 1 0 0 80 -100 20 -50 P 2 1 0 0 200 0 135 50 P 2 1 0 0 53 88 20 45 P 2 1 0 0 73 58 53 88 P 2 1 0 0 20 45 73 58 P 2 1 0 0 63 72 101 97 P 2 1 0 0 25 50 55 85 P 2 1 0 0 55 85 70 60 P 2 1 0 0 70 60 30 50 P 2 1 0 0 30 50 55 80 P 2 1 0 0 55 80 65 65 P 2 1 0 0 65 65 35 55 P 2 1 0 0 35 55 55 75 P 2 1 0 0 55 75 55 70 P 2 1 0 0 145 150 188 165 P 2 1 0 0 165 190 145 150 P 2 1 0 0 188 165 165 190 P 2 1 0 0 176 177 197 197 P 2 1 0 0 150 155 165 185 P 2 1 0 0 165 185 185 165 P 2 1 0 0 185 165 155 155 P 2 1 0 0 155 155 165 180 P 2 1 0 0 165 180 180 165 P 2 1 0 0 180 165 160 160 P 2 1 0 0 160 160 165 170 P 2 1 0 0 165 170 170 170 P 2 1 0 0 200 -100 200 0 P 2 1 0 0 105 100 115 100 S -10 -100 20 100 1 1 0 F S 115 0 145 200 1 1 0 F C 200 -100 15 1 1 0 N X B B -100 0 100 R 40 40 1 1 P X C C 200 -200 100 U 40 40 1 1 P X E E 200 300 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTA92LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTA92LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTA92LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBTA92LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTH10LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTH10LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTH10LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBTH10LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTH24LT1-NPN-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTH24LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTH24LT1-NPN-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMBTH24LT1-NPN-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMBTH81LT1-PNP-SOT23-BEC # Package Name: SOT23-BEC # Dev Tech: MMBTH81LT1 # Dev Prefix: T # Gate count = 1 # DEF MMBTH81LT1-PNP-SOT23-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMBTH81LT1-PNP-SOT23-BEC" -400 200 50 H V L B F2 "transistor-SOT23-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2111LT1-PNP-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2111LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2111LT1-PNP-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMUN2111LT1-PNP-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2112LT1-PNP-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2112LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2112LT1-PNP-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMUN2112LT1-PNP-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2113LT1-PNP-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2113LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2113LT1-PNP-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMUN2113LT1-PNP-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2114LT1-PNP-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2114LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2114LT1-PNP-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MMUN2114LT1-PNP-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2211LT1-NPN-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2211LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2211LT1-NPN-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMUN2211LT1-NPN-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2212LT1-NPN-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2212LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2212LT1-NPN-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMUN2212LT1-NPN-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2213LT1-NPN-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2213LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2213LT1-NPN-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMUN2213LT1-NPN-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MMUN2214LT1-NPN-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MMUN2214LT1 # Dev Prefix: T # Gate count = 1 # DEF MMUN2214LT1-NPN-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MMUN2214LT1-NPN-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPHS10-NPN-TO92-CEB # Package Name: TO92-CEB # Dev Tech: MPHS10 # Dev Prefix: T # Gate count = 1 # DEF MPHS10-NPN-TO92-CEB T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPHS10-NPN-TO92-CEB" -400 200 50 H V L B F2 "transistor-TO92-CEB" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPS2222A-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPS2222A # Dev Prefix: T # Gate count = 1 # DEF MPS2222A-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPS2222A-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPS2907A-PNP-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPS2907A # Dev Prefix: T # Gate count = 1 # DEF MPS2907A-PNP-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MPS2907A-PNP-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA06-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA06 # Dev Prefix: T # Gate count = 1 # DEF MPSA06-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA06-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA13-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA13 # Dev Prefix: T # Gate count = 1 # DEF MPSA13-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA13-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA14-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA14 # Dev Prefix: T # Gate count = 1 # DEF MPSA14-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA14-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA18-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA18 # Dev Prefix: T # Gate count = 1 # DEF MPSA18-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA18-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA29-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA29 # Dev Prefix: T # Gate count = 1 # DEF MPSA29-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA29-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA42-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA42 # Dev Prefix: T # Gate count = 1 # DEF MPSA42-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA42-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA44-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA44 # Dev Prefix: T # Gate count = 1 # DEF MPSA44-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA44-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA56-PNP-TO92-BCE # Package Name: TO92-BCE # Dev Tech: MPSA56 # Dev Prefix: T # Gate count = 1 # DEF MPSA56-PNP-TO92-BCE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MPSA56-PNP-TO92-BCE" -400 200 50 H V L B F2 "transistor-TO92-BCE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA63-PNP-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA63 # Dev Prefix: T # Gate count = 1 # DEF MPSA63-PNP-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MPSA63-PNP-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA64-PNP-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA64 # Dev Prefix: T # Gate count = 1 # DEF MPSA64-PNP-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MPSA64-PNP-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA92-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA92 # Dev Prefix: T # Gate count = 1 # DEF MPSA92-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA92-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSA93-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSA93 # Dev Prefix: T # Gate count = 1 # DEF MPSA93-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSA93-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSL51-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSL51 # Dev Prefix: T # Gate count = 1 # DEF MPSL51-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSL51-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSW42-NPN-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSW42 # Dev Prefix: T # Gate count = 1 # DEF MPSW42-NPN-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "MPSW42-NPN-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MPSW92-PNP-TO92-CBE # Package Name: TO92-CBE # Dev Tech: MPSW92 # Dev Prefix: T # Gate count = 1 # DEF MPSW92-PNP-TO92-CBE T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "MPSW92-PNP-TO92-CBE" -400 200 50 H V L B F2 "transistor-TO92-CBE" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B B -100 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2111T1-PNP_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2111T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2111T1-PNP_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2111T1-PNP_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 30 P 2 1 0 0 -90 30 -110 40 P 2 1 0 0 -110 40 -70 50 P 2 1 0 0 -70 50 -110 60 P 2 1 0 0 -110 60 -70 70 P 2 1 0 0 -70 70 -110 80 P 2 1 0 0 -110 80 -70 90 P 2 1 0 0 -70 90 -90 100 P 2 1 0 0 -90 100 -90 140 P 2 1 0 0 -90 140 100 140 P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2112T1-PNP_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2112T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2112T1-PNP_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2112T1-PNP_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 30 P 2 1 0 0 -90 30 -110 40 P 2 1 0 0 -110 40 -70 50 P 2 1 0 0 -70 50 -110 60 P 2 1 0 0 -110 60 -70 70 P 2 1 0 0 -70 70 -110 80 P 2 1 0 0 -110 80 -70 90 P 2 1 0 0 -70 90 -90 100 P 2 1 0 0 -90 100 -90 140 P 2 1 0 0 -90 140 100 140 P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2113T1-PNP_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2113T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2113T1-PNP_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2113T1-PNP_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 30 P 2 1 0 0 -90 30 -110 40 P 2 1 0 0 -110 40 -70 50 P 2 1 0 0 -70 50 -110 60 P 2 1 0 0 -110 60 -70 70 P 2 1 0 0 -70 70 -110 80 P 2 1 0 0 -110 80 -70 90 P 2 1 0 0 -70 90 -90 100 P 2 1 0 0 -90 100 -90 140 P 2 1 0 0 -90 140 100 140 P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2114T1-PNP_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2114T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2114T1-PNP_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2114T1-PNP_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 30 P 2 1 0 0 -90 30 -110 40 P 2 1 0 0 -110 40 -70 50 P 2 1 0 0 -70 50 -110 60 P 2 1 0 0 -110 60 -70 70 P 2 1 0 0 -70 70 -110 80 P 2 1 0 0 -110 80 -70 90 P 2 1 0 0 -70 90 -90 100 P 2 1 0 0 -90 100 -90 140 P 2 1 0 0 -90 140 100 140 P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 -200 100 U 40 40 1 1 P X E E 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2211T1-NPN_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2211T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2211T1-NPN_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2211T1-NPN_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 -30 P 2 1 0 0 -90 -30 -70 -40 P 2 1 0 0 -70 -40 -110 -50 P 2 1 0 0 -110 -50 -70 -60 P 2 1 0 0 -70 -60 -110 -70 P 2 1 0 0 -110 -70 -70 -80 P 2 1 0 0 -70 -80 -110 -90 P 2 1 0 0 -110 -90 -90 -100 P 2 1 0 0 -90 -100 -90 -140 P 2 1 0 0 -90 -140 100 -140 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 -140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2212T1-NPN_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2212T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2212T1-NPN_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2212T1-NPN_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 -30 P 2 1 0 0 -90 -30 -70 -40 P 2 1 0 0 -70 -40 -110 -50 P 2 1 0 0 -110 -50 -70 -60 P 2 1 0 0 -70 -60 -110 -70 P 2 1 0 0 -110 -70 -70 -80 P 2 1 0 0 -70 -80 -110 -90 P 2 1 0 0 -110 -90 -90 -100 P 2 1 0 0 -90 -100 -90 -140 P 2 1 0 0 -90 -140 100 -140 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 -140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2213T1-NPN_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2213T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2213T1-NPN_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2213T1-NPN_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 -30 P 2 1 0 0 -90 -30 -70 -40 P 2 1 0 0 -70 -40 -110 -50 P 2 1 0 0 -110 -50 -70 -60 P 2 1 0 0 -70 -60 -110 -70 P 2 1 0 0 -110 -70 -70 -80 P 2 1 0 0 -70 -80 -110 -90 P 2 1 0 0 -110 -90 -90 -100 P 2 1 0 0 -90 -100 -90 -140 P 2 1 0 0 -90 -140 100 -140 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 -140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: MUN2214T1-NPN_DRIVER-SC59-BEC # Package Name: SC59-BEC # Dev Tech: MUN2214T1 # Dev Prefix: T # Gate count = 1 # DEF MUN2214T1-NPN_DRIVER-SC59-BEC T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DRIVER F0 "T" -400 300 50 H V L B F1 "MUN2214T1-NPN_DRIVER-SC59-BEC" -400 200 50 H V L B F2 "transistor-SC59-BEC" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 P 2 1 0 0 -200 0 -190 30 P 2 1 0 0 -190 30 -180 -20 P 2 1 0 0 -180 -20 -170 30 P 2 1 0 0 -170 30 -160 -20 P 2 1 0 0 -160 -20 -150 30 P 2 1 0 0 -150 30 -140 -20 P 2 1 0 0 -140 -20 -130 0 P 2 1 0 0 -130 0 -90 0 P 2 1 0 0 -90 0 -10 0 P 2 1 0 0 -90 0 -90 -30 P 2 1 0 0 -90 -30 -70 -40 P 2 1 0 0 -70 -40 -110 -50 P 2 1 0 0 -110 -50 -70 -60 P 2 1 0 0 -70 -60 -110 -70 P 2 1 0 0 -110 -70 -70 -80 P 2 1 0 0 -70 -80 -110 -90 P 2 1 0 0 -110 -90 -90 -100 P 2 1 0 0 -90 -100 -90 -140 P 2 1 0 0 -90 -140 100 -140 S -10 -100 20 100 1 1 0 F C -90 0 10 1 1 0 N C 100 -140 10 1 1 0 N X B B -300 0 100 R 40 40 1 1 P X C C 100 200 100 D 40 40 1 1 P X E E 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: NTE103A # Package Name: TO18- # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF NTE103A T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "NTE103A" -400 200 50 H V L B F2 "transistor-TO18-" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 2 -100 0 100 R 40 40 1 1 P X C 3 100 200 100 D 40 40 1 1 P X E 1 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP31 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF TIP31 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "TIP31" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP31A # Package Name: TO220 # Dev Tech: A # Dev Prefix: T # Gate count = 1 # DEF TIP31A T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "TIP31A" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP31B # Package Name: TO220 # Dev Tech: B # Dev Prefix: T # Gate count = 1 # DEF TIP31B T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "TIP31B" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP31C # Package Name: TO220 # Dev Tech: C # Dev Prefix: T # Gate count = 1 # DEF TIP31C T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN F0 "T" -400 300 50 H V L B F1 "TIP31C" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 100 100 20 60 P 2 1 0 0 70 -60 100 -100 P 2 1 0 0 100 -100 50 -100 P 2 1 0 0 50 -100 70 -60 P 2 1 0 0 60 -80 12 -56 P 2 1 0 0 60 -95 90 -95 P 2 1 0 0 90 -95 70 -70 P 2 1 0 0 70 -70 60 -90 P 2 1 0 0 60 -90 75 -90 P 2 1 0 0 75 -90 70 -80 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 200 100 D 40 40 1 1 P X E 3 100 -200 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP32 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF TIP32 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "TIP32" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP32A # Package Name: TO220 # Dev Tech: A # Dev Prefix: T # Gate count = 1 # DEF TIP32A T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "TIP32A" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP32B # Package Name: TO220 # Dev Tech: B # Dev Prefix: T # Gate count = 1 # DEF TIP32B T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "TIP32B" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP32C # Package Name: TO220 # Dev Tech: C # Dev Prefix: T # Gate count = 1 # DEF TIP32C T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: PNP F0 "T" -400 300 50 H V L B F1 "TIP32C" -400 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 82 66 62 102 P 2 1 0 0 62 102 20 58 P 2 1 0 0 20 58 82 66 P 2 1 0 0 100 100 71 83 P 2 1 0 0 100 -100 20 -60 P 2 1 0 0 75 70 60 95 P 2 1 0 0 60 95 30 65 P 2 1 0 0 30 65 70 70 P 2 1 0 0 70 70 60 85 P 2 1 0 0 60 85 45 75 P 2 1 0 0 45 75 60 75 S -10 -100 20 100 1 1 0 F X B 1 -100 0 100 R 40 40 1 1 P X C 2 100 -200 100 U 40 40 1 1 P X E 3 100 200 100 D 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP122 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF TIP122 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "TIP122" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF # # Dev Name: TIP131 # Package Name: TO220 # Dev Tech: '' # Dev Prefix: T # Gate count = 1 # DEF TIP131 T 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: NPN-DAR F0 "T" -250 300 50 H V L B F1 "TIP131" -160 200 50 H V L B F2 "transistor-TO220" 0 150 50 H I C C DRAW P 2 1 0 0 200 100 80 100 P 2 1 0 0 56 -56 90 -100 P 2 1 0 0 115 -100 90 -100 P 2 1 0 0 36 -86 56 -56 P 2 1 0 0 90 -100 36 -86 P 2 1 0 0 80 100 20 50 P 2 1 0 0 200 0 145 -50 P 2 1 0 0 200 -200 156 -185 P 2 1 0 0 180 -160 200 -200 P 2 1 0 0 156 -185 180 -160 P 2 1 0 0 46 -72 8 -47 P 2 1 0 0 168 -172 137 -142 P 2 1 0 0 85 -95 55 -60 P 2 1 0 0 55 -60 40 -85 P 2 1 0 0 40 -85 80 -95 P 2 1 0 0 80 -95 55 -65 P 2 1 0 0 55 -65 45 -80 P 2 1 0 0 45 -80 75 -90 P 2 1 0 0 75 -90 55 -70 P 2 1 0 0 55 -70 55 -75 P 2 1 0 0 195 -195 180 -165 P 2 1 0 0 180 -165 160 -185 P 2 1 0 0 160 -185 190 -195 P 2 1 0 0 190 -195 180 -170 P 2 1 0 0 180 -170 165 -185 P 2 1 0 0 165 -185 185 -190 P 2 1 0 0 185 -190 180 -180 P 2 1 0 0 180 -180 175 -180 S -10 -100 20 100 1 1 0 F S 115 -200 145 0 1 1 0 F C 200 100 15 1 1 0 N X B 1 -100 0 100 R 40 40 1 1 P X C 2 200 100 100 D 40 40 1 1 P X E 3 200 -300 100 U 40 40 1 1 P ENDDRAW ENDDEF #End Library