EESchema-LIBRARY Version 2.3 29/04/2008-12:24:21 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 4 # # Dev Name: FD1771 # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: # Gate count = 1 # DEF FD1771 ?? 0 40 Y Y 1 L N # Gate Name: G$1 # Symbol Name: FD1771 DRAW P 2 1 0 0 -500 1400 500 1400 P 2 1 0 0 500 1400 500 -1400 P 2 1 0 0 500 -1400 -500 -1400 P 2 1 0 0 -500 -1400 -500 1400 X /CS 3 -700 100 200 R 40 40 1 1 I X /DINT 37 700 -800 200 L 40 40 1 1 I I X /IP 35 700 400 200 L 40 40 1 1 I I X /MR 19 -700 -200 200 R 40 40 1 1 I I X /PH3 17 700 -300 200 L 40 40 1 1 O I X /RE 4 -700 0 200 R 40 40 1 1 I I X /TEST 22 -700 -800 200 R 40 40 1 1 I I X /TR00 34 700 300 200 L 40 40 1 1 I I X /WE 2 -700 -100 200 R 40 40 1 1 I I X /WF 33 700 500 200 L 40 40 1 1 I I X /WPRT 36 700 600 200 L 40 40 1 1 I I X /XTDS 25 700 1100 200 L 40 40 1 1 I I X 3PM 18 700 -400 200 L 40 40 1 1 I X A0 5 -700 400 200 R 40 40 1 1 I X A1 6 -700 300 200 R 40 40 1 1 I X CLK 24 -700 -700 200 R 40 40 1 1 I C X D0 7 -700 1300 200 R 40 40 1 1 B X D1 8 -700 1200 200 R 40 40 1 1 B X D2 9 -700 1100 200 R 40 40 1 1 B X D3 10 -700 1000 200 R 40 40 1 1 B X D4 11 -700 900 200 R 40 40 1 1 B X D5 12 -700 800 200 R 40 40 1 1 B X D6 13 -700 700 200 R 40 40 1 1 B X D7 14 -700 600 200 R 40 40 1 1 B X DRQ 38 -700 -400 200 R 40 40 1 1 O X FDCLK 26 700 1200 200 L 40 40 1 1 I X FDDATA 27 700 1300 200 L 40 40 1 1 I X HLD 28 700 -600 200 L 40 40 1 1 O X HLT 23 700 -700 200 L 40 40 1 1 I X INTRQ 39 -700 -500 200 R 40 40 1 1 O X PH1/STEP 15 700 -100 200 L 40 40 1 1 O X PH2/DIRC 16 700 -200 200 L 40 40 1 1 O X READY 32 700 200 200 L 40 40 1 1 I X TG43 29 700 100 200 L 40 40 1 1 O X VBB 1 -700 -1100 200 R 40 40 1 1 W X VCC 21 700 -1300 200 L 40 40 1 1 W X VDD 40 700 -1100 200 L 40 40 1 1 W X VSS 20 -700 -1300 200 R 40 40 1 1 W X WD 31 700 900 200 L 40 40 1 1 O X WG 30 700 800 200 L 40 40 1 1 O ENDDRAW ENDDEF # # Dev Name: WD1770-00 # Package Name: DIL28-6 # Dev Tech: '' # Dev Prefix: # Gate count = 2 # DEF WD1770-00 ?? 0 40 Y Y 2 L N # Gate Name: IC$1 # Symbol Name: WD1770 DRAW P 2 1 0 0 -500 1000 500 1000 P 2 1 0 0 500 1000 500 -900 P 2 1 0 0 500 -900 -500 -900 P 2 1 0 0 -500 -900 -500 1000 X /CS 1 -700 -400 200 R 40 40 1 1 I I X /DDEN 26 700 -600 200 L 40 40 1 1 I I X /IP 24 700 300 200 L 40 40 1 1 I I X /MR 13 -700 -500 200 R 40 40 1 1 I I X /RD 19 700 600 200 L 40 40 1 1 I I X /TR00 23 700 200 200 L 40 40 1 1 I I X /WPRT 25 700 100 200 L 40 40 1 1 I I X A0 3 -700 0 200 R 40 40 1 1 I X A1 4 -700 -100 200 R 40 40 1 1 I X CLK 18 700 -800 200 L 40 40 1 1 I C X D0 5 -700 900 200 R 40 40 1 1 B X D1 6 -700 800 200 R 40 40 1 1 B X D2 7 -700 700 200 R 40 40 1 1 B X D3 8 -700 600 200 R 40 40 1 1 B X D4 9 -700 500 200 R 40 40 1 1 B X D5 10 -700 400 200 R 40 40 1 1 B X D6 11 -700 300 200 R 40 40 1 1 B X D7 12 -700 200 200 R 40 40 1 1 B X DIRC 17 700 -100 200 L 40 40 1 1 O X DRQ 27 -700 -700 200 R 40 40 1 1 O X INTRQ 28 -700 -800 200 R 40 40 1 1 O X MO 20 700 0 200 L 40 40 1 1 O X R/W 2 -700 -300 200 R 40 40 1 1 I X STEP 16 700 -200 200 L 40 40 1 1 O X WD 22 700 700 200 L 40 40 1 1 O X WG 21 700 800 200 L 40 40 1 1 O # Gate Name: PWR # Symbol Name: PWRN T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 14 0 -300 200 U 40 40 2 1 W X VCC 15 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: WD1772-00 # Package Name: DIL28-6 # Dev Tech: '' # Dev Prefix: # Gate count = 2 # DEF WD1772-00 ?? 0 40 Y Y 2 L N # Gate Name: IC$1 # Symbol Name: WD1772 DRAW P 2 1 0 0 -500 1000 500 1000 P 2 1 0 0 500 1000 500 -900 P 2 1 0 0 500 -900 -500 -900 P 2 1 0 0 -500 -900 -500 1000 X /CS 1 -700 -400 200 R 40 40 1 1 I I X /DDEN 26 700 -600 200 L 40 40 1 1 I I X /IP 24 700 300 200 L 40 40 1 1 I I X /MR 13 -700 -500 200 R 40 40 1 1 I I X /RD 19 700 600 200 L 40 40 1 1 I I X /TR00 23 700 200 200 L 40 40 1 1 I I X /WPRT 25 700 100 200 L 40 40 1 1 I I X A0 3 -700 0 200 R 40 40 1 1 I X A1 4 -700 -100 200 R 40 40 1 1 I X CLK 18 700 -800 200 L 40 40 1 1 I C X D0 5 -700 900 200 R 40 40 1 1 B X D1 6 -700 800 200 R 40 40 1 1 B X D2 7 -700 700 200 R 40 40 1 1 B X D3 8 -700 600 200 R 40 40 1 1 B X D4 9 -700 500 200 R 40 40 1 1 B X D5 10 -700 400 200 R 40 40 1 1 B X D6 11 -700 300 200 R 40 40 1 1 B X D7 12 -700 200 200 R 40 40 1 1 B X DIRC 17 700 -100 200 L 40 40 1 1 O X DRQ 27 -700 -700 200 R 40 40 1 1 O X INTRQ 28 -700 -800 200 R 40 40 1 1 O X MO 20 700 0 200 L 40 40 1 1 O X R/W 2 -700 -300 200 R 40 40 1 1 I X STEP 16 700 -200 200 L 40 40 1 1 O X WD 22 700 700 200 L 40 40 1 1 O X WG 21 700 800 200 L 40 40 1 1 O # Gate Name: PWR # Symbol Name: PWRN T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 14 0 -300 200 U 40 40 2 1 W X VCC 15 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: WD1773 # Package Name: DIL28-6 # Dev Tech: '' # Dev Prefix: # Gate count = 2 # DEF WD1773 ?? 0 40 Y Y 2 L N # Gate Name: IC$1 # Symbol Name: WD1773 DRAW P 2 1 0 0 -500 1000 500 1000 P 2 1 0 0 500 1000 500 -900 P 2 1 0 0 500 -900 -500 -900 P 2 1 0 0 -500 -900 -500 1000 X /CS 1 -700 -400 200 R 40 40 1 1 I I X /DDEN 26 700 -600 200 L 40 40 1 1 I I X /IP 24 700 300 200 L 40 40 1 1 I I X /MR 13 -700 -500 200 R 40 40 1 1 I I X /RD 19 700 600 200 L 40 40 1 1 I I X /TR00 23 700 200 200 L 40 40 1 1 I I X /WPRT 25 700 100 200 L 40 40 1 1 I I X A0 3 -700 0 200 R 40 40 1 1 I X A1 4 -700 -100 200 R 40 40 1 1 I X CLK 18 700 -800 200 L 40 40 1 1 I C X D0 5 -700 900 200 R 40 40 1 1 B X D1 6 -700 800 200 R 40 40 1 1 B X D2 7 -700 700 200 R 40 40 1 1 B X D3 8 -700 600 200 R 40 40 1 1 B X D4 9 -700 500 200 R 40 40 1 1 B X D5 10 -700 400 200 R 40 40 1 1 B X D6 11 -700 300 200 R 40 40 1 1 B X D7 12 -700 200 200 R 40 40 1 1 B X DIRC 17 700 -100 200 L 40 40 1 1 O X DRQ 27 -700 -700 200 R 40 40 1 1 O X INTRQ 28 -700 -800 200 R 40 40 1 1 O X R/W 2 -700 -300 200 R 40 40 1 1 I X RDY/ENP 20 700 0 200 L 40 40 1 1 I X STEP 16 700 -200 200 L 40 40 1 1 O X WD 22 700 700 200 L 40 40 1 1 O X WG 21 700 800 200 L 40 40 1 1 O # Gate Name: PWR # Symbol Name: PWRN T 1 50 -155 50 0 2 0 GND T 1 50 175 50 0 2 0 VCC X GND 14 0 -300 200 U 40 40 2 1 W X VCC 15 0 300 200 D 40 40 2 1 W ENDDRAW ENDDEF #End Library