EESchema-LIBRARY Version 2.3 29/04/2008-12:26:03 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 2 # # Dev Name: XC3S100E-VQ100 # Package Name: VQ100 # Dev Tech: '' # Dev Prefix: IC # Gate count = 6 # DEF XC3S100E-VQ100 IC 0 40 Y Y 6 L N # Gate Name: B0 # Symbol Name: XC100VQ100BANK0 F0 "IC" -900 750 50 H V L B F1 "XC3S100E-VQ100" -900 -620 50 H V L B F2 "xilinx-xc3sxxxe_vq100-VQ100" 0 150 50 H I C C DRAW P 2 1 0 0 -900 700 -900 500 P 2 1 0 0 -900 500 -900 -500 P 2 1 0 0 -900 -500 900 -500 P 2 1 0 0 900 -500 900 500 P 2 1 0 0 900 500 900 700 P 2 1 0 0 900 700 -900 700 P 2 1 0 0 -900 500 900 500 T 0 28 603 86 0 1 0 BANK~0 X IO 92 -1000 200 100 R 40 40 1 1 B X IO_L01N_0 79 -1000 100 100 R 40 40 1 1 B X IO_L01P_0 78 -1000 0 100 R 40 40 1 1 B X IO_L02N_0/GCLK5 84 -1000 -100 100 R 40 40 1 1 B X IO_L02P_0/GCLK4 83 -1000 -200 100 R 40 40 1 1 B X IO_L03N_0/GCLK7 86 -1000 -300 100 R 40 40 1 1 B X IO_L03P_0/GCLK6 85 -1000 -400 100 R 40 40 1 1 B X IO_L05N_0/GCLK11 91 1000 200 100 L 40 40 1 1 B X IO_L05P_0/GCLK10 90 1000 100 100 L 40 40 1 1 B X IO_L06N_0/VREF_0 95 1000 0 100 L 40 40 1 1 B X IO_L06P_0 94 1000 -100 100 L 40 40 1 1 B X IO_L07N_0/HSWAP 99 1000 -200 100 L 40 40 1 1 B X IO_L07P_0 98 1000 -300 100 L 40 40 1 1 B X IP_L04N_0/GCLK9 89 1000 400 100 L 40 40 1 1 I X IP_L04P_0/GCLK8 88 1000 300 100 L 40 40 1 1 I X VCCO_0 82 -1000 400 100 R 40 40 1 1 W X VCCO_0@1 97 -1000 300 100 R 40 40 1 1 W # Gate Name: B1 # Symbol Name: XC100VQ100BANK1 P 2 2 0 0 -900 700 -900 500 P 2 2 0 0 -900 500 -900 -500 P 2 2 0 0 -900 -500 900 -500 P 2 2 0 0 900 -500 900 500 P 2 2 0 0 900 500 900 700 P 2 2 0 0 900 700 -900 700 P 2 2 0 0 -900 500 900 500 T 0 28 603 86 0 2 0 BANK~1 X IO_L01N_1 54 -1000 100 100 R 40 40 2 1 B X IO_L01P_1 53 -1000 0 100 R 40 40 2 1 B X IO_L02N_1 58 -1000 -100 100 R 40 40 2 1 B X IO_L02P_1 57 -1000 -200 100 R 40 40 2 1 B X IO_L03N_1/RHCLK1 61 -1000 -300 100 R 40 40 2 1 B X IO_L03P_1/RHCLK0 60 -1000 -400 100 R 40 40 2 1 B X IO_L04N_1/RHCLK3 63 1000 400 100 L 40 40 2 1 B X IO_L04P_1/RHCLK2 62 1000 300 100 L 40 40 2 1 B X IO_L05N_1/RHCLK5 66 1000 200 100 L 40 40 2 1 B X IO_L05P_1/RHCLK4 65 1000 100 100 L 40 40 2 1 B X IO_L06N_1/RHCLK7 68 1000 0 100 L 40 40 2 1 B X IO_L06P_1/RHCLK6 67 1000 -100 100 L 40 40 2 1 B X IO_L07N_1 71 1000 -200 100 L 40 40 2 1 B X IO_L07P_1 70 1000 -300 100 L 40 40 2 1 B X IP/VREF_1 69 -1000 200 100 R 40 40 2 1 I X VCCO_1 55 -1000 400 100 R 40 40 2 1 W X VCCO_1@1 73 -1000 300 100 R 40 40 2 1 W # Gate Name: B2 # Symbol Name: XC100VQ100BANK2 P 2 3 0 0 -1000 700 -1000 500 P 2 3 0 0 -1000 500 -1000 -900 P 2 3 0 0 -1000 -900 1000 -900 P 2 3 0 0 1000 -900 1000 500 P 2 3 0 0 1000 500 1000 700 P 2 3 0 0 1000 700 -1000 700 P 2 3 0 0 -1000 500 1000 500 T 0 28 603 86 0 3 0 BANK~2 X IO/D5 34 1100 -400 100 L 40 40 3 1 B X IO/M1 42 1100 -500 100 L 40 40 3 1 B X IO_L01N_2/INIT_B 25 -1100 100 100 R 40 40 3 1 B X IO_L01P_2/CSO_B 24 -1100 0 100 R 40 40 3 1 B X IO_L02N_2/MOSI/CSI_B 27 -1100 -100 100 R 40 40 3 1 B X IO_L02P_2/DOUT/BUSY 26 -1100 -200 100 R 40 40 3 1 B X IO_L03N_2/D6/GCLK13 33 -1100 -300 100 R 40 40 3 1 B X IO_L03P_2/D7/GCLK12 32 -1100 -400 100 R 40 40 3 1 B X IO_L04N_2/D3/GCLK15 36 -1100 -500 100 R 40 40 3 1 B X IO_L04P_2/D4/GCLK14 35 -1100 -600 100 R 40 40 3 1 B X IO_L06N_2/D1/GCLK3 41 1100 400 100 L 40 40 3 1 B X IO_L06P_2/D2/GCLK2 40 1100 300 100 L 40 40 3 1 B X IO_L07N_2/D0/DIN 44 1100 200 100 L 40 40 3 1 B X IO_L07P_2/M0 43 1100 100 100 L 40 40 3 1 B X IO_L08N_2/VS1 48 1100 0 100 L 40 40 3 1 B X IO_L08P_2/VS2 47 1100 -100 100 L 40 40 3 1 B X IO_L09N_2/CCLK 50 1100 -200 100 L 40 40 3 1 B X IO_L09P_2/VS0 49 1100 -300 100 L 40 40 3 1 B X IP/VREF2 30 -1100 200 100 R 40 40 3 1 I X IP_L05N_2/M2/GCLK1 39 -1100 -700 100 R 40 40 3 1 I X IP_L05P_2/RDWR_B/GCLK0 38 -1100 -800 100 R 40 40 3 1 I X VCCO_2 31 -1100 400 100 R 40 40 3 1 W X VCCO_2@1 45 -1100 300 100 R 40 40 3 1 W # Gate Name: B3 # Symbol Name: XC100VQ100BANK3 P 2 4 0 0 -900 700 -900 500 P 2 4 0 0 -900 500 -900 -500 P 2 4 0 0 -900 -500 900 -500 P 2 4 0 0 900 -500 900 500 P 2 4 0 0 900 500 900 700 P 2 4 0 0 900 700 -900 700 P 2 4 0 0 -900 500 900 500 T 0 28 603 86 0 4 0 BANK~3 X IO_L01N_3 3 -1000 100 100 R 40 40 4 1 B X IO_L01P_3 2 -1000 0 100 R 40 40 4 1 B X IO_L02N_3/VREF3 5 -1000 -100 100 R 40 40 4 1 B X IO_L02P_3 4 -1000 -200 100 R 40 40 4 1 B X IO_L03N_3/LHCLK1 10 -1000 -300 100 R 40 40 4 1 B X IO_L03P_3/LHCLK0 9 -1000 -400 100 R 40 40 4 1 B X IO_L04N_3/LHCLK3 12 1000 400 100 L 40 40 4 1 B X IO_L04P_3/LHCLK2 11 1000 300 100 L 40 40 4 1 B X IO_L05N_3/LHCLK5 16 1000 200 100 L 40 40 4 1 B X IO_L05P_3/LHCLK4 15 1000 100 100 L 40 40 4 1 B X IO_L06N_3/LHCLK7 18 1000 0 100 L 40 40 4 1 B X IO_L06P_3/LHCLK6 17 1000 -100 100 L 40 40 4 1 B X IO_L07N_3 23 1000 -200 100 L 40 40 4 1 B X IO_L07P_3 22 1000 -300 100 L 40 40 4 1 B X IP 13 -1000 200 100 R 40 40 4 1 I X VCCO_3 8 -1000 400 100 R 40 40 4 1 W X VCCO_3@1 20 -1000 300 100 R 40 40 4 1 W # Gate Name: JTAG # Symbol Name: XC100VQ100JTAG P 2 5 0 0 -600 400 -600 200 P 2 5 0 0 -600 200 -600 -300 P 2 5 0 0 -600 -300 600 -300 P 2 5 0 0 600 -300 600 200 P 2 5 0 0 600 200 600 400 P 2 5 0 0 600 400 0 400 P 2 5 0 0 0 400 -600 400 P 2 5 0 0 -600 200 0 200 P 2 5 0 0 0 200 600 200 P 2 5 0 0 0 400 0 200 T 0 -298 293 86 0 5 0 JTAG T 0 318 293 86 0 5 0 CONFIG X DONE 51 700 0 100 L 40 40 5 1 O X PROG_B 1 700 -100 100 L 40 40 5 1 I X TCK 77 -700 100 100 R 40 40 5 1 I X TDI 100 -700 0 100 R 40 40 5 1 I X TDO 76 -700 -100 100 R 40 40 5 1 O X TMS 75 -700 -200 100 R 40 40 5 1 I # Gate Name: POWER # Symbol Name: XC100VQ100POWER P 2 6 0 0 -700 200 -700 -200 P 2 6 0 0 -700 -200 700 -200 P 2 6 0 0 -700 200 700 200 P 2 6 0 0 700 200 700 -200 T 0 -351 -117 86 0 6 0 GND T 0 349 -117 86 0 6 0 GND T 0 -322 103 86 0 6 0 VCCAUX T 0 398 103 86 0 6 0 VCCINT X GND 7 -600 -300 100 U 40 40 6 1 W X GND@1 14 -500 -300 100 U 40 40 6 1 W X GND@2 19 -400 -300 100 U 40 40 6 1 W X GND@3 29 -300 -300 100 U 40 40 6 1 W X GND@4 37 -200 -300 100 U 40 40 6 1 W X GND@5 52 -100 -300 100 U 40 40 6 1 W X GND@6 59 100 -300 100 U 40 40 6 1 W X GND@7 64 200 -300 100 U 40 40 6 1 W X GND@8 72 300 -300 100 U 40 40 6 1 W X GND@9 81 400 -300 100 U 40 40 6 1 W X GND@10 87 500 -300 100 U 40 40 6 1 W X GND@11 93 600 -300 100 U 40 40 6 1 W X VCCAUX 21 -500 300 100 D 40 40 6 1 W X VCCAUX@1 46 -400 300 100 D 40 40 6 1 W X VCCAUX@2 74 -300 300 100 D 40 40 6 1 W X VCCAUX@3 96 -200 300 100 D 40 40 6 1 W X VCCINT 6 200 300 100 D 40 40 6 1 W X VCCINT@1 28 300 300 100 D 40 40 6 1 W X VCCINT@2 56 400 300 100 D 40 40 6 1 W X VCCINT@3 80 500 300 100 D 40 40 6 1 W ENDDRAW ENDDEF # # Dev Name: XC3S250E-VQ100 # Package Name: VQ100 # Dev Tech: '' # Dev Prefix: IC # Gate count = 6 # DEF XC3S250E-VQ100 IC 0 40 Y Y 6 L N # Gate Name: B0 # Symbol Name: XC100VQ100BANK0 F0 "IC" -900 750 50 H V L B F1 "XC3S250E-VQ100" -900 -620 50 H V L B F2 "xilinx-xc3sxxxe_vq100-VQ100" 0 150 50 H I C C DRAW P 2 1 0 0 -900 700 -900 500 P 2 1 0 0 -900 500 -900 -500 P 2 1 0 0 -900 -500 900 -500 P 2 1 0 0 900 -500 900 500 P 2 1 0 0 900 500 900 700 P 2 1 0 0 900 700 -900 700 P 2 1 0 0 -900 500 900 500 T 0 28 603 86 0 1 0 BANK~0 X IO 92 -1000 200 100 R 40 40 1 1 B X IO_L01N_0 79 -1000 100 100 R 40 40 1 1 B X IO_L01P_0 78 -1000 0 100 R 40 40 1 1 B X IO_L02N_0/GCLK5 84 -1000 -100 100 R 40 40 1 1 B X IO_L02P_0/GCLK4 83 -1000 -200 100 R 40 40 1 1 B X IO_L03N_0/GCLK7 86 -1000 -300 100 R 40 40 1 1 B X IO_L03P_0/GCLK6 85 -1000 -400 100 R 40 40 1 1 B X IO_L05N_0/GCLK11 91 1000 200 100 L 40 40 1 1 B X IO_L05P_0/GCLK10 90 1000 100 100 L 40 40 1 1 B X IO_L06N_0/VREF_0 95 1000 0 100 L 40 40 1 1 B X IO_L06P_0 94 1000 -100 100 L 40 40 1 1 B X IO_L07N_0/HSWAP 99 1000 -200 100 L 40 40 1 1 B X IO_L07P_0 98 1000 -300 100 L 40 40 1 1 B X IP_L04N_0/GCLK9 89 1000 400 100 L 40 40 1 1 I X IP_L04P_0/GCLK8 88 1000 300 100 L 40 40 1 1 I X VCCO_0 82 -1000 400 100 R 40 40 1 1 W X VCCO_0@1 97 -1000 300 100 R 40 40 1 1 W # Gate Name: B1 # Symbol Name: XC100VQ100BANK1 P 2 2 0 0 -900 700 -900 500 P 2 2 0 0 -900 500 -900 -500 P 2 2 0 0 -900 -500 900 -500 P 2 2 0 0 900 -500 900 500 P 2 2 0 0 900 500 900 700 P 2 2 0 0 900 700 -900 700 P 2 2 0 0 -900 500 900 500 T 0 28 603 86 0 2 0 BANK~1 X IO_L01N_1 54 -1000 100 100 R 40 40 2 1 B X IO_L01P_1 53 -1000 0 100 R 40 40 2 1 B X IO_L02N_1 58 -1000 -100 100 R 40 40 2 1 B X IO_L02P_1 57 -1000 -200 100 R 40 40 2 1 B X IO_L03N_1/RHCLK1 61 -1000 -300 100 R 40 40 2 1 B X IO_L03P_1/RHCLK0 60 -1000 -400 100 R 40 40 2 1 B X IO_L04N_1/RHCLK3 63 1000 400 100 L 40 40 2 1 B X IO_L04P_1/RHCLK2 62 1000 300 100 L 40 40 2 1 B X IO_L05N_1/RHCLK5 66 1000 200 100 L 40 40 2 1 B X IO_L05P_1/RHCLK4 65 1000 100 100 L 40 40 2 1 B X IO_L06N_1/RHCLK7 68 1000 0 100 L 40 40 2 1 B X IO_L06P_1/RHCLK6 67 1000 -100 100 L 40 40 2 1 B X IO_L07N_1 71 1000 -200 100 L 40 40 2 1 B X IO_L07P_1 70 1000 -300 100 L 40 40 2 1 B X IP/VREF_1 69 -1000 200 100 R 40 40 2 1 I X VCCO_1 55 -1000 400 100 R 40 40 2 1 W X VCCO_1@1 73 -1000 300 100 R 40 40 2 1 W # Gate Name: B2 # Symbol Name: XC100VQ100BANK2 P 2 3 0 0 -1000 700 -1000 500 P 2 3 0 0 -1000 500 -1000 -900 P 2 3 0 0 -1000 -900 1000 -900 P 2 3 0 0 1000 -900 1000 500 P 2 3 0 0 1000 500 1000 700 P 2 3 0 0 1000 700 -1000 700 P 2 3 0 0 -1000 500 1000 500 T 0 28 603 86 0 3 0 BANK~2 X IO/D5 34 1100 -400 100 L 40 40 3 1 B X IO/M1 42 1100 -500 100 L 40 40 3 1 B X IO_L01N_2/INIT_B 25 -1100 100 100 R 40 40 3 1 B X IO_L01P_2/CSO_B 24 -1100 0 100 R 40 40 3 1 B X IO_L02N_2/MOSI/CSI_B 27 -1100 -100 100 R 40 40 3 1 B X IO_L02P_2/DOUT/BUSY 26 -1100 -200 100 R 40 40 3 1 B X IO_L03N_2/D6/GCLK13 33 -1100 -300 100 R 40 40 3 1 B X IO_L03P_2/D7/GCLK12 32 -1100 -400 100 R 40 40 3 1 B X IO_L04N_2/D3/GCLK15 36 -1100 -500 100 R 40 40 3 1 B X IO_L04P_2/D4/GCLK14 35 -1100 -600 100 R 40 40 3 1 B X IO_L06N_2/D1/GCLK3 41 1100 400 100 L 40 40 3 1 B X IO_L06P_2/D2/GCLK2 40 1100 300 100 L 40 40 3 1 B X IO_L07N_2/D0/DIN 44 1100 200 100 L 40 40 3 1 B X IO_L07P_2/M0 43 1100 100 100 L 40 40 3 1 B X IO_L08N_2/VS1 48 1100 0 100 L 40 40 3 1 B X IO_L08P_2/VS2 47 1100 -100 100 L 40 40 3 1 B X IO_L09N_2/CCLK 50 1100 -200 100 L 40 40 3 1 B X IO_L09P_2/VS0 49 1100 -300 100 L 40 40 3 1 B X IP/VREF2 30 -1100 200 100 R 40 40 3 1 I X IP_L05N_2/M2/GCLK1 39 -1100 -700 100 R 40 40 3 1 I X IP_L05P_2/RDWR_B/GCLK0 38 -1100 -800 100 R 40 40 3 1 I X VCCO_2 31 -1100 400 100 R 40 40 3 1 W X VCCO_2@1 45 -1100 300 100 R 40 40 3 1 W # Gate Name: B3 # Symbol Name: XC100VQ100BANK3 P 2 4 0 0 -900 700 -900 500 P 2 4 0 0 -900 500 -900 -500 P 2 4 0 0 -900 -500 900 -500 P 2 4 0 0 900 -500 900 500 P 2 4 0 0 900 500 900 700 P 2 4 0 0 900 700 -900 700 P 2 4 0 0 -900 500 900 500 T 0 28 603 86 0 4 0 BANK~3 X IO_L01N_3 3 -1000 100 100 R 40 40 4 1 B X IO_L01P_3 2 -1000 0 100 R 40 40 4 1 B X IO_L02N_3/VREF3 5 -1000 -100 100 R 40 40 4 1 B X IO_L02P_3 4 -1000 -200 100 R 40 40 4 1 B X IO_L03N_3/LHCLK1 10 -1000 -300 100 R 40 40 4 1 B X IO_L03P_3/LHCLK0 9 -1000 -400 100 R 40 40 4 1 B X IO_L04N_3/LHCLK3 12 1000 400 100 L 40 40 4 1 B X IO_L04P_3/LHCLK2 11 1000 300 100 L 40 40 4 1 B X IO_L05N_3/LHCLK5 16 1000 200 100 L 40 40 4 1 B X IO_L05P_3/LHCLK4 15 1000 100 100 L 40 40 4 1 B X IO_L06N_3/LHCLK7 18 1000 0 100 L 40 40 4 1 B X IO_L06P_3/LHCLK6 17 1000 -100 100 L 40 40 4 1 B X IO_L07N_3 23 1000 -200 100 L 40 40 4 1 B X IO_L07P_3 22 1000 -300 100 L 40 40 4 1 B X IP 13 -1000 200 100 R 40 40 4 1 I X VCCO_3 8 -1000 400 100 R 40 40 4 1 W X VCCO_3@1 20 -1000 300 100 R 40 40 4 1 W # Gate Name: JTAG # Symbol Name: XC100VQ100JTAG P 2 5 0 0 -600 400 -600 200 P 2 5 0 0 -600 200 -600 -300 P 2 5 0 0 -600 -300 600 -300 P 2 5 0 0 600 -300 600 200 P 2 5 0 0 600 200 600 400 P 2 5 0 0 600 400 0 400 P 2 5 0 0 0 400 -600 400 P 2 5 0 0 -600 200 0 200 P 2 5 0 0 0 200 600 200 P 2 5 0 0 0 400 0 200 T 0 -298 293 86 0 5 0 JTAG T 0 318 293 86 0 5 0 CONFIG X DONE 51 700 0 100 L 40 40 5 1 O X PROG_B 1 700 -100 100 L 40 40 5 1 I X TCK 77 -700 100 100 R 40 40 5 1 I X TDI 100 -700 0 100 R 40 40 5 1 I X TDO 76 -700 -100 100 R 40 40 5 1 O X TMS 75 -700 -200 100 R 40 40 5 1 I # Gate Name: POWER # Symbol Name: XC100VQ100POWER P 2 6 0 0 -700 200 -700 -200 P 2 6 0 0 -700 -200 700 -200 P 2 6 0 0 -700 200 700 200 P 2 6 0 0 700 200 700 -200 T 0 -351 -117 86 0 6 0 GND T 0 349 -117 86 0 6 0 GND T 0 -322 103 86 0 6 0 VCCAUX T 0 398 103 86 0 6 0 VCCINT X GND 7 -600 -300 100 U 40 40 6 1 W X GND@1 14 -500 -300 100 U 40 40 6 1 W X GND@2 19 -400 -300 100 U 40 40 6 1 W X GND@3 29 -300 -300 100 U 40 40 6 1 W X GND@4 37 -200 -300 100 U 40 40 6 1 W X GND@5 52 -100 -300 100 U 40 40 6 1 W X GND@6 59 100 -300 100 U 40 40 6 1 W X GND@7 64 200 -300 100 U 40 40 6 1 W X GND@8 72 300 -300 100 U 40 40 6 1 W X GND@9 81 400 -300 100 U 40 40 6 1 W X GND@10 87 500 -300 100 U 40 40 6 1 W X GND@11 93 600 -300 100 U 40 40 6 1 W X VCCAUX 21 -500 300 100 D 40 40 6 1 W X VCCAUX@1 46 -400 300 100 D 40 40 6 1 W X VCCAUX@2 74 -300 300 100 D 40 40 6 1 W X VCCAUX@3 96 -200 300 100 D 40 40 6 1 W X VCCINT 6 200 300 100 D 40 40 6 1 W X VCCINT@1 28 300 300 100 D 40 40 6 1 W X VCCINT@2 56 400 300 100 D 40 40 6 1 W X VCCINT@3 80 500 300 100 D 40 40 6 1 W ENDDRAW ENDDEF #End Library