EESchema-LIBRARY Version 2.3  29/04/2008-12:26:03
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 16
#
# Dev Name: Z8F0X11HH
# Package Name: SSOP-20
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X11HH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X11HH" 0 -100 50 H V L B
F2 "z8encore8k_v10-SSOP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X11
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
X DBG 14 800 -100 200 L 40 40 2 1 B 
X NC 17 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0 19 800 200 200 L 40 40 2 1 B 
X PB1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8F0X11PH
# Package Name: PDIP-20
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X11PH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X11PH" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X11
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
X DBG 14 800 -100 200 L 40 40 2 1 B 
X NC 17 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0 19 800 200 200 L 40 40 2 1 B 
X PB1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8F0X12PJ
# Package Name: PDIP-28
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X12PJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X12PJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X12
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X NC 23 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0 28 800 500 200 L 40 40 2 1 B 
X PB1 27 800 400 200 L 40 40 2 1 B 
X PB2 26 800 300 200 L 40 40 2 1 B 
X PB3 25 800 200 200 L 40 40 2 1 B 
X PB4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8F0X12SJ
# Package Name: SOIC-28
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X12SJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X12SJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-SOIC-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X12
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X NC 23 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0 28 800 500 200 L 40 40 2 1 B 
X PB1 27 800 400 200 L 40 40 2 1 B 
X PB2 26 800 300 200 L 40 40 2 1 B 
X PB3 25 800 200 200 L 40 40 2 1 B 
X PB4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8F0X21HH
# Package Name: SSOP-20
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X21HH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X21HH" 0 -100 50 H V L B
F2 "z8encore8k_v10-SSOP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X21
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
X DBG 14 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0/ANA0 19 800 200 200 L 40 40 2 1 B 
X PB1/ANA1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X VREF 17 800 0 200 L 40 40 2 1 P 
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8F0X21PH
# Package Name: PDIP-20
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X21PH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X21PH" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X21
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
X DBG 14 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0/ANA0 19 800 200 200 L 40 40 2 1 B 
X PB1/ANA1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X VREF 17 800 0 200 L 40 40 2 1 P 
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8F0X22PJ
# Package Name: PDIP-28
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X22PJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X22PJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X22
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0/ANA0 28 800 500 200 L 40 40 2 1 B 
X PB1/ANA1 27 800 400 200 L 40 40 2 1 B 
X PB2/ANA2 26 800 300 200 L 40 40 2 1 B 
X PB3/ANA3 25 800 200 200 L 40 40 2 1 B 
X PB4/ANA4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X VREF 23 800 0 200 L 40 40 2 1 P 
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8F0X22SJ
# Package Name: SOIC-28
# Dev Tech: F
# Dev Prefix: U
# Gate count = 2
#
DEF Z8F0X22SJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8F0X22SJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-SOIC-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X22
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0/ANA0 28 800 500 200 L 40 40 2 1 B 
X PB1/ANA1 27 800 400 200 L 40 40 2 1 B 
X PB2/ANA2 26 800 300 200 L 40 40 2 1 B 
X PB3/ANA3 25 800 200 200 L 40 40 2 1 B 
X PB4/ANA4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X VREF 23 800 0 200 L 40 40 2 1 P 
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X11HH
# Package Name: SSOP-20
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X11HH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X11HH" 0 -100 50 H V L B
F2 "z8encore8k_v10-SSOP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X11
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
X DBG 14 800 -100 200 L 40 40 2 1 B 
X NC 17 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0 19 800 200 200 L 40 40 2 1 B 
X PB1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X11PH
# Package Name: PDIP-20
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X11PH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X11PH" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X11
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
X DBG 14 800 -100 200 L 40 40 2 1 B 
X NC 17 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0 19 800 200 200 L 40 40 2 1 B 
X PB1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X12PJ
# Package Name: PDIP-28
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X12PJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X12PJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X12
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X NC 23 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0 28 800 500 200 L 40 40 2 1 B 
X PB1 27 800 400 200 L 40 40 2 1 B 
X PB2 26 800 300 200 L 40 40 2 1 B 
X PB3 25 800 200 200 L 40 40 2 1 B 
X PB4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X12SJ
# Package Name: SOIC-28
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X12SJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X12SJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-SOIC-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X12
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X NC 23 800 0 200 L 40 40 2 1 U 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0 28 800 500 200 L 40 40 2 1 B 
X PB1 27 800 400 200 L 40 40 2 1 B 
X PB2 26 800 300 200 L 40 40 2 1 B 
X PB3 25 800 200 200 L 40 40 2 1 B 
X PB4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X21HH
# Package Name: SSOP-20
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X21HH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X21HH" 0 -100 50 H V L B
F2 "z8encore8k_v10-SSOP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X21
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
X DBG 14 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0/ANA0 19 800 200 200 L 40 40 2 1 B 
X PB1/ANA1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X VREF 17 800 0 200 L 40 40 2 1 P 
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X21PH
# Package Name: PDIP-20
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X21PH U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X21PH" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-20" 0 150 50 H I C C
DRAW
X AVDD 15 -300 600 200 D 40 40 1 1 W 
X AVSS 16 -300 -500 200 U 40 40 1 1 W 
X VDD 7 -100 600 200 D 40 40 1 1 W 
X VSS 4 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X21
P 2 2 0 0 -600 400 600 400
P 2 2 0 0 600 400 600 -500
P 2 2 0 0 600 -500 -600 -500
P 2 2 0 0 -600 -500 -600 400
X DBG 14 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 8 -800 -200 200 R 40 40 2 1 B 
X PA1/T0OUT 9 -800 -300 200 R 40 40 2 1 B 
X PA2/DE0 10 -800 -400 200 R 40 40 2 1 B 
X PA3/CTS0 11 800 -400 200 L 40 40 2 1 B 
X PA4/RXD0 12 800 -300 200 L 40 40 2 1 B 
X PA5/TXD0 13 800 -200 200 L 40 40 2 1 B 
X PA6/SCL 1 -800 300 200 R 40 40 2 1 B 
X PA7/SDA 2 -800 200 200 R 40 40 2 1 B 
X PB0/ANA0 19 800 200 200 L 40 40 2 1 B 
X PB1/ANA1 18 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 20 800 300 200 L 40 40 2 1 B 
X RESET 3 -800 100 200 R 40 40 2 1 I I
X VREF 17 800 0 200 L 40 40 2 1 P 
X XIN 5 -800 0 200 R 40 40 2 1 P 
X XOUT 6 -800 -100 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X22PJ
# Package Name: PDIP-28
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X22PJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X22PJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-PDIP-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X22
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0/ANA0 28 800 500 200 L 40 40 2 1 B 
X PB1/ANA1 27 800 400 200 L 40 40 2 1 B 
X PB2/ANA2 26 800 300 200 L 40 40 2 1 B 
X PB3/ANA3 25 800 200 200 L 40 40 2 1 B 
X PB4/ANA4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X VREF 23 800 0 200 L 40 40 2 1 P 
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#
# Dev Name: Z8R0X22SJ
# Package Name: SOIC-28
# Dev Tech: R
# Dev Prefix: U
# Gate count = 2
#
DEF Z8R0X22SJ U 0 40 Y Y 2 L N
# Gate Name: -PWR
# Symbol Name: PWR2A2
F0 "U" 0 0 50 H V L B
F1 "Z8R0X22SJ" 0 -100 50 H V L B
F2 "z8encore8k_v10-SOIC-28" 0 150 50 H I C C
DRAW
X AVDD 21 -300 600 200 D 40 40 1 1 W 
X AVSS 22 -300 -500 200 U 40 40 1 1 W 
X VDD 8 -100 600 200 D 40 40 1 1 W 
X VSS 5 -100 -500 200 U 40 40 1 1 W 
# Gate Name: G$1
# Symbol Name: Z8*0X22
P 2 2 0 0 -600 600 600 600
P 2 2 0 0 600 600 600 -700
P 2 2 0 0 600 -700 -600 -700
P 2 2 0 0 -600 -700 -600 600
X DBG 20 800 -100 200 L 40 40 2 1 B 
X PA0/T0IN 13 -800 -500 200 R 40 40 2 1 B 
X PA1/T0OUT 14 -800 -600 200 R 40 40 2 1 B 
X PA2/DE0 15 800 -600 200 L 40 40 2 1 B 
X PA3/CTS0 16 800 -500 200 L 40 40 2 1 B 
X PA4/RXD0 17 800 -400 200 L 40 40 2 1 B 
X PA5/TXD0 18 800 -300 200 L 40 40 2 1 B 
X PA6/SCL 2 -800 400 200 R 40 40 2 1 B 
X PA7/SDA 3 -800 300 200 R 40 40 2 1 B 
X PB0/ANA0 28 800 500 200 L 40 40 2 1 B 
X PB1/ANA1 27 800 400 200 L 40 40 2 1 B 
X PB2/ANA2 26 800 300 200 L 40 40 2 1 B 
X PB3/ANA3 25 800 200 200 L 40 40 2 1 B 
X PB4/ANA4 24 800 100 200 L 40 40 2 1 B 
X PC0/T1IN 1 -800 500 200 R 40 40 2 1 B 
X PC1/T1OUT 19 800 -200 200 L 40 40 2 1 B 
X PC2/SS 12 -800 -400 200 R 40 40 2 1 B 
X PC3/SCK 11 -800 -300 200 R 40 40 2 1 B 
X PC4/MOSI 10 -800 -200 200 R 40 40 2 1 B 
X PC5/MISO 9 -800 -100 200 R 40 40 2 1 B 
X RESET 4 -800 200 200 R 40 40 2 1 I I
X VREF 23 800 0 200 L 40 40 2 1 P 
X XIN 6 -800 100 200 R 40 40 2 1 P 
X XOUT 7 -800 0 200 R 40 40 2 1 P 
ENDDRAW
ENDDEF

#End Library