EESchema-LIBRARY Version 2.3 29/04/2008-12:26:04 # Converted with eagle2kicad.ulp Version 0.9 # Device count = 10 # # Dev Name: _40PIN_Z8FXX21PM # Package Name: DIL40 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _40PIN_Z8FXX21PM U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX21-DIP F0 "U" -700 2100 50 H V L B F1 "_40PIN_Z8FXX21PM" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-DIL40" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 29 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 7 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 6 -900 1800 200 R 40 40 1 1 B X PA2/DE0 5 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 4 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 38 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 37 -900 1400 200 R 40 40 1 1 B X PA6/SCL 36 -900 1300 200 R 40 40 1 1 B X PA7/SDA 35 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 17 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 18 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 24 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 23 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 19 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 20 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 21 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 22 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 27 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 28 800 1800 200 L 40 40 1 1 B X PC2/SS* 8 800 1700 200 L 40 40 1 1 B X PC3/SCK 33 800 1600 200 L 40 40 1 1 B X PC4/MOSI 39 800 1500 200 L 40 40 1 1 B X PC5/MISO 3 800 1400 200 L 40 40 1 1 B X PC6/T2IN 30 800 1300 200 L 40 40 1 1 B X PD0 13 -900 1000 200 R 40 40 1 1 B X PD1 12 -900 900 200 R 40 40 1 1 B X PD3/DE1 2 -900 700 200 R 40 40 1 1 B X PD4/RXD1 1 -900 600 200 R 40 40 1 1 B X PD5/TXD1 40 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 34 -900 400 200 R 40 40 1 1 B X RESET* 9 -900 -1500 200 R 40 40 1 1 I X VREF 25 -900 100 200 R 40 40 1 1 P X XIN 15 -900 -1700 200 R 40 40 1 1 I X XOUT 14 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_40-PIN X AVDD@16 16 -400 600 200 D 40 40 2 1 W X AVSS@26 26 -400 -800 200 U 40 40 2 1 W X VDD@10 10 -100 600 200 D 40 40 2 1 W X VDD@31 31 0 600 200 D 40 40 2 1 W X VSS@11 11 -100 -800 200 U 40 40 2 1 W X VSS@32 32 0 -800 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _44PIN_Z8FXX21AN # Package Name: SQFP-S-10X10-44 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _44PIN_Z8FXX21AN U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX21 F0 "U" -700 2100 50 H V L B F1 "_44PIN_Z8FXX21AN" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-SQFP-S-10X10-44" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 15 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 34 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 33 -900 1800 200 R 40 40 1 1 B X PA2/DE0 32 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 31 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 25 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 24 -900 1400 200 R 40 40 1 1 B X PA6/SCL 23 -900 1300 200 R 40 40 1 1 B X PA7/SDA 22 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 2 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 3 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 9 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 8 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 4 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 5 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 6 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 7 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 13 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 14 800 1800 200 L 40 40 1 1 B X PC2/SS* 36 800 1700 200 L 40 40 1 1 B X PC3/SCK 20 800 1600 200 L 40 40 1 1 B X PC4/MOSI 26 800 1500 200 L 40 40 1 1 B X PC5/MISO 30 800 1400 200 L 40 40 1 1 B X PC6/T2IN 16 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 17 800 1200 200 L 40 40 1 1 B X PD0 41 -900 1000 200 R 40 40 1 1 B X PD1 40 -900 900 200 R 40 40 1 1 B X PD2 35 -900 800 200 R 40 40 1 1 B X PD3/DE1 29 -900 700 200 R 40 40 1 1 B X PD4/RXD1 28 -900 600 200 R 40 40 1 1 B X PD5/TXD1 27 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 21 -900 400 200 R 40 40 1 1 B X RESET* 37 -900 -1500 200 R 40 40 1 1 I X VREF 10 -900 100 200 R 40 40 1 1 P X XIN 43 -900 -1700 200 R 40 40 1 1 I X XOUT 42 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_44-PIN X AVDD@18,1 1 -500 600 200 D 40 40 2 1 W X AVSS@28,11 11 -500 -500 200 U 40 40 2 1 W X VDD@11,38 38 -200 600 200 D 40 40 2 1 W X VDD@17,44 44 -100 600 200 D 40 40 2 1 W X VDD@35,18 18 0 600 200 D 40 40 2 1 W X VSS@12,39 39 -200 -500 200 U 40 40 2 1 W X VSS@29.12 12 -100 -500 200 U 40 40 2 1 W X VSS@36,19 19 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _44PIN_Z8FXX21VN # Package Name: PLCC44S # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _44PIN_Z8FXX21VN U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX21 F0 "U" -700 2100 50 H V L B F1 "_44PIN_Z8FXX21VN" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-PLCC44S" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 32 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 7 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 6 -900 1800 200 R 40 40 1 1 B X PA2/DE0 5 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 4 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 42 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 41 -900 1400 200 R 40 40 1 1 B X PA6/SCL 40 -900 1300 200 R 40 40 1 1 B X PA7/SDA 39 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 19 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 20 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 26 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 25 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 21 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 22 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 23 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 24 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 30 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 31 800 1800 200 L 40 40 1 1 B X PC2/SS* 9 800 1700 200 L 40 40 1 1 B X PC3/SCK 37 800 1600 200 L 40 40 1 1 B X PC4/MOSI 43 800 1500 200 L 40 40 1 1 B X PC5/MISO 3 800 1400 200 L 40 40 1 1 B X PC6/T2IN 33 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 34 800 1200 200 L 40 40 1 1 B X PD0 14 -900 1000 200 R 40 40 1 1 B X PD1 13 -900 900 200 R 40 40 1 1 B X PD2 8 -900 800 200 R 40 40 1 1 B X PD3/DE1 2 -900 700 200 R 40 40 1 1 B X PD4/RXD1 1 -900 600 200 R 40 40 1 1 B X PD5/TXD1 44 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 38 -900 400 200 R 40 40 1 1 B X RESET* 10 -900 -1500 200 R 40 40 1 1 I X VREF 27 -900 100 200 R 40 40 1 1 P X XIN 16 -900 -1700 200 R 40 40 1 1 I X XOUT 15 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_44-PIN X AVDD@18,1 18 -500 600 200 D 40 40 2 1 W X AVSS@28,11 28 -500 -500 200 U 40 40 2 1 W X VDD@11,38 11 -200 600 200 D 40 40 2 1 W X VDD@17,44 17 -100 600 200 D 40 40 2 1 W X VDD@35,18 35 0 600 200 D 40 40 2 1 W X VSS@12,39 12 -200 -500 200 U 40 40 2 1 W X VSS@29.12 29 -100 -500 200 U 40 40 2 1 W X VSS@36,19 36 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _44PIN_Z8FXX21VN-SMS # Package Name: PLCCSM44 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _44PIN_Z8FXX21VN-SMS U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX21 F0 "U" -700 2100 50 H V L B F1 "_44PIN_Z8FXX21VN-SMS" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-PLCCSM44" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 32 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 7 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 6 -900 1800 200 R 40 40 1 1 B X PA2/DE0 5 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 4 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 42 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 41 -900 1400 200 R 40 40 1 1 B X PA6/SCL 40 -900 1300 200 R 40 40 1 1 B X PA7/SDA 39 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 19 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 20 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 26 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 25 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 21 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 22 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 23 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 24 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 30 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 31 800 1800 200 L 40 40 1 1 B X PC2/SS* 9 800 1700 200 L 40 40 1 1 B X PC3/SCK 37 800 1600 200 L 40 40 1 1 B X PC4/MOSI 43 800 1500 200 L 40 40 1 1 B X PC5/MISO 3 800 1400 200 L 40 40 1 1 B X PC6/T2IN 33 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 34 800 1200 200 L 40 40 1 1 B X PD0 14 -900 1000 200 R 40 40 1 1 B X PD1 13 -900 900 200 R 40 40 1 1 B X PD2 8 -900 800 200 R 40 40 1 1 B X PD3/DE1 2 -900 700 200 R 40 40 1 1 B X PD4/RXD1 1 -900 600 200 R 40 40 1 1 B X PD5/TXD1 44 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 38 -900 400 200 R 40 40 1 1 B X RESET* 10 -900 -1500 200 R 40 40 1 1 I X VREF 27 -900 100 200 R 40 40 1 1 P X XIN 16 -900 -1700 200 R 40 40 1 1 I X XOUT 15 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_44-PIN X AVDD@18,1 18 -500 600 200 D 40 40 2 1 W X AVSS@28,11 28 -500 -500 200 U 40 40 2 1 W X VDD@11,38 11 -200 600 200 D 40 40 2 1 W X VDD@17,44 17 -100 600 200 D 40 40 2 1 W X VDD@35,18 35 0 600 200 D 40 40 2 1 W X VSS@12,39 12 -200 -500 200 U 40 40 2 1 W X VSS@29.12 29 -100 -500 200 U 40 40 2 1 W X VSS@36,19 36 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _44PIN_Z8FXX21VN-THS # Package Name: PLCC-S44 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _44PIN_Z8FXX21VN-THS U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX21 F0 "U" -700 2100 50 H V L B F1 "_44PIN_Z8FXX21VN-THS" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-PLCC-S44" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 32 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 7 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 6 -900 1800 200 R 40 40 1 1 B X PA2/DE0 5 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 4 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 42 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 41 -900 1400 200 R 40 40 1 1 B X PA6/SCL 40 -900 1300 200 R 40 40 1 1 B X PA7/SDA 39 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 19 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 20 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 26 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 25 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 21 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 22 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 23 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 24 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 30 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 31 800 1800 200 L 40 40 1 1 B X PC2/SS* 9 800 1700 200 L 40 40 1 1 B X PC3/SCK 37 800 1600 200 L 40 40 1 1 B X PC4/MOSI 43 800 1500 200 L 40 40 1 1 B X PC5/MISO 3 800 1400 200 L 40 40 1 1 B X PC6/T2IN 33 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 34 800 1200 200 L 40 40 1 1 B X PD0 14 -900 1000 200 R 40 40 1 1 B X PD1 13 -900 900 200 R 40 40 1 1 B X PD2 8 -900 800 200 R 40 40 1 1 B X PD3/DE1 2 -900 700 200 R 40 40 1 1 B X PD4/RXD1 1 -900 600 200 R 40 40 1 1 B X PD5/TXD1 44 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 38 -900 400 200 R 40 40 1 1 B X RESET* 10 -900 -1500 200 R 40 40 1 1 I X VREF 27 -900 100 200 R 40 40 1 1 P X XIN 16 -900 -1700 200 R 40 40 1 1 I X XOUT 15 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_44-PIN X AVDD@18,1 18 -500 600 200 D 40 40 2 1 W X AVSS@28,11 28 -500 -500 200 U 40 40 2 1 W X VDD@11,38 11 -200 600 200 D 40 40 2 1 W X VDD@17,44 17 -100 600 200 D 40 40 2 1 W X VDD@35,18 35 0 600 200 D 40 40 2 1 W X VSS@12,39 12 -200 -500 200 U 40 40 2 1 W X VSS@29.12 29 -100 -500 200 U 40 40 2 1 W X VSS@36,19 36 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _64PIN_Z8FXX22AR # Package Name: SQFP-S-10X10-64 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _64PIN_Z8FXX22AR U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX22 F0 "U" -700 2100 50 H V L B F1 "_64PIN_Z8FXX22AR" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-SQFP-S-10X10-64" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 19 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 49 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 48 -900 1800 200 R 40 40 1 1 B X PA2/DE0 47 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 46 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 35 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 34 -900 1400 200 R 40 40 1 1 B X PA6/SCL 33 -900 1300 200 R 40 40 1 1 B X PA7/SDA 32 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 5 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 6 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 12 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 11 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 7 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 8 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 9 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 10 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 17 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 18 800 1800 200 L 40 40 1 1 B X PC2/SS* 51 800 1700 200 L 40 40 1 1 B X PC3/SCK 30 800 1600 200 L 40 40 1 1 B X PC4/MOSI 38 800 1500 200 L 40 40 1 1 B X PC5/MISO 42 800 1400 200 L 40 40 1 1 B X PC6/T2IN 20 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 21 800 1200 200 L 40 40 1 1 B X PD0 62 -900 1000 200 R 40 40 1 1 B X PD1 61 -900 900 200 R 40 40 1 1 B X PD2 50 -900 800 200 R 40 40 1 1 B X PD3/DE1 41 -900 700 200 R 40 40 1 1 B X PD4/RXD1 40 -900 600 200 R 40 40 1 1 B X PD5/TXD1 39 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 31 -900 400 200 R 40 40 1 1 B X PD7/RCOUT 29 -900 300 200 R 40 40 1 1 B X PE0 59 800 1000 200 L 40 40 1 1 B X PE1 58 800 900 200 L 40 40 1 1 B X PE2 57 800 800 200 L 40 40 1 1 B X PE3 55 800 700 200 L 40 40 1 1 B X PE4 54 800 600 200 L 40 40 1 1 B X PE5 27 800 500 200 L 40 40 1 1 B X PE6 26 800 400 200 L 40 40 1 1 B X PE7 25 800 300 200 L 40 40 1 1 B X PF7 43 800 -600 200 L 40 40 1 1 B X PG3 23 800 -1100 200 L 40 40 1 1 B X PH0/ANA8 3 -900 -1000 200 R 40 40 1 1 B X PH1/ANA9 4 -900 -1100 200 R 40 40 1 1 B X PH2/ANA10 13 -900 -1200 200 R 40 40 1 1 B X PH3/ANA11 14 -900 -1300 200 R 40 40 1 1 B X RESET* 52 -900 -1500 200 R 40 40 1 1 I X VREF 15 -900 100 200 R 40 40 1 1 P X XIN 64 -900 -1700 200 R 40 40 1 1 I X XOUT 63 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_64-PIN X AVDD@2 2 -900 600 200 D 40 40 2 1 W X AVSS@16 16 -900 -500 200 U 40 40 2 1 W X VDD@22 22 -400 600 200 D 40 40 2 1 W X VDD@24 24 -300 600 200 D 40 40 2 1 W X VDD@37 37 -200 600 200 D 40 40 2 1 W X VDD@44 44 -100 600 200 D 40 40 2 1 W X VDD@53 53 0 600 200 D 40 40 2 1 W X VSS@1 1 -500 -500 200 U 40 40 2 1 W X VSS@28 28 -400 -500 200 U 40 40 2 1 W X VSS@36 36 -300 -500 200 U 40 40 2 1 W X VSS@45 45 -200 -500 200 U 40 40 2 1 W X VSS@56 56 -100 -500 200 U 40 40 2 1 W X VSS@60 60 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _68PIN_Z8FXX22VS # Package Name: PLCC68S # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _68PIN_Z8FXX22VS U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX22 F0 "U" -700 2100 50 H V L B F1 "_68PIN_Z8FXX22VS" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-PLCC68S" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 47 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 10 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 9 -900 1800 200 R 40 40 1 1 B X PA2/DE0 8 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 7 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 63 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 62 -900 1400 200 R 40 40 1 1 B X PA6/SCL 61 -900 1300 200 R 40 40 1 1 B X PA7/SDA 60 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 31 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 32 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 38 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 37 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 33 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 34 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 35 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 36 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 45 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 46 800 1800 200 L 40 40 1 1 B X PC2/SS* 12 800 1700 200 L 40 40 1 1 B X PC3/SCK 58 800 1600 200 L 40 40 1 1 B X PC4/MOSI 67 800 1500 200 L 40 40 1 1 B X PC5/MISO 3 800 1400 200 L 40 40 1 1 B X PC6/T2IN 48 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 49 800 1200 200 L 40 40 1 1 B X PD0 24 -900 1000 200 R 40 40 1 1 B X PD1 23 -900 900 200 R 40 40 1 1 B X PD2 11 -900 800 200 R 40 40 1 1 B X PD3/DE1 2 -900 700 200 R 40 40 1 1 B X PD4/RXD1 1 -900 600 200 R 40 40 1 1 B X PD5/TXD1 68 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 59 -900 400 200 R 40 40 1 1 B X PD7/RCOUT 57 -900 300 200 R 40 40 1 1 B X PE0 20 800 1000 200 L 40 40 1 1 B X PE1 19 800 900 200 L 40 40 1 1 B X PE2 18 800 800 200 L 40 40 1 1 B X PE3 16 800 700 200 L 40 40 1 1 B X PE4 15 800 600 200 L 40 40 1 1 B X PE5 55 800 500 200 L 40 40 1 1 B X PE6 54 800 400 200 L 40 40 1 1 B X PE7 53 800 300 200 L 40 40 1 1 B X PF7 4 800 -600 200 L 40 40 1 1 B X PG3 51 800 -1100 200 L 40 40 1 1 B X PH0/ANA8 29 -900 -1000 200 R 40 40 1 1 B X PH1/ANA9 30 -900 -1100 200 R 40 40 1 1 B X PH2/ANA10 39 -900 -1200 200 R 40 40 1 1 B X PH3/ANA11 40 -900 -1300 200 R 40 40 1 1 B X RESET* 13 -900 -1500 200 R 40 40 1 1 I X VREF 41 -900 100 200 R 40 40 1 1 P X XIN 26 -900 -1700 200 R 40 40 1 1 I X XOUT 25 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_68-PIN X AVDD@28 28 -900 600 200 D 40 40 2 1 W X AVSS@42 42 -1000 -500 200 U 40 40 2 1 W X AVSS@43 43 -900 -500 200 U 40 40 2 1 W X VDD@5 5 -600 600 200 D 40 40 2 1 W X VDD@14 14 -500 600 200 D 40 40 2 1 W X VDD@22 22 -400 600 200 D 40 40 2 1 W X VDD@50 50 -300 600 200 D 40 40 2 1 W X VDD@52 52 -200 600 200 D 40 40 2 1 W X VDD@65 65 -100 600 200 D 40 40 2 1 W X VDD@66 66 0 600 200 D 40 40 2 1 W X VSS@6 6 -600 -500 200 U 40 40 2 1 W X VSS@17 17 -500 -500 200 U 40 40 2 1 W X VSS@21 21 -400 -500 200 U 40 40 2 1 W X VSS@27 27 -300 -500 200 U 40 40 2 1 W X VSS@44 44 -200 -500 200 U 40 40 2 1 W X VSS@56 56 -100 -500 200 U 40 40 2 1 W X VSS@64 64 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _68PIN_Z8FXX22VS-SMS # Package Name: PLCCSM68 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _68PIN_Z8FXX22VS-SMS U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX22 F0 "U" -700 2100 50 H V L B F1 "_68PIN_Z8FXX22VS-SMS" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-PLCCSM68" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 47 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 10 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 9 -900 1800 200 R 40 40 1 1 B X PA2/DE0 8 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 7 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 63 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 62 -900 1400 200 R 40 40 1 1 B X PA6/SCL 61 -900 1300 200 R 40 40 1 1 B X PA7/SDA 60 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 31 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 32 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 38 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 37 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 33 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 34 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 35 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 36 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 45 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 46 800 1800 200 L 40 40 1 1 B X PC2/SS* 12 800 1700 200 L 40 40 1 1 B X PC3/SCK 58 800 1600 200 L 40 40 1 1 B X PC4/MOSI 67 800 1500 200 L 40 40 1 1 B X PC5/MISO 3 800 1400 200 L 40 40 1 1 B X PC6/T2IN 48 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 49 800 1200 200 L 40 40 1 1 B X PD0 24 -900 1000 200 R 40 40 1 1 B X PD1 23 -900 900 200 R 40 40 1 1 B X PD2 11 -900 800 200 R 40 40 1 1 B X PD3/DE1 2 -900 700 200 R 40 40 1 1 B X PD4/RXD1 1 -900 600 200 R 40 40 1 1 B X PD5/TXD1 68 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 59 -900 400 200 R 40 40 1 1 B X PD7/RCOUT 57 -900 300 200 R 40 40 1 1 B X PE0 20 800 1000 200 L 40 40 1 1 B X PE1 19 800 900 200 L 40 40 1 1 B X PE2 18 800 800 200 L 40 40 1 1 B X PE3 16 800 700 200 L 40 40 1 1 B X PE4 15 800 600 200 L 40 40 1 1 B X PE5 55 800 500 200 L 40 40 1 1 B X PE6 54 800 400 200 L 40 40 1 1 B X PE7 53 800 300 200 L 40 40 1 1 B X PF7 4 800 -600 200 L 40 40 1 1 B X PG3 51 800 -1100 200 L 40 40 1 1 B X PH0/ANA8 29 -900 -1000 200 R 40 40 1 1 B X PH1/ANA9 30 -900 -1100 200 R 40 40 1 1 B X PH2/ANA10 39 -900 -1200 200 R 40 40 1 1 B X PH3/ANA11 40 -900 -1300 200 R 40 40 1 1 B X RESET* 13 -900 -1500 200 R 40 40 1 1 I X VREF 41 -900 100 200 R 40 40 1 1 P X XIN 26 -900 -1700 200 R 40 40 1 1 I X XOUT 25 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_68-PIN X AVDD@28 28 -900 600 200 D 40 40 2 1 W X AVSS@42 42 -1000 -500 200 U 40 40 2 1 W X AVSS@43 43 -900 -500 200 U 40 40 2 1 W X VDD@5 5 -600 600 200 D 40 40 2 1 W X VDD@14 14 -500 600 200 D 40 40 2 1 W X VDD@22 22 -400 600 200 D 40 40 2 1 W X VDD@50 50 -300 600 200 D 40 40 2 1 W X VDD@52 52 -200 600 200 D 40 40 2 1 W X VDD@65 65 -100 600 200 D 40 40 2 1 W X VDD@66 66 0 600 200 D 40 40 2 1 W X VSS@6 6 -600 -500 200 U 40 40 2 1 W X VSS@17 17 -500 -500 200 U 40 40 2 1 W X VSS@21 21 -400 -500 200 U 40 40 2 1 W X VSS@27 27 -300 -500 200 U 40 40 2 1 W X VSS@44 44 -200 -500 200 U 40 40 2 1 W X VSS@56 56 -100 -500 200 U 40 40 2 1 W X VSS@64 64 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _68PIN_Z8FXX22VS-THS # Package Name: PLCC-S68 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _68PIN_Z8FXX22VS-THS U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX22 F0 "U" -700 2100 50 H V L B F1 "_68PIN_Z8FXX22VS-THS" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-PLCC-S68" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 47 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 10 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 9 -900 1800 200 R 40 40 1 1 B X PA2/DE0 8 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 7 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 63 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 62 -900 1400 200 R 40 40 1 1 B X PA6/SCL 61 -900 1300 200 R 40 40 1 1 B X PA7/SDA 60 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 31 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 32 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 38 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 37 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 33 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 34 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 35 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 36 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 45 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 46 800 1800 200 L 40 40 1 1 B X PC2/SS* 12 800 1700 200 L 40 40 1 1 B X PC3/SCK 58 800 1600 200 L 40 40 1 1 B X PC4/MOSI 67 800 1500 200 L 40 40 1 1 B X PC5/MISO 3 800 1400 200 L 40 40 1 1 B X PC6/T2IN 48 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 49 800 1200 200 L 40 40 1 1 B X PD0 24 -900 1000 200 R 40 40 1 1 B X PD1 23 -900 900 200 R 40 40 1 1 B X PD2 11 -900 800 200 R 40 40 1 1 B X PD3/DE1 2 -900 700 200 R 40 40 1 1 B X PD4/RXD1 1 -900 600 200 R 40 40 1 1 B X PD5/TXD1 68 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 59 -900 400 200 R 40 40 1 1 B X PD7/RCOUT 57 -900 300 200 R 40 40 1 1 B X PE0 20 800 1000 200 L 40 40 1 1 B X PE1 19 800 900 200 L 40 40 1 1 B X PE2 18 800 800 200 L 40 40 1 1 B X PE3 16 800 700 200 L 40 40 1 1 B X PE4 15 800 600 200 L 40 40 1 1 B X PE5 55 800 500 200 L 40 40 1 1 B X PE6 54 800 400 200 L 40 40 1 1 B X PE7 53 800 300 200 L 40 40 1 1 B X PF7 4 800 -600 200 L 40 40 1 1 B X PG3 51 800 -1100 200 L 40 40 1 1 B X PH0/ANA8 29 -900 -1000 200 R 40 40 1 1 B X PH1/ANA9 30 -900 -1100 200 R 40 40 1 1 B X PH2/ANA10 39 -900 -1200 200 R 40 40 1 1 B X PH3/ANA11 40 -900 -1300 200 R 40 40 1 1 B X RESET* 13 -900 -1500 200 R 40 40 1 1 I X VREF 41 -900 100 200 R 40 40 1 1 P X XIN 26 -900 -1700 200 R 40 40 1 1 I X XOUT 25 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_68-PIN X AVDD@28 28 -900 600 200 D 40 40 2 1 W X AVSS@42 42 -1000 -500 200 U 40 40 2 1 W X AVSS@43 43 -900 -500 200 U 40 40 2 1 W X VDD@5 5 -600 600 200 D 40 40 2 1 W X VDD@14 14 -500 600 200 D 40 40 2 1 W X VDD@22 22 -400 600 200 D 40 40 2 1 W X VDD@50 50 -300 600 200 D 40 40 2 1 W X VDD@52 52 -200 600 200 D 40 40 2 1 W X VDD@65 65 -100 600 200 D 40 40 2 1 W X VDD@66 66 0 600 200 D 40 40 2 1 W X VSS@6 6 -600 -500 200 U 40 40 2 1 W X VSS@17 17 -500 -500 200 U 40 40 2 1 W X VSS@21 21 -400 -500 200 U 40 40 2 1 W X VSS@27 27 -300 -500 200 U 40 40 2 1 W X VSS@44 44 -200 -500 200 U 40 40 2 1 W X VSS@56 56 -100 -500 200 U 40 40 2 1 W X VSS@64 64 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF # # Dev Name: _80PIN_Z8FXX23FT # Package Name: SQFP-R-14X20-80 # Dev Tech: '' # Dev Prefix: U # Gate count = 2 # DEF _80PIN_Z8FXX23FT U 0 40 Y Y 2 L N # Gate Name: G$1 # Symbol Name: Z8FXX23 F0 "U" -700 2100 50 H V L B F1 "_80PIN_Z8FXX23FT" -700 -2100 50 H V L B F2 "zilog-z8-encore-v1_2a-SQFP-R-14X20-80" 0 150 50 H I C C DRAW P 2 1 0 0 -700 -1900 600 -1900 P 2 1 0 0 600 -1900 600 2000 P 2 1 0 0 600 2000 -700 2000 P 2 1 0 0 -700 2000 -700 -1900 X DBG 44 800 -1800 200 L 40 40 1 1 B X PA0/T0IN 1 -900 1900 200 R 40 40 1 1 B X PA1/T0OUT 80 -900 1800 200 R 40 40 1 1 B X PA2/DE0 79 -900 1700 200 R 40 40 1 1 B X PA3/CTS0* 78 -900 1600 200 R 40 40 1 1 B X PA4/RXD0 67 -900 1500 200 R 40 40 1 1 B X PA5/TXD0 66 -900 1400 200 R 40 40 1 1 B X PA6/SCL 65 -900 1300 200 R 40 40 1 1 B X PA7/SDA 64 -900 1200 200 R 40 40 1 1 B X PB0/ANA0 29 -900 -100 200 R 40 40 1 1 B X PB1/ANA1 30 -900 -200 200 R 40 40 1 1 B X PB2/ANA2 36 -900 -300 200 R 40 40 1 1 B X PB3/ANA3 35 -900 -400 200 R 40 40 1 1 B X PB4/ANA4 31 -900 -500 200 R 40 40 1 1 B X PB5/ANA5 32 -900 -600 200 R 40 40 1 1 B X PB6/ANA6 33 -900 -700 200 R 40 40 1 1 B X PB7/ANA7 34 -900 -800 200 R 40 40 1 1 B X PC0/T1IN 42 800 1900 200 L 40 40 1 1 B X PC1/T1OUT 43 800 1800 200 L 40 40 1 1 B X PC2/SS* 3 800 1700 200 L 40 40 1 1 B X PC3/SCK 62 800 1600 200 L 40 40 1 1 B X PC4/MOSI 70 800 1500 200 L 40 40 1 1 B X PC5/MISO 74 800 1400 200 L 40 40 1 1 B X PC6/T2IN 45 800 1300 200 L 40 40 1 1 B X PC7/T2OUT 46 800 1200 200 L 40 40 1 1 B X PD0 22 -900 1000 200 R 40 40 1 1 B X PD1 21 -900 900 200 R 40 40 1 1 B X PD2 2 -900 800 200 R 40 40 1 1 B X PD3/DE1 73 -900 700 200 R 40 40 1 1 B X PD4/RXD1 72 -900 600 200 R 40 40 1 1 B X PD5/TXD1 71 -900 500 200 R 40 40 1 1 B X PD6/CTS1* 63 -900 400 200 R 40 40 1 1 B X PD7/RCOUT 61 -900 300 200 R 40 40 1 1 B X PE0 15 800 1000 200 L 40 40 1 1 B X PE1 14 800 900 200 L 40 40 1 1 B X PE2 13 800 800 200 L 40 40 1 1 B X PE3 11 800 700 200 L 40 40 1 1 B X PE4 10 800 600 200 L 40 40 1 1 B X PE5 56 800 500 200 L 40 40 1 1 B X PE6 55 800 400 200 L 40 40 1 1 B X PE7 54 800 300 200 L 40 40 1 1 B X PF0 19 800 100 200 L 40 40 1 1 B X PF1 18 800 0 200 L 40 40 1 1 B X PF2 17 800 -100 200 L 40 40 1 1 B X PF3 9 800 -200 200 L 40 40 1 1 B X PF4 8 800 -300 200 L 40 40 1 1 B X PF5 7 800 -400 200 L 40 40 1 1 B X PF6 4 800 -500 200 L 40 40 1 1 B X PF7 75 800 -600 200 L 40 40 1 1 B X PG0 60 800 -800 200 L 40 40 1 1 B X PG1 58 800 -900 200 L 40 40 1 1 B X PG2 57 800 -1000 200 L 40 40 1 1 B X PG3 52 800 -1100 200 L 40 40 1 1 B X PG4 51 800 -1200 200 L 40 40 1 1 B X PG5 50 800 -1300 200 L 40 40 1 1 B X PG6 49 800 -1400 200 L 40 40 1 1 B X PG7 47 800 -1500 200 L 40 40 1 1 B X PH0/ANA8 27 -900 -1000 200 R 40 40 1 1 B X PH1/ANA9 28 -900 -1100 200 R 40 40 1 1 B X PH2/ANA10 37 -900 -1200 200 R 40 40 1 1 B X PH3/ANA11 38 -900 -1300 200 R 40 40 1 1 B X RESET* 5 -900 -1500 200 R 40 40 1 1 I X VREF 39 -900 100 200 R 40 40 1 1 P X XIN 24 -900 -1700 200 R 40 40 1 1 I X XOUT 23 -900 -1800 200 R 40 40 1 1 O # Gate Name: P # Symbol Name: PWR_80-PIN X AVDD@26 26 -900 600 200 D 40 40 2 1 W X AVSS@40 40 -900 -500 200 U 40 40 2 1 W X VDD@6 6 -500 600 200 D 40 40 2 1 W X VDD@20 20 -400 600 200 D 40 40 2 1 W X VDD@48 48 -300 600 200 D 40 40 2 1 W X VDD@53 53 -200 600 200 D 40 40 2 1 W X VDD@69 69 -100 600 200 D 40 40 2 1 W X VDD@76 76 0 600 200 D 40 40 2 1 W X VSS@12 12 -600 -500 200 U 40 40 2 1 W X VSS@16 16 -500 -500 200 U 40 40 2 1 W X VSS@25 25 -400 -500 200 U 40 40 2 1 W X VSS@41 41 -300 -500 200 U 40 40 2 1 W X VSS@59 59 -200 -500 200 U 40 40 2 1 W X VSS@68 68 -100 -500 200 U 40 40 2 1 W X VSS@77 77 0 -500 200 U 40 40 2 1 W ENDDRAW ENDDEF #End Library